diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2018-06-07 19:27:44 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-29 11:38:53 -0700 |
| commit | fde9042dbac2a273f5607e659b8e5a98c301e42b (patch) | |
| tree | 9321c705dbbf5159f9b50e8520e5fdd1f39f7be3 /chip/npcx/gpio_chip-npcx7.h | |
| parent | 47a1c1a0427400d5a0f5def8f69fcb70bbb4f4e7 (diff) | |
| download | chrome-ec-fde9042dbac2a273f5607e659b8e5a98c301e42b.tar.gz | |
npcx: gpio: bypass for excessive power consumption on low-voltage IOs.
It was found that for npcx ec's GPIOs that support low-voltage input,
there is an excessive power consumption when they are selected to
low-voltage mode and their Vin is 1.8V.
To bypass this issue when the chip enters deep sleep where current is
important, this CL includes:
1. Disable GPIOs without ISR which are selected to 1.8V and not i2c
ports in gpio_pre_init().
2. Disable input buffer of 1.8V i2c ports before entering deep sleep.
3. Enable input buffer of 1.8V i2c ports after ec wakes up.
BRANCH=none
BUG=b:110170824
TEST=No build errors for npcx ec series. Measured power consumption on
yorp and it saved ~1.3mA current after applying this patch at S0ix. Run
stress test on poppy and no symptom found. Remove CONFIG_LOW_POWER_IDLE
in board driver and no symptom occurred on poppy and yorp.
Change-Id: Iaf66c81ca16104839734ba19492f2061113dafb3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1098864
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/npcx/gpio_chip-npcx7.h')
| -rw-r--r-- | chip/npcx/gpio_chip-npcx7.h | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h index 23f18b8700..e0081b761a 100644 --- a/chip/npcx/gpio_chip-npcx7.h +++ b/chip/npcx/gpio_chip-npcx7.h @@ -100,7 +100,6 @@ #define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0) #define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1) #define NPCX_WUI_GPIO_F_4 WUI(1, MIWU_GROUP_2, 2) -#define NPCX_WUI_GPIO_1_3 WUI(1, MIWU_GROUP_2, 3) #define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4) #define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5) #define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6) @@ -151,7 +150,6 @@ #define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2) #define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3) #define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4) -#define NPCX_WUI_GPIO_6_5 WUI(1, MIWU_GROUP_7, 5) #ifndef NPCX_EXT32K_OSC_SUPPORT #define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if support*/ #endif @@ -169,7 +167,17 @@ /* Group F: NPCX_IRQ_WKINTFG_2 */ #define NPCX_WUI_GPIO_F_1 WUI(2, MIWU_GROUP_6, 1) #define NPCX_WUI_GPIO_F_2 WUI(2, MIWU_GROUP_6, 2) -#define NPCX_WUI_GPIO_B_6 WUI(2, MIWU_GROUP_6, 6) + +/* Others GPO without MIWU functionality */ +#define NPCX_WUI_GPIO_1_2 WUI_NONE +#define NPCX_WUI_GPIO_1_3 WUI_NONE /* Software strap pin GP_SEL1_L */ +#define NPCX_WUI_GPIO_3_2 WUI_NONE +#define NPCX_WUI_GPIO_3_5 WUI_NONE +#define NPCX_WUI_GPIO_6_5 WUI_NONE /* Software strap pin FLPRG_L */ +#define NPCX_WUI_GPIO_6_6 WUI_NONE +#define NPCX_WUI_GPIO_7_7 WUI_NONE +#define NPCX_WUI_GPIO_B_6 WUI_NONE /* Software strap pin GP_SEL0_L */ +#define NPCX_WUI_GPIO_D_6 WUI_NONE /*****************************************************************************/ /* Macro functions for Alternative mapping table */ |