diff options
author | Mulin Chao <mlchao@nuvoton.com> | 2017-05-05 17:38:56 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2017-05-12 20:58:09 -0700 |
commit | f9c201e93c45f008b79ce63c1ec276ede05146f0 (patch) | |
tree | b8c8f927e2ce59370b00dedc12129b45d308aa46 /chip/npcx/flash.c | |
parent | a30bb73e783cac43d9d7583a38bfe72bb2d41478 (diff) | |
download | chrome-ec-f9c201e93c45f008b79ce63c1ec276ede05146f0.tar.gz |
npcx: flash: Add write-protect support for internal flash of npcx7 ecstabilize-9554.B
In order to support write-protect mechanism for the internal flash
of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by
controlling the WP_L pin of internal flash. During ec initialization
or any utilities related to access status registers, we'll protect them
if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we
only can unlock write protection of internal flash by rebooting ec.
This CL also includes:
1. Add protect_range array of npcx7's internal flash (W25Q80) for
write-protect mechanism.
2. Add bypass of bit 7 of DEVCNT.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series. (Besides gru)
Build poppy board and upload FW to platform. No issues found.
Passed flash write-protect checking on npcx796f evb.
Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/501727
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/flash.c')
-rw-r--r-- | chip/npcx/flash.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c index 457cbf4c91..9c73bbdb3c 100644 --- a/chip/npcx/flash.c +++ b/chip/npcx/flash.c @@ -191,6 +191,18 @@ static uint8_t flash_get_status2(void) return ret; } +#ifdef NPCX_INT_FLASH_SUPPORT +static void flash_protect_int_flash(int enable) +{ + /* + * Please notice the type of WP_IF bit is R/W1S. Once it's set, + * only rebooting EC can clear it. + */ + if (enable && !IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF)) + SET_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF); +} +#endif + #ifdef CONFIG_HOSTCMD_FLASH_SPI_INFO void flash_get_mfr_dev_id(uint8_t *dest) @@ -263,6 +275,14 @@ static int flash_set_status_for_prot(int reg1, int reg2) flash_uma_lock(0); } + /* + * If WP# is active and ec doesn't protect the status registers of + * internal spi-flash, protect it now before setting them. + */ +#ifdef NPCX_INT_FLASH_SUPPORT + flash_protect_int_flash(!gpio_get_level(GPIO_WP_L)); +#endif + /* Lock physical flash operations */ flash_lock_mapped_storage(1); @@ -308,6 +328,14 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes) uint8_t sr1, sr2; int rv = EC_SUCCESS; + /* + * If WP# is active and ec doesn't protect the status registers of + * internal spi-flash, protect it now. + */ +#ifdef NPCX_INT_FLASH_SUPPORT + flash_protect_int_flash(!gpio_get_level(GPIO_WP_L)); +#endif + sr1 = flash_get_status1(); sr2 = flash_get_status2(); @@ -647,6 +675,14 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) int flash_pre_init(void) { + /* + * Protect status registers of internal spi-flash if WP# is active + * during ec initialization. + */ +#ifdef NPCX_INT_FLASH_SUPPORT + flash_protect_int_flash(!gpio_get_level(GPIO_WP_L)); +#endif + /* Enable FIU interface */ flash_pinmux(1); |