diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-07 14:12:57 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:33 -0700 |
| commit | fe77303bec6c78786a9df1dbdb33af64787e20c8 (patch) | |
| tree | 772d2fbb53178121ddca0dfbafbd304ee075ce1b /chip/npcx/config_flash_layout.h | |
| parent | 1167cad6a88e45bbf6a5599f19d018cd6a8b5233 (diff) | |
| download | chrome-ec-fe77303bec6c78786a9df1dbdb33af64787e20c8.tar.gz | |
cleanup: Remove redundant FLASH_SIZE CONFIGs
Since there is no more concept of a flash region belonging only to the
EC, we only need one FLASH_SIZE config, which represents the actual
physical size of flash.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6
Reviewed-on: https://chromium-review.googlesource.com/297824
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/config_flash_layout.h')
| -rw-r--r-- | chip/npcx/config_flash_layout.h | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h index efdfdf171e..5d296c4836 100644 --- a/chip/npcx/config_flash_layout.h +++ b/chip/npcx/config_flash_layout.h @@ -20,14 +20,20 @@ #define CONFIG_MAPPED_STORAGE_BASE 0x64000000 #undef CONFIG_FLASH_PSTATE -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_SPI_FLASH_SIZE - 0x40000) +/* + * On NPCX, the first 256KB of external SPI storage belongs to the EC, + * regardless of the actual size of external SPI. + */ +#define NPCX_EC_FLASH_SIZE 0x40000 + +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_SPI_FLASH_SIZE - 0x20000) +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000 #define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 /* Size of one firmware image in flash */ #ifndef CONFIG_FW_IMAGE_SIZE -#define CONFIG_FW_IMAGE_SIZE (CONFIG_FLASH_PHYSICAL_SIZE / 2) +#define CONFIG_FW_IMAGE_SIZE (96 * 1024) /* 96 KB for FW images */ #endif /* Header support which is used by booter to copy FW from flash to code ram */ @@ -40,12 +46,11 @@ /* RO firmware offset in flash */ #define CONFIG_RO_MEM_OFF CONFIG_RO_HDR_SIZE -#define CONFIG_RO_SIZE (96 * 1024) /* 96KB for RO FW */ -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE +#define CONFIG_RO_SIZE CONFIG_FW_IMAGE_SIZE /* RW firmware offset in flash */ #define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF -#define CONFIG_RW_SIZE (96 * 1024) /* 96KB for RW FW */ +#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE /* The storage offset of ec.R*.flat which is used for CONFIG_CDRAM_ARCH */ #define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE |