WIP - Nuvoton 30-Jan patch

Issues fixed on 0216:
1.Modified CONFIG_KEYBOARD_COL2_INVERTED support in keyboard_raw.c
2.Modified warm_reset checking in gpio.c
3.Modified system_get_chip_name in system.c for package info.
4.Modified fan.c and pwm.c for:
● If the DCRn value is greater than the CTRn value, the PWM_n signal is always low.
● Fan stall condition event:
  If the measured fan speed is lower than the lowLimit value (unless the Fan Speed Low Limit value is 0) or in case of erroneous measurement, the userCallback is called.
5. Change cycle_pluses to 480 in board.c

Issues fixed:
1. Jump data at top of RAM is getting corrupted.  Changed the flag to
RESET_FLAG_RESET_PIN.  Added a workaround method to fix VCC1_RST
issue.

2. Hibernate wake need to report whether wake reason was GPIO or RTC

3. Hibernate wake must be distinguishable from watchdog reset.  The
booter will log reset reason in Code RAM.  I copy the log data to
battery-backup RAM in little FW.  And system driver will refer this
data to distinguish if it's watchdog reset or not.

4. Watchdog reset flag is not set.  Same fix as 3.

5. Should return error if unable to clear SPI flash status register.

6. Remove chip_temp_sensor.c

7. Remove use of pstate from flash driver

8. Remove support for watchdog warm reset

9. Keyboard raw driver must support COL2 inverted

10. LPC memory mapped data must be read-only from host

11. LPC should support PLTRST# signal

12. Problems reading chip type/version.  Use core registers and ROM data to read IDs.

13. When chip type/version is unknown, report hex value.

14. Watchdog does not consistently print panic information.

15. Remove console force enable logic.

16. Enable only the peripheral clocks that are needed.  Please notice
user should add bit mask in CGC_XXX_MASK if they want to enable
additional module.  For example, if user wants to enable PWM3, he must
add PWDWN_CTL2_PWM3_PD bit in CGC_PWM_MASK.

Please see HOOK_FREQ_CHANGE and HOOK_INIT these two hook functions.
If I turn off all I2C modules in system_pre_init and turn on the
modules I need in i2c_init, I found its freq is not correct.  The root
cause is hook_notify(HOOK_FREQ_CHANGE) is executed first (in
clock_init) before i2c_init.  At this time, i2c modules are power-down
and writing to freq register is useless.  I re-execute freq-changed
hook function after turning on modules again.

17. MPU properly configured to prevent code execution from data RAM

18. Partial nvcontext implementation.  Copy these 16 bytes in our battery-backup RAM.

Additional items we also modified:

1. pwm.c: Support open-drain IO type of PWM.  (PWM IO-Type cannot by
determined by GPIO, we use bit 1 & 2 of function byte of gpio_alt_func
array to support it)

2. ec_npcxflash.c: Use definition to replace constant value.  Stop
watchdog during flash programing.

3. npcx_cmds.tcl: Adjust script sequence for robustness.  Add unlock
MPU commands for Data RAM.

BUG=chrome-os-partner:34346
BRANCH=none
TEST=manually verify changes

Change-Id: I722a77d29e7543b054819480c7b7477af4263119
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/248670

1 files changed, 3 insertions, 1 deletions

diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
index 88afba0266..611112aa63 100644
--- a/chip/npcx/config_chip.h
+++ b/chip/npcx/config_chip.h
@@ -54,8 +54,10 @@
 /* Default task stack size */
 #define TASK_STACK_SIZE         512
 
-/* SPI Flash Spec of W25Q20CV */
+/* Address of RAM log used by Booter */
+#define ADDR_BOOT_RAMLOG        0x100C7FC0
 
+/* SPI Flash Spec of W25Q20CV */
 #define CONFIG_FLASH_BANK_SIZE	0x00001000  /* protect bank size 4K bytes */
 #define CONFIG_FLASH_ERASE_SIZE	0x00001000  /* sector erase size 4K bytes */
 #define CONFIG_FLASH_WRITE_SIZE	0x00000001  /* minimum write size */