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| author | Furquan Shaikh <furquan@google.com> | 2018-08-29 16:16:57 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-05 16:11:09 -0700 |
| commit | 76e1d976246d90918e5f18d12d1df194b39cd90c (patch) | |
| tree | 72817b400cd2189493d68d12d7826d6369db67a7 /chip/npcx/config_chip.h | |
| parent | fc2140871e7d2d81b89a7e7043bd361f89189e99 (diff) | |
| download | chrome-ec-76e1d976246d90918e5f18d12d1df194b39cd90c.tar.gz | |
npcx: Decide erase size based on ro/rw region size
This change updates the erase operation in npcx chip to use 64k/32k/4k
block erase depending upon the alignment of CONFIG_RO_SIZE. This helps
reduce the EC SW sync time from ~9.5 seconds to ~5.4 seconds on NPCX7.
Ideally, we would want to check the offset and size of region to be
erased dynamically and decide which erase operation to use. However,
common flash code checks against CONFIG_FLASH_ERASE_SIZE to ensure
that the area being erased is aligned to that size. Thus, even if we
add dynamic erase at chip level, it isn't going to help.
This change also updates CONFIG_FLASH_BANK_SIZE to be the same as
CONFIG_FLASH_ERASE_SIZE since it is checked by common code. I am
honestly not sure why the CONFIG_FLASH_BANK_SIZE is tightly coupled
with CONFIG_FLASH_ERASE_SIZE. But, based on the usage, it seems to be
a safe change.
On the other hand, changing CONFIG_FLASH_BANK_SIZE helps reduce the
write time as well, thus overall helping with the EC SW Sync time.
Please see go/cros-npcx7-ec-sw-sync for more details.
BUG=b:113530328
BRANCH=nocturne
TEST=Verified that EC SW sync time goes down from 9.5 seconds to 5.4
seconds.
Change-Id: I5908eeeb3e4207a27abe804db8eb9d39ef9d73c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1195598
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip.h')
| -rw-r--r-- | chip/npcx/config_chip.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index e956e4cf6a..494f76c352 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -53,13 +53,6 @@ /* Address of RAM log used by Booter */ #define ADDR_BOOT_RAMLOG 0x100C7FC0 -/* SPI Flash Spec of W25Q20CV */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* protect bank size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* sector erase size 4K bytes */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000001 /* minimum write size */ - -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ - #include "config_flash_layout.h" /* Optional features present on this chip */ |