diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-05 17:27:37 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:32 -0700 |
| commit | 558c465165acf494905fa59c822c7190b4646899 (patch) | |
| tree | a20a512da9d8aed29cb46d99b8df0b8bb0ab5714 /chip/npcx/config_chip.h | |
| parent | d58e54730c03290296df5bb65cb84264e4b2facc (diff) | |
| download | chrome-ec-558c465165acf494905fa59c822c7190b4646899.tar.gz | |
cleanup: Remove CDRAM / CODERAM CONFIGs
CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.
These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip.h')
| -rw-r--r-- | chip/npcx/config_chip.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 56db32cc65..17e366ccfd 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -47,8 +47,6 @@ /* Memory mapping */ #define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ #define CONFIG_RAM_SIZE (0x00008000 - 0x800) /* 30KB data ram */ -#define CONFIG_CDRAM_BASE 0x100A8000 /* memory address of code ram */ -#define CONFIG_CDRAM_SIZE 0x00018000 /* 96KB code ram */ #define CONFIG_PROGRAM_MEMORY_BASE 0x64000000 /* program memory base address */ #define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ #define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ |