diff options
| author | Yilun Lin <yllin@google.com> | 2019-07-17 14:30:42 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-07-17 11:11:35 +0000 |
| commit | 1445108e8e2e34383a2df5efd30157526a905577 (patch) | |
| tree | 2e2130c94a8d09fbc0ba09be02948ed826ff3bd1 /chip/mt_scp | |
| parent | 3e8e4db7892acc2d64410ed24f1f0b333d66978b (diff) | |
| download | chrome-ec-1445108e8e2e34383a2df5efd30157526a905577.tar.gz | |
mt_scp: Drop TCM and L1 cache setting.
This config has been moved to kernel https://crrev.com/c/1687454 to
correctly initialize L1 cache. We should drop the config in SCP side.
Also, update the comment for CM4_MOD registers.
TEST=Boot SCP with kernel https://crrev.com/c/1627394/10
BUG=b:132658087
BRANCH=none
Change-Id: I37613533563acc00017f96a3d3009383057f072b
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703946
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Erin Lo <erin.lo@mediatek.com>
Commit-Queue: Yilun Lin <yllin@chromium.org>
Auto-Submit: Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'chip/mt_scp')
| -rw-r--r-- | chip/mt_scp/registers.h | 9 | ||||
| -rw-r--r-- | chip/mt_scp/system.c | 10 |
2 files changed, 11 insertions, 8 deletions
diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h index 608efcc17b..248a63e1ee 100644 --- a/chip/mt_scp/registers.h +++ b/chip/mt_scp/registers.h @@ -556,7 +556,14 @@ #ifndef __ASSEMBLER__ -/* Cortex-M4 mod */ +/* + * Cortex-M4 mod + * Available power saving features: + * 1. FPU freeze - freeze FPU operand when FPU is not used + * 2. LSU gating - gate LSU clock when not LSU operation + * 3. Trace clk disable - gate trace clock + * 4. DCM for CPU stall - gate CPU clock when CPU stall + */ #define CM4_MODIFICATION REG32(0xE00FE000) #define CM4_DCM_FEATURE REG32(0xE00FE004) /* UART, 16550 compatible */ diff --git a/chip/mt_scp/system.c b/chip/mt_scp/system.c index bd5e2ee36c..eaf37e5626 100644 --- a/chip/mt_scp/system.c +++ b/chip/mt_scp/system.c @@ -60,12 +60,8 @@ void chip_pre_init(void) { } -static void scp_enable_tcm(void) +static void scp_cm4_mod(void) { - /* Enable L1 cache and tightly coupled memory (TCM) */ - SCP_CLK_L1_SRAM_PD = 0; - SCP_CLK_TCM_TAIL_SRAM_PD = 0; - /* SCP CM4 mod */ CM4_MODIFICATION = 3; CM4_DCM_FEATURE = 3; } @@ -79,8 +75,8 @@ static void scp_enable_pirq(void) void system_pre_init(void) { - /* SRAM */ - scp_enable_tcm(); + /* CM4 Modification */ + scp_cm4_mod(); /* Clock */ scp_enable_clock(); /* Peripheral IRQ */ |