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| author | Randall Spangler <rspangler@chromium.org> | 2011-12-12 15:39:07 -0800 |
|---|---|---|
| committer | Randall Spangler <rspangler@chromium.org> | 2011-12-13 09:50:53 -0800 |
| commit | caba91fe2797f2e7a2792a151d337c20d080a950 (patch) | |
| tree | 59165d9809476115709733cf0c333c8789481c23 /chip/lm4/lpc.c | |
| parent | 1ce694189a847727e8eca53fbc324f67b92238e5 (diff) | |
| download | chrome-ec-caba91fe2797f2e7a2792a151d337c20d080a950.tar.gz | |
Change register.h macros to use inline funcs without concatenate (##).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: Ia8c54bfeff2351e8f76d97db558952a9d2ca9a45
Diffstat (limited to 'chip/lm4/lpc.c')
| -rw-r--r-- | chip/lm4/lpc.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c index 962b4f07ba..68f12c230d 100644 --- a/chip/lm4/lpc.c +++ b/chip/lm4/lpc.c @@ -29,18 +29,18 @@ static void configure_gpio(void) /* I/O: PL0:3 = command/address/data * inp: PL4 (frame), PL5 (reset), PM0 (powerdown), PM5 (clock) * out: PM1 (sci), PM2 (clkrun), PM4 (serirq) */ - LM4_GPIO_AFSEL(L) |= 0x3f; - LM4_GPIO_AFSEL(M) |= 0x37; - LM4_GPIO_PCTL(L) |= 0x00ffffff; - LM4_GPIO_PCTL(M) |= 0x00ff0fff; - LM4_GPIO_DEN(L) |= 0x3f; - LM4_GPIO_DEN(M) |= 0x37; + LM4_GPIO_AFSEL(LM4_GPIO_L) |= 0x3f; + LM4_GPIO_AFSEL(LM4_GPIO_M) |= 0x37; + LM4_GPIO_PCTL(LM4_GPIO_L) |= 0x00ffffff; + LM4_GPIO_PCTL(LM4_GPIO_M) |= 0x00ff0fff; + LM4_GPIO_DEN(LM4_GPIO_L) |= 0x3f; + LM4_GPIO_DEN(LM4_GPIO_M) |= 0x37; /* Set the drive strength to 8mA for serirq only */ /* TODO: Only necessary on BDS because the cabling to the x86 * is long and flaky; remove this for Link. Setting this for all * I/O lines seems to hang the x86 during boot. */ - LM4_GPIO_DR8R(M) |= 0x00000010; + LM4_GPIO_DR8R(LM4_GPIO_M) |= 0x00000010; } |