it8380dev: add flash module and fix system jump

1. Add flash control module for emulation board.
2. Fix system jump for Andes core.
3. Change the physical size of the flash on the chip to 256KB.

note:
1. Only IT839x series supports flash write protect by registers.
2. Static DMA method of flash code only for IT839x series and IT838x Dx.

Signed-off-by: Dino Li <dino.li@ite.com.tw>

BRANCH=none
BUG=none
TEST=1. console command flashwp and flashinfo
       1-a. flashwp enable
       1-b. WP asserted and reboot
       1-c. flashinfo RO protected now
       1-d. WP deasserted and reboot
       1-e. No protected
       1-f. flashwp disable
       1-g. WP asserted and reboot
       1-h. No protected
     2. console sysjump and sysinfo
       2-a. sysjump rw
       2-b. jumping to image RW
       2-c. sysinfo, Copy : RW, Jumped : yes
       2-d. sysjump ro
       2-e. jumping to image RO
       2-f. sysinfo, Copy : RO, Jumped : yes
     3. RO/RW firmware image test
       3-a. sysjump rw
       3-b. use console command "eflash" to erase RO region,
            erase OK and system still work.
       3-c. reflash firmware
       3-d. sysjump rw, sysjump ro
       3-e. use console command "eflash" to erase RW region,
            erase OK and system still work.

Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8
Reviewed-on: https://chromium-review.googlesource.com/271390
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>

1 files changed, 21 insertions, 5 deletions

diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index c918d3eb5b..3cfeede2cf 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -639,11 +639,18 @@ enum clock_gate_offsets {
 /* --- General Control (GCTRL) --- */
 #define IT83XX_GCTRL_BASE 0x00F02000
 
-#define IT83XX_GCTRL_WNCKR     REG8(IT83XX_GCTRL_BASE+0x0B)
-#define IT83XX_GCTRL_RSTS      REG8(IT83XX_GCTRL_BASE+0x06)
-#define IT83XX_GCTRL_BADRSEL   REG8(IT83XX_GCTRL_BASE+0x0A)
-#define IT83XX_GCTRL_RSTC4     REG8(IT83XX_GCTRL_BASE+0x11)
-#define IT83XX_GCTRL_MCCR2     REG8(IT83XX_GCTRL_BASE+0x44)
+#define IT83XX_GCTRL_WNCKR        REG8(IT83XX_GCTRL_BASE+0x0B)
+#define IT83XX_GCTRL_RSTS         REG8(IT83XX_GCTRL_BASE+0x06)
+#define IT83XX_GCTRL_BADRSEL      REG8(IT83XX_GCTRL_BASE+0x0A)
+#define IT83XX_GCTRL_RSTC4        REG8(IT83XX_GCTRL_BASE+0x11)
+#define IT83XX_GCTRL_SPCTRL4      REG8(IT83XX_GCTRL_BASE+0x1C)
+#define IT83XX_GCTRL_MCCR         REG8(IT83XX_GCTRL_BASE+0x30)
+#define IT83XX_GCTRL_EPLR         REG8(IT83XX_GCTRL_BASE+0x37)
+#define IT83XX_GCTRL_IVTBAR       REG8(IT83XX_GCTRL_BASE+0x41)
+#define IT83XX_GCTRL_MCCR2        REG8(IT83XX_GCTRL_BASE+0x44)
+#define IT83XX_GCTRL_EWPR0PFH(i)  REG8(IT83XX_GCTRL_BASE+0x60+i)
+#define IT83XX_GCTRL_EWPR0PFD(i)  REG8(IT83XX_GCTRL_BASE+0xA0+i)
+#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i)
 
 /* --- Pulse Width Modulation (PWM) --- */
 #define IT83XX_PWM_BASE   0x00F01800
@@ -868,6 +875,15 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4))
 #define IT83XX_SMFI_H2RAMECSIE  REG8(IT83XX_SMFI_BASE+0x7A)
 #define IT83XX_SMFI_H2RAMECSA   REG8(IT83XX_SMFI_BASE+0x7B)
 #define IT83XX_SMFI_H2RAMHSS    REG8(IT83XX_SMFI_BASE+0x7C)
+#define IT83XX_SMFI_ECINDAR0    REG8(IT83XX_SMFI_BASE+0x3B)
+#define IT83XX_SMFI_ECINDAR1    REG8(IT83XX_SMFI_BASE+0x3C)
+#define IT83XX_SMFI_ECINDAR2    REG8(IT83XX_SMFI_BASE+0x3D)
+#define IT83XX_SMFI_ECINDAR3    REG8(IT83XX_SMFI_BASE+0x3E)
+#define IT83XX_SMFI_ECINDDR     REG8(IT83XX_SMFI_BASE+0x3F)
+#define IT83XX_SMFI_SCAR2L      REG8(IT83XX_SMFI_BASE+0x46)
+#define IT83XX_SMFI_SCAR2M      REG8(IT83XX_SMFI_BASE+0x47)
+#define IT83XX_SMFI_SCAR2H      REG8(IT83XX_SMFI_BASE+0x48)
+#define IT83XX_SMFI_STCDMACR    REG8(IT83XX_SMFI_BASE+0x80)
 
 /* Serial Peripheral Interface (SSPI) */
 #define IT83XX_SSPI_BASE  0x00F02600