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| author | Dino Li <Dino.Li@ite.com.tw> | 2019-06-10 16:26:36 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-06-11 17:26:38 +0000 |
| commit | 59d060ebfe68082f4ea87214ffcda976c55176af (patch) | |
| tree | e237e25e9979220a716b72b65d43fb559504bc60 /chip/it83xx/registers.h | |
| parent | 3a668749460466ff002b5dd2cbf00529f97e5974 (diff) | |
| download | chrome-ec-59d060ebfe68082f4ea87214ffcda976c55176af.tar.gz | |
core:RISC-V / chip:IT83202
The IT83202 is an embedded controller with RISC-V core.
It supports maximum ram size to 256KB and internal flash to 1MB.
BUG=none
BRANCH=none
TEST=EC boots and test console commands (eg: taskinfo, version, sysjump...)
on it83202 EVB.
Change-Id: I424c0d2878beb941c816363b5c7a3f57fda9fd13
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1588300
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 13f6609662..184b7985fb 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -414,7 +414,7 @@ #define CPU_INT(irq) CONCAT2(IT83XX_CPU_INT_IRQ_, irq) /* --- INTC --- */ -#define IT83XX_INTC_BASE 0x00F01100 +#define IT83XX_INTC_BASE CHIP_EC_INTC_BASE #define IT83XX_INTC_REG(n) REG8(IT83XX_INTC_BASE+(n)) @@ -766,8 +766,14 @@ enum clock_gate_offsets { /* --- General Control (GCTRL) --- */ #define IT83XX_GCTRL_BASE 0x00F02000 +#ifdef IT83XX_CHIP_ID_3BYTES +#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE+0x85) +#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE+0x86) +#define IT83XX_GCTRL_CHIPID3 REG8(IT83XX_GCTRL_BASE+0x87) +#else #define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE+0x00) #define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE+0x01) +#endif #define IT83XX_GCTRL_CHIPVER REG8(IT83XX_GCTRL_BASE+0x02) #define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE+0x0B) #define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE+0x06) @@ -784,6 +790,8 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) #define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) #define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) +#define IT83XX_GCTRL_MCCR3 REG8(IT83XX_GCTRL_BASE+0x5D) +#define ILMCR_ILM2_ENABLE BIT(2) #define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE+0x60+i) #define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE+0xA0+i) #define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i) @@ -1030,6 +1038,7 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) #define IT83XX_SMFI_ECINDAR1 REG8(IT83XX_SMFI_BASE+0x3C) #define IT83XX_SMFI_ECINDAR2 REG8(IT83XX_SMFI_BASE+0x3D) #define IT83XX_SMFI_ECINDAR3 REG8(IT83XX_SMFI_BASE+0x3E) +#define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) #define IT83XX_SMFI_ECINDDR REG8(IT83XX_SMFI_BASE+0x3F) #define IT83XX_SMFI_SCAR2L REG8(IT83XX_SMFI_BASE+0x46) #define IT83XX_SMFI_SCAR2M REG8(IT83XX_SMFI_BASE+0x47) |