diff options
| author | tim <tim2.lin@ite.corp-partner.google.com> | 2019-12-10 14:56:37 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-12-11 06:56:31 +0000 |
| commit | 82b48440086e010880db8bd102e7ade1f8d515ad (patch) | |
| tree | 9a09e65e4549682ab0fd1be44ec8255ac0e802dc /chip/it83xx/registers.h | |
| parent | cd3aace7aa0a3a01220e716c36a17af312d63ae4 (diff) | |
| download | chrome-ec-82b48440086e010880db8bd102e7ade1f8d515ad.tar.gz | |
it83xx/spi: add spi slave function
Add the spi slave function which is required to
communicate with the EC when the CPU is the ARM
processor.
BUG=none
BRANCH=none
TEST=Replaced board elm's EC with it83202 and
boot kernel and keyboard work.
Change-Id: I7ce3bb56450276997b58e84b1c6de3f8e45bb4b7
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918991
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 65460009b7..aeab504147 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -961,6 +961,8 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_RSTDMMC REG8(IT83XX_GCTRL_BASE+0x10) #define IT83XX_GCTRL_RSTC4 REG8(IT83XX_GCTRL_BASE+0x11) #define IT83XX_GCTRL_SPCTRL4 REG8(IT83XX_GCTRL_BASE+0x1C) +#define IT83XX_GCTRL_MCCR3 REG8(IT83XX_GCTRL_BASE+0x20) +#define IT83XX_GCTRL_SPISLVPFE BIT(6) #define IT83XX_GCTRL_MCCR REG8(IT83XX_GCTRL_BASE+0x30) #define IT83XX_GCTRL_PMER1 REG8(IT83XX_GCTRL_BASE+0x32) #define IT83XX_GCTRL_PMER2 REG8(IT83XX_GCTRL_BASE+0x33) @@ -1239,6 +1241,40 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) #define IT83XX_SSPI_SPISTS REG8(IT83XX_SSPI_BASE+0x03) #define IT83XX_SSPI_SPICTRL3 REG8(IT83XX_SSPI_BASE+0x04) +/* Serial Peripheral Interface (SPI) */ +#define IT83XX_SPI_BASE 0x00F03A00 + +#define IT83XX_SPI_SPISGCR REG8(IT83XX_SPI_BASE+0x00) +#define IT83XX_SPI_SPISCEN BIT(0) +#define IT83XX_SPI_TXRXFAR REG8(IT83XX_SPI_BASE+0x01) +#define IT83XX_SPI_CPURXF2A BIT(4) +#define IT83XX_SPI_CPURXF1A BIT(3) +#define IT83XX_SPI_CPUTFA BIT(1) +#define IT83XX_SPI_TXFCR REG8(IT83XX_SPI_BASE+0x02) +#define IT83XX_SPI_TXFCMR BIT(2) +#define IT83XX_SPI_TXFR BIT(1) +#define IT83XX_SPI_TXFS BIT(0) +#define IT83XX_SPI_IMR REG8(IT83XX_SPI_BASE+0x04) +#define IT83XX_SPI_RFFIM BIT(7) +#define IT83XX_SPI_EDIM BIT(2) +#define IT83XX_SPI_ISR REG8(IT83XX_SPI_BASE+0x05) +#define IT83XX_SPI_RXFIFOFULL BIT(7) +#define IT83XX_SPI_ENDDETECTINT BIT(2) +#define IT83XX_SPI_RXFSR REG8(IT83XX_SPI_BASE+0x07) +#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) +#define IT83XX_SPI_RXF2FS BIT(2) +#define IT83XX_SPI_RXF1FS BIT(1) +#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE+0x08) +#define IT83XX_SPI_CPUWTFDB0 REG32(IT83XX_SPI_BASE+0x08) +#define IT83XX_SPI_FCR REG8(IT83XX_SPI_BASE+0x09) +#define IT83XX_SPI_SPISRTXF BIT(2) +#define IT83XX_SPI_RXFR BIT(1) +#define IT83XX_SPI_RXFCMR BIT(0) +#define IT83XX_SPI_RXFRDRB0 REG32(IT83XX_SPI_BASE+0x0C) +#define IT83XX_SPI_FTCB0R REG8(IT83XX_SPI_BASE+0x18) +#define IT83XX_SPI_FTCB1R REG8(IT83XX_SPI_BASE+0x19) +#define IT83XX_SPI_HPR2 REG8(IT83XX_SPI_BASE+0x1E) + /* Platform Environment Control Interface (PECI) */ #define IT83XX_PECI_BASE 0x00F02C00 |