ish: cleanup of UART-related functionality

This commit cleans up UART-related ISH code:

* Moving REG{8,16,32} macro usages into header files
* Changing ifdef logic in code to use IS_ENABLED macro
* Reduce repeated code in uart_defs.h
* Change hexadecimal masks in uart_defs.h to use BIT(n) macros
* Change disabling of UART2 to use common logic in uart_stop_hw

BUG=b:130573158
BRANCH=none
TEST=UART on arcada_ish is functioning as normal

Change-Id: Ia05feea2de8c14e44e4d3f9dd7c790bcb81cd1c0
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1582457
Reviewed-by: Jett Rink <jettrink@chromium.org>

2 files changed, 164 insertions, 196 deletions

diff --git a/chip/ish/uart.c b/chip/ish/uart.c
index 5076f5eeaf..e512b53588 100644
--- a/chip/ish/uart.c
+++ b/chip/ish/uart.c
@@ -46,6 +46,13 @@ static struct uart_ctx uart_ctx[UART_DEVICES] = {
 		.input_freq = UART_ISH_INPUT_FREQ,
 		.addr_interval = UART_ISH_ADDR_INTERVAL,
 		.uart_state = UART_STATE_CG,
+	},
+	{
+		.id = 2,
+		.base = UART2_BASE,
+		.input_freq = UART_ISH_INPUT_FREQ,
+		.addr_interval = UART_ISH_ADDR_INTERVAL,
+		.uart_state = UART_STATE_CG,
 	}
 };
 
@@ -58,47 +65,35 @@ int uart_init_done(void)
 
 void uart_tx_start(void)
 {
-#if !defined(CONFIG_POLLING_UART)
-
-	enum UART_PORT id = ISH_DEBUG_UART; /* UART for ISH */
-
-	if (REG8(IER(id)) & IER_TDRQ)
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/* TODO: disable low power mode while transmit */
+	if (!IS_ENABLED(CONFIG_POLLING_UART)) {
+		if (IER(ISH_DEBUG_UART) & IER_TDRQ)
+			return;
 
-	REG8(IER(id)) |= IER_TDRQ;
+		/* Do not allow deep sleep while transmit in progress */
+		disable_sleep(SLEEP_MASK_UART);
 
-	task_trigger_irq(ISH_DEBUG_UART_IRQ);
+		IER(ISH_DEBUG_UART) |= IER_TDRQ;
 
-#endif
+		task_trigger_irq(ISH_DEBUG_UART_IRQ);
+	}
 }
 
 void uart_tx_stop(void)
 {
-#if !defined(CONFIG_POLLING_UART)
-	enum UART_PORT id = ISH_DEBUG_UART; /* UART for ISH */
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-
-	REG8(IER(id)) &= ~IER_TDRQ;
+	if (!IS_ENABLED(CONFIG_POLLING_UART)) {
+		/* Re-allow deep sleep */
+		enable_sleep(SLEEP_MASK_UART);
 
-	/* TODO: re-enable low power mode */
-#endif
+		IER(ISH_DEBUG_UART) &= ~IER_TDRQ;
+	}
 }
 
 void uart_tx_flush(void)
 {
-#if !defined(CONFIG_POLLING_UART)
-	enum UART_PORT id = ISH_DEBUG_UART; /* UART for ISH */
-
-	while (!(REG8(LSR(id)) & LSR_TEMT) )
-		;
-#endif
+	if (!IS_ENABLED(CONFIG_POLLING_UART)) {
+		while (!(LSR(ISH_DEBUG_UART) & LSR_TEMT))
+			continue;
+	}
 }
 
 int uart_tx_ready(void)
@@ -108,32 +103,24 @@ int uart_tx_ready(void)
 
 int uart_rx_available(void)
 {
-#if !defined(CONFIG_POLLING_UART)
-	enum UART_PORT id = ISH_DEBUG_UART; /* UART for ISH */
+	if (IS_ENABLED(CONFIG_POLLING_UART))
+		return 0;
 
-	return REG8(LSR(id)) & LSR_DR;
-#else
-	return 0;
-#endif
+	return LSR(ISH_DEBUG_UART) & LSR_DR;
 }
 
 void uart_write_char(char c)
 {
-	enum UART_PORT id = ISH_DEBUG_UART; /* UART for ISH */
-
 	/* Wait till reciever is ready */
-	while ((REG8(LSR(id)) & LSR_TEMT) == 0)
-		;
+	while ((LSR(ISH_DEBUG_UART) & LSR_TEMT) == 0)
+		continue;
 
-	REG8(THR(id)) = c;
+	THR(ISH_DEBUG_UART) = c;
 }
 
-#if !defined(CONFIG_POLLING_UART)
 int uart_read_char(void)
 {
-	enum UART_PORT id = ISH_DEBUG_UART; /* UART for ISH */
-
-	return REG8(RBR(id));
+	return RBR(ISH_DEBUG_UART);
 }
 
 void uart_ec_interrupt(void)
@@ -142,8 +129,9 @@ void uart_ec_interrupt(void)
 	uart_process_input();
 	uart_process_output();
 }
+#ifndef CONFIG_POLLING_UART
 DECLARE_IRQ(ISH_DEBUG_UART_IRQ, uart_ec_interrupt);
-#endif /* !defined(CONFIG_POLLING_UART) */
+#endif
 
 static int uart_return_baud_rate_by_id(int baud_rate_id)
 {
@@ -167,42 +155,43 @@ static void uart_hw_init(enum UART_PORT id)
 	/* Calculate baud rate divisor */
 	divisor = (ctx->input_freq / ctx->baud_rate) >> 4;
 
-	REG32(MUL(ctx->id)) = (divisor * ctx->baud_rate);
-	REG32(DIV(ctx->id)) = (ctx->input_freq / 16);
-	REG32(PS(ctx->id)) = 16;
+	MUL(ctx->id) = (divisor * ctx->baud_rate);
+	DIV(ctx->id) = (ctx->input_freq / 16);
+	PS(ctx->id) = 16;
 
 	/* Set the DLAB to access the baud rate divisor registers */
-	REG8(LCR(ctx->id)) = LCR_DLAB;
-	REG8(DLL(ctx->id)) = (divisor & 0xff);
-	REG8(DLH(ctx->id)) = ((divisor >> 8) & 0xff);
+	LCR(ctx->id) = LCR_DLAB;
+	DLL(ctx->id) = (divisor & 0xff);
+	DLH(ctx->id) = ((divisor >> 8) & 0xff);
 
 	/* 8 data bits, 1 stop bit, no parity, clear DLAB */
-	REG8(LCR(ctx->id)) = LCR_8BIT_CHR;
+	LCR(ctx->id) = LCR_8BIT_CHR;
 
 	if (ctx->client_flags & UART_CONFIG_HW_FLOW_CONTROL)
 		mcr = MCR_AUTO_FLOW_EN;
 
-	mcr |= MCR_INTR_ENABLE;	/* needs to be set regardless of flow control */
+	/* needs to be set regardless of flow control */
+	mcr |= MCR_INTR_ENABLE;
 
 	mcr |= (MCR_RTS | MCR_DTR);
-	REG8(MCR(ctx->id)) = mcr;
+	MCR(ctx->id) = mcr;
 
 	fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1;
 
 	/* configure FIFOs */
-	REG8(FCR(ctx->id)) = (fcr | FCR_FIFO_ENABLE
-			      | FCR_RESET_RX | FCR_RESET_TX);
+	FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE
+			| FCR_RESET_RX | FCR_RESET_TX);
 
 	/* enable UART unit */
-	REG32(ABR(ctx->id)) = ABR_UUE;
+	ABR(ctx->id) = ABR_UUE;
 
 	/* clear the port */
-	REG8(RBR(ctx->id));
-#ifdef CONFIG_POLLING_UART
-	REG8(IER(ctx->id)) = 0x00;
-#else
-	REG8(IER(ctx->id)) = IER_RECV;
-#endif
+	RBR(ctx->id);
+
+	if (IS_ENABLED(CONFIG_POLLING_UART))
+		IER(ctx->id) = 0x00;
+	else
+		IER(ctx->id) = IER_RECV;
 }
 
 static void uart_stop_hw(enum UART_PORT id)
@@ -213,25 +202,24 @@ static void uart_stop_hw(enum UART_PORT id)
 	/* Manually clearing the fifo from possible noise.
 	 * Entering D0i3 when fifo is not cleared may result in a hang.
 	 */
-	fifo_len = (REG32(FOR(id)) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS;
+	fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS;
 
 	for (i = 0; i < fifo_len; i++)
-		(void)REG8(RBR(id));
+		(void)RBR(id);
 
 	/* No interrupts are enabled */
-	REG8(IER(id)) = 0;
-	REG8(MCR(id)) = 0;
+	IER(id) = 0;
+	MCR(id) = 0;
 
 	/* Clear and disable FIFOs */
-	REG8(FCR(id)) = (FCR_RESET_RX | FCR_RESET_TX);
+	FCR(id) = (FCR_RESET_RX | FCR_RESET_TX);
 
 	/* Disable uart unit */
-	REG32(ABR(id)) = 0;
+	ABR(id) = 0;
 }
 
 static int uart_client_init(enum UART_PORT id, uint32_t baud_rate_id, int flags)
 {
-
 	if ((uart_ctx[id].base == 0) || (id >= UART_DEVICES))
 		return UART_ERROR;
 
@@ -254,7 +242,6 @@ static int uart_client_init(enum UART_PORT id, uint32_t baud_rate_id, int flags)
 static void uart_drv_init(void)
 {
 	int i;
-	uint32_t fifo_len;
 
 	/* Disable UART */
 	for (i = 0; i < UART_DEVICES; i++)
@@ -263,34 +250,15 @@ static void uart_drv_init(void)
 	/* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit
 	 * to allow PMU to clock gate ISH
 	 */
-	REG32(HSU_BASE + HSU_REG_GIEN) = (GIEN_DMA_EN | GIEN_UART0_EN
-					  | GIEN_UART1_EN | GIEN_PWR_MGMT);
-
-	/* There is a by design HW "bug" where all UARTs are enabled by default
-	 * but they must be disbled to enter clock gating.
-	 * UART0 and UART1 are disabled during their init - but we don't init
-	 * UART2 so as a w/a we disable UART2 even though it isn't being used.
-	 * we also clear UART 2 fifo, which may cause problem entrying TCG is
-	 * not empty (we do the same for UART0 and 1 in "uart_stop_hw"
-	 */
-
-	fifo_len = (REG32(UART2_BASE + UART_REG_FOR)
-		    & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS;
-
-	for (i = 0; i < fifo_len; i++)
-		(void)REG8((UART2_BASE + UART_REG_RBR));
-
-	REG32(UART2_BASE + UART_REG_ABR) = 0;
+	HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN
+			| GIEN_UART1_EN | GIEN_PWR_MGMT);
 
 	task_enable_irq(ISH_DEBUG_UART_IRQ);
 }
 
 void uart_init(void)
 {
-
 	uart_drv_init();
-
 	uart_client_init(ISH_DEBUG_UART, B115200, 0);
-
 	init_done = 1;
 }
diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h
index 6a04557c58..ed37c47d13 100644
--- a/chip/ish/uart_defs.h
+++ b/chip/ish/uart_defs.h
@@ -11,169 +11,169 @@
 #include <stdint.h>
 #include <stddef.h>
 
-#define	UART_ERROR		-1
+#define UART_ERROR		-1
 #define UART_BUSY		-2
 #define HSU_BASE		ISH_UART_BASE
-#define UART0_OFFS              (0x80)
-#define UART0_BASE              (ISH_UART_BASE + UART0_OFFS)
-#define UART0_SIZE              (0x80)
+#define UART0_OFFS		(0x80)
+#define UART0_BASE		(ISH_UART_BASE + UART0_OFFS)
+#define UART0_SIZE		(0x80)
 
-#define UART1_OFFS              (0x100)
-#define UART1_BASE              (ISH_UART_BASE + UART1_OFFS)
-#define UART1_SIZE              (0x80)
+#define UART1_OFFS		(0x100)
+#define UART1_BASE		(ISH_UART_BASE + UART1_OFFS)
+#define UART1_SIZE		(0x80)
 
-#define UART2_OFFS              (0x180)
-#define UART2_BASE              (ISH_UART_BASE + UART2_OFFS)
-#define UART2_SIZE              (0x80)
+#define UART2_OFFS		(0x180)
+#define UART2_BASE		(ISH_UART_BASE + UART2_OFFS)
+#define UART2_SIZE		(0x80)
+
+#define UART_REG(size, name, n)					\
+	REG##size(uart_ctx[n].base +					\
+		  UART_OFFSET_##name * uart_ctx[n].addr_interval)
 
 /* Register accesses */
-#define LSR(n)  (uart_ctx[n].base + UART_REG_LSR * uart_ctx[n].addr_interval)
-#define THR(n)  (uart_ctx[n].base + UART_REG_THR * uart_ctx[n].addr_interval)
-#define FOR(n)  (uart_ctx[n].base + UART_REG_FOR * uart_ctx[n].addr_interval)
-#define RBR(n)  (uart_ctx[n].base + UART_REG_RBR * uart_ctx[n].addr_interval)
-#define DLL(n)  (uart_ctx[n].base + UART_REG_DLL * uart_ctx[n].addr_interval)
-#define DLH(n)  (uart_ctx[n].base + UART_REG_DLH * uart_ctx[n].addr_interval)
-#define DLD(n)  (uart_ctx[n].base + UART_REG_DLD * uart_ctx[n].addr_interval)
-#define IER(n)  (uart_ctx[n].base + UART_REG_IER * uart_ctx[n].addr_interval)
-#define IIR(n)  (uart_ctx[n].base + UART_REG_IIR * uart_ctx[n].addr_interval)
-#define FCR(n)  (uart_ctx[n].base + UART_REG_FCR * uart_ctx[n].addr_interval)
-#define LCR(n)  (uart_ctx[n].base + UART_REG_LCR * uart_ctx[n].addr_interval)
-#define MCR(n)  (uart_ctx[n].base + UART_REG_MCR * uart_ctx[n].addr_interval)
-#define MSR(n)  (uart_ctx[n].base + UART_REG_MSR * uart_ctx[n].addr_interval)
-#define FCTR(n)  (uart_ctx[n].base + UART_REG_FCTR * uart_ctx[n].addr_interval)
-#define EFR(n)  (uart_ctx[n].base + UART_REG_EFR * uart_ctx[n].addr_interval)
-#define RXTRG(n) \
-		(uart_ctx[n].base + UART_REG_RXTRG * uart_ctx[n].addr_interval)
-#define ABR(n)  (uart_ctx[n].base + UART_REG_ABR * uart_ctx[n].addr_interval)
-#define PS(n)  (uart_ctx[n].base + UART_REG_PS * uart_ctx[n].addr_interval)
-#define MUL(n)  (uart_ctx[n].base + UART_REG_MUL * uart_ctx[n].addr_interval)
-#define DIV(n)  (uart_ctx[n].base + UART_REG_DIV * uart_ctx[n].addr_interval)
+#define LSR(n)			UART_REG(8, LSR, n)
+#define THR(n)			UART_REG(8, THR, n)
+#define FOR(n)			UART_REG(32, FOR, n)
+#define RBR(n)			UART_REG(8, RBR, n)
+#define DLL(n)			UART_REG(8, DLL, n)
+#define DLH(n)			UART_REG(8, DLH, n)
+#define DLD(n)			UART_REG(8, DLD, n)
+#define IER(n)			UART_REG(8, IER, n)
+#define IIR(n)			UART_REG(8, IIR, n)
+#define FCR(n)			UART_REG(8, FCR, n)
+#define LCR(n)			UART_REG(8, LCR, n)
+#define MCR(n)			UART_REG(8, MCR, n)
+#define MSR(n)			UART_REG(8, MSR, n)
+#define ABR(n)			UART_REG(32, ABR, n)
+#define PS(n)			UART_REG(32, PS, n)
+#define MUL(n)			UART_REG(32, MUL, n)
+#define DIV(n)			UART_REG(32, DIV, n)
 
 /* RBR: Receive Buffer register     (BLAB bit = 0)  */
-#define UART_REG_RBR		(0)
+#define UART_OFFSET_RBR	(0)
 /* THR: Transmit Holding register   (BLAB bit = 0)  */
-#define UART_REG_THR		(0)
+#define UART_OFFSET_THR	(0)
 /* IER: Interrupt Enable register   (BLAB bit = 0)  */
-#define UART_REG_IER		(1)
+#define UART_OFFSET_IER	(1)
 
 #define FCR_FIFO_SIZE_16	(0x00)
 #define FCR_FIFO_SIZE_64	(0x20)
-#define FCR_ITL_FIFO_64_BYTES_1	(0x00)
+#define FCR_ITL_FIFO_64_BYTES_1 (0x00)
 
 /* FCR: FIFO Control register */
-#define UART_REG_FCR		(2)
-#define FCR_FIFO_ENABLE		(0x01)
-#define FCR_RESET_RX		(0x02)
-#define FCR_RESET_TX		(0x04)
+#define UART_OFFSET_FCR	(2)
+#define FCR_FIFO_ENABLE	BIT(0)
+#define FCR_RESET_RX		BIT(1)
+#define FCR_RESET_TX		BIT(2)
 
 /* LCR: Line Control register */
-#define UART_REG_LCR		(3)
-#define LCR_DLAB                (0x80)
-#define LCR_5BIT_CHR            (0x00)
-#define LCR_6BIT_CHR            (0x01)
-#define LCR_7BIT_CHR            (0x02)
-#define LCR_8BIT_CHR            (0x03)
-#define LCR_BIT_CHR_MASK        (0x03)
-#define LCR_SB                  (0x40)	/*Set Break */
+#define UART_OFFSET_LCR	(3)
+#define LCR_DLAB		(0x80)
+#define LCR_5BIT_CHR		(0x00)
+#define LCR_6BIT_CHR		(0x01)
+#define LCR_7BIT_CHR		(0x02)
+#define LCR_8BIT_CHR		(0x03)
+#define LCR_BIT_CHR_MASK	(0x03)
+#define LCR_SB			(0x40)	/* Set Break */
 
 /* MCR: Modem Control register */
-#define UART_REG_MCR		(4)
-#define MCR_DTR			(0x1)
-#define MCR_RTS			(0x2)
-#define MCR_LOO			(0x10)
-#define MCR_INTR_ENABLE		(0x08)
-#define MCR_AUTO_FLOW_EN	(0x20)
+#define UART_OFFSET_MCR	(4)
+#define MCR_DTR		BIT(0)
+#define MCR_RTS		BIT(1)
+#define MCR_LOO		BIT(4)
+#define MCR_INTR_ENABLE	BIT(3)
+#define MCR_AUTO_FLOW_EN	BIT(5)
 
 /* LSR: Line Status register */
-#define UART_REG_LSR		(5)
-#define LSR_DR			(0x01)	/* Data Ready */
-#define LSR_OE			(0x02)	/* Overrun error */
-#define LSR_PE			(0x04)	/* Parity error */
-#define LSR_FE			(0x08)	/* Framing error */
-#define LSR_BI			(0x10)	/* Breaking interrupt */
-#define LSR_THR_EMPTY		(0x20)	/* Non FIFO mode: Transmit holding
+#define UART_OFFSET_LSR	(5)
+#define LSR_DR			BIT(0)	/* Data Ready */
+#define LSR_OE			BIT(1)	/* Overrun error */
+#define LSR_PE			BIT(2)	/* Parity error */
+#define LSR_FE			BIT(3)	/* Framing error */
+#define LSR_BI			BIT(4)	/* Breaking interrupt */
+#define LSR_THR_EMPTY		BIT(5)	/* Non FIFO mode: Transmit holding
 					 * register empty
 					 */
-#define LSR_TDRQ		(0x20)	/* FIFO mode: Transmit Data request */
-#define LSR_TEMT		(0x40)	/* Transmitter empty */
+#define LSR_TDRQ		BIT(5)	/* FIFO mode: Transmit Data request */
+#define LSR_TEMT		BIT(6)	/* Transmitter empty */
 
-#define FCR_ITL_FIFO_64_BYTES_56    (0xc0)
+#define FCR_ITL_FIFO_64_BYTES_56 (BIT(6) | BIT(7))
 
-#define IER_RECV		(0x01)
-#define IER_TDRQ		(0x02)
-#define IER_LINE_STAT		(0x04)
+#define IER_RECV		BIT(0)
+#define IER_TDRQ		BIT(1)
+#define IER_LINE_STAT		BIT(2)
 
-#define UART_REG_IIR		(2)
+#define UART_OFFSET_IIR	(2)
 /* MSR: Modem Status register */
-#define UART_REG_MSR		(6)
+#define UART_OFFSET_MSR	(6)
 
 /* DLL: Divisor Latch Reg. low byte  (BLAB bit = 1) */
-#define UART_REG_DLL		(0)
+#define UART_OFFSET_DLL	(0)
 
 /* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */
-#define UART_REG_DLH		(1)
+#define UART_OFFSET_DLH	(1)
 
 /* DLH: Divisor Latch Fractional. (BLAB bit = 1) */
-#define UART_REG_DLD		(2)
+#define UART_OFFSET_DLD	(2)
 
 /* FOR: Fifo O Register (ISH only) */
-#define UART_REG_FOR		(0x20)
-#define FOR_OCCUPANCY_OFFS      0
-#define FOR_OCCUPANCY_MASK      0x7F
+#define UART_OFFSET_FOR	(0x20)
+#define FOR_OCCUPANCY_OFFS	0
+#define FOR_OCCUPANCY_MASK	0x7F
 
 /* ABR: Auto-Baud Control Register (ISH only) */
-#define UART_REG_ABR		(0x24)
-#define ABR_UUE			(0x10)
+#define UART_OFFSET_ABR	(0x24)
+#define ABR_UUE		BIT(4)
 
 /* Pre-Scalar Register (ISH only) */
-#define UART_REG_PS		(0x30)
+#define UART_OFFSET_PS		(0x30)
 
 /* DDS registers (ISH only) */
-#define UART_REG_MUL		(0x34)
-#define UART_REG_DIV		(0x38)
+#define UART_OFFSET_MUL	(0x34)
+#define UART_OFFSET_DIV	(0x38)
 
 /* G_IEN: Global Interrupt Enable  (ISH only) */
-#define HSU_REG_GIEN		(0)
-#define HSU_REG_GIST		(4)
-
-#define GIEN_PWR_MGMT           (0x01000000)
-#define GIEN_DMA_EN             (0x00000020)
-#define GIEN_UART2_EN           (0x00000004)
-#define GIEN_UART1_EN           (0x00000002)
-#define GIEN_UART0_EN           (0x00000001)
-#define GIST_DMA_EN             (0x00000020)
-#define GIST_UART2_EN           (0x00000004)
-#define GIST_UART1_EN           (0x00000002)
-#define GIST_UART0_EN           (0x00000001)
-#define GIST_UARTx_EN           (GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN)
+#define HSU_REG_GIEN		REG32(HSU_BASE + 0x0)
+#define HSU_REG_GIST		REG32(HSU_BASE + 0x4)
+
+#define GIEN_PWR_MGMT		BIT(24)
+#define GIEN_DMA_EN		BIT(5)
+#define GIEN_UART2_EN		BIT(2)
+#define GIEN_UART1_EN		BIT(1)
+#define GIEN_UART0_EN		BIT(0)
+#define GIST_DMA_EN		BIT(5)
+#define GIST_UART2_EN		BIT(2)
+#define GIST_UART1_EN		BIT(1)
+#define GIST_UART0_EN		BIT(0)
+#define GIST_UARTx_EN		(GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN)
 
 /* UART config flag, send to sc_io_control if the current UART line has HW
  * flow control lines connected.
  */
-#define UART_CONFIG_HW_FLOW_CONTROL       BIT(0)
+#define UART_CONFIG_HW_FLOW_CONTROL		BIT(0)
 
- /* UART config flag for sc_io_control.  If defined a sc_io_event_rx_msg is
-  * raised only when the rx buffer is completely full. Otherwise, the event
-  * is raised after a timeout is received on the UART line,
-  * and all data received until now is provided.
-  */
-#define UART_CONFIG_DELIVER_FULL_RX_BUF   BIT(1)
+/* UART config flag for sc_io_control.  If defined a sc_io_event_rx_msg is
+ * raised only when the rx buffer is completely full. Otherwise, the event
+ * is raised after a timeout is received on the UART line,
+ * and all data received until now is provided.
+ */
+#define UART_CONFIG_DELIVER_FULL_RX_BUF	BIT(1)
 
 /* UART config flag for sc_io_control.  If defined a sc_io_event_rx_buf_depleted
  * is raised when all rx buffers that were added are full. Otherwise, no
  * event is raised.
  */
-#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2)
+#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF	BIT(2)
 
-#define UART_INT_DEVICES		2
+#define UART_INT_DEVICES		3
 #define UART_EXT_DEVICES		8
 #define UART_DEVICES			UART_INT_DEVICES
 #define UART_ISH_ADDR_INTERVAL		1
 
 #define B9600				0x0000d
 #define B57600				0x00000018
-#define B115200				0x00000011
-#define B921600				0x00000012
+#define B115200			0x00000011
+#define B921600			0x00000012
 #define B2000000			0x00000013
 #define B3000000			0x00000014
 #define B3250000			0x00000015
@@ -223,4 +223,4 @@ struct uart_ctx {
 	uint32_t client_flags;
 };
 
-#endif	/* _CROS_EC_UART_DEFS_H_ */
+#endif /* _CROS_EC_UART_DEFS_H_ */