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| author | Jett Rink <jettrink@chromium.org> | 2019-04-11 10:26:46 -0600 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-18 19:51:25 -0700 |
| commit | 8fce0a9a7d19f040feaec666c58b2c0871db7fc9 (patch) | |
| tree | e7500574eaa63777bbeb0a0a9d90b3853e5220f9 /chip/ish/registers.h | |
| parent | fc2ab5234189258cabc64590b1433545e2cf94fb (diff) | |
| download | chrome-ec-8fce0a9a7d19f040feaec666c58b2c0871db7fc9.tar.gz | |
ish: move register definitions to register.h
Move bit field definitions to register.h close to their register
location definition.
BRANCH=none
BUG=none
TEST=arcada communication still works
Change-Id: I6dfacc24f43a9b8ff490a98c3e231f06f55a1dc6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1564376
Commit-Ready: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index f6e1a292fa..84c6e901fc 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -128,8 +128,13 @@ enum ish_i2c_port { /* IPC_Registers */ #define IPC_PISR (ISH_IPC_BASE + 0x0) +#define IPC_PISR_HOST2ISH_BIT BIT(0) + #define IPC_PIMR (ISH_IPC_BASE + 0x4) -#define IPC_PIMR_CSME_CSR_BIT (0x1 << 23) +#define IPC_PIMR_HOST2ISH_BIT BIT(0) +#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) +#define IPC_PIMR_CSME_CSR_BIT BIT(23) + #define IPC_ISH2HOST_MSG_REGS (ISH_IPC_BASE + 0x60) #define IPC_ISH_FWSTS (ISH_IPC_BASE + 0x34) #define IPC_HOST2ISH_DOORBELL (ISH_IPC_BASE + 0x48) @@ -140,8 +145,11 @@ enum ish_i2c_port { #define IPC_ISH_RMP0 (ISH_IPC_BASE + 0x360) #define IPC_ISH_RMP1 (ISH_IPC_BASE + 0x364) #define IPC_ISH_RMP2 (ISH_IPC_BASE + 0x368) -#define DMA_ENABLED_MASK (0x1 << 0) +#define DMA_ENABLED_MASK BIT(0) + #define IPC_BUSY_CLEAR (ISH_IPC_BASE + 0x378) +#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) + #define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) #define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384) #define IPC_UMA_RANGE_UPPER_0 REG32(ISH_IPC_BASE + 0x388) |