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| author | Jett Rink <jettrink@chromium.org> | 2018-12-21 14:59:57 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-01-30 20:41:18 -0800 |
| commit | 77e81a4a63e3edaaefc110cfa228701ba973aca4 (patch) | |
| tree | 12e056df65baec9e1f08f6f97dff9a38af5270b9 /chip/ish/registers.h | |
| parent | b8b8329840d748037e66f1fe967b205637b116e8 (diff) | |
| download | chrome-ec-77e81a4a63e3edaaefc110cfa228701ba973aca4.tar.gz | |
ish: fix task profiling
Previously when performing 'taskinfo' command on ISH5, the time spend in
exception was very high. The time spent in each task was also negative.
The task profiling was broken in many ways. This CL fixes the following:
- Added correct exception start and end times through out
- Updated exception (isr) start and end time to 32-bit so we don't
have issues with 32-bit time rollover
- Fixed time spending in task, exception, and IRQ distribution
- Fixed code that determines which vector is being serviced. Calculation
before was backwards previously.
- The IRQ_COUNT for ish was too small so we couldn't correctly
profile the IRQ distribution
BRANCH=none
BUG=b:121343650,b:112750896
TEST='taskinfo' behaves correctly on aracada (ISH5)
Change-Id: I643d3133a608865a1862a70585cfeced4d24649d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1389058
Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com>
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index b23890f75a..6137dc6e08 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -59,7 +59,8 @@ enum ish_i2c_port { */ #define USER_VEC_START 32 /* Map IRQs to vectors after offset 10 for certain APIC interrupts */ -#define IRQ_TO_VEC(irq) (irq + USER_VEC_START + 10) +#define IRQ_TO_VEC(irq) ((irq) + USER_VEC_START + 10) +#define VEC_TO_IRQ(vec) ((vec) - USER_VEC_START - 10) /* ISH GPIO Registers */ #define ISH_GPIO_GCCR REG32(ISH_GPIO_BASE + 0x000) /* Direction lock */ |