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| author | Jack Rosenthal <jrosenth@chromium.org> | 2019-04-23 09:32:15 -0600 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-05-02 05:38:23 -0700 |
| commit | 2487d2012337b19e1c409c1ab5c7f763ec40b5b8 (patch) | |
| tree | 1e248be080c2c3530f9bde7ab9b4ec841eb08466 /chip/ish/registers.h | |
| parent | 5e3a5bf39077ea2856d599a7ea7c4643fd5d4acc (diff) | |
| download | chrome-ec-2487d2012337b19e1c409c1ab5c7f763ec40b5b8.tar.gz | |
ish: refactor IPC usage of REG macros into registers.h
This is the final CL needed to resolve b:130573158.
BUG=b:130573158
BRANCH=none
TEST=arcada_ish functions as normal after changes
Change-Id: Ia4cc9bfa95938b9f57fc1cd241cd6821b42a3ce6
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1578435
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 7e6b580d76..7881fd3fe7 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -130,25 +130,25 @@ enum ish_i2c_port { #endif /* IPC_Registers */ -#define IPC_PISR (ISH_IPC_BASE + 0x0) +#define IPC_PISR REG32(ISH_IPC_BASE + 0x0) #define IPC_PISR_HOST2ISH_BIT BIT(0) -#define IPC_PIMR (ISH_IPC_BASE + 0x4) +#define IPC_PIMR REG32(ISH_IPC_BASE + 0x4) #define IPC_PIMR_HOST2ISH_BIT BIT(0) #define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) #define IPC_PIMR_CSME_CSR_BIT BIT(23) -#define IPC_ISH2HOST_MSG_REGS (ISH_IPC_BASE + 0x60) -#define IPC_ISH_FWSTS (ISH_IPC_BASE + 0x34) -#define IPC_HOST2ISH_DOORBELL (ISH_IPC_BASE + 0x48) -#define IPC_HOST2ISH_MSG_REGS (ISH_IPC_BASE + 0xE0) -#define IPC_ISH2HOST_DOORBELL (ISH_IPC_BASE + 0x54) -#define IPC_ISH2PMC_DOORBELL (ISH_IPC_BASE + 0x58) -#define IPC_ISH2PMC_MSG_REGS (ISH_IPC_BASE + 0x260) -#define IPC_ISH_RMP0 (ISH_IPC_BASE + 0x360) -#define IPC_ISH_RMP1 (ISH_IPC_BASE + 0x364) -#define IPC_ISH_RMP2 (ISH_IPC_BASE + 0x368) +#define IPC_ISH2HOST_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0x60) +#define IPC_ISH_FWSTS REG32(ISH_IPC_BASE + 0x34) +#define IPC_HOST2ISH_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x48) +#define IPC_HOST2ISH_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0xE0) +#define IPC_ISH2HOST_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x54) +#define IPC_ISH2PMC_DOORBELL REG32(ISH_IPC_BASE + 0x58) +#define IPC_ISH2PMC_MSG_BASE (ISH_IPC_BASE + 0x260) +#define IPC_ISH_RMP0 REG32(ISH_IPC_BASE + 0x360) +#define IPC_ISH_RMP1 REG32(ISH_IPC_BASE + 0x364) +#define IPC_ISH_RMP2 REG32(ISH_IPC_BASE + 0x368) #define DMA_ENABLED_MASK BIT(0) -#define IPC_BUSY_CLEAR (ISH_IPC_BASE + 0x378) +#define IPC_BUSY_CLEAR REG32(ISH_IPC_BASE + 0x378) #define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) #define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) @@ -340,10 +340,10 @@ enum ish_i2c_port { #if defined(CHIP_FAMILY_ISH3) /* on ISH3, reused ISH2PMC IPC message registers */ -#define SNOWBALL_BASE IPC_ISH2PMC_MSG_REGS +#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE #else /* from ISH4, used reserved rom part of AON memory */ -#define SNOWBALL_BASE CONFIG_ISH_AON_SRAM_ROM_START +#define SNOWBALL_BASE CONFIG_ISH_AON_SRAM_ROM_START #endif /** |