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| author | Hyungwoo Yang <hyungwoo.yang@intel.com> | 2019-05-14 08:23:58 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-05-16 09:04:39 -0700 |
| commit | 0ef828836e412f5acdccbbe6346e6b95841fce3c (patch) | |
| tree | 997c429c0e768c01084cbbcc8e514f67859e9b16 /chip/ish/registers.h | |
| parent | 45434aed20e695e08fcbb3f74c43e03f6fa19bf2 (diff) | |
| download | chrome-ec-0ef828836e412f5acdccbbe6346e6b95841fce3c.tar.gz | |
ish: fix reading current interrupt vector
When we switched to using REG32 macros for registers, we made
a mistake in using address of LAPIC's ISR.
The original CL that changed this was CL:1586458
BRANCH=none
BUG=none
TEST=Tested on Arcada platform
Change-Id: Ia64806a4cb0fa5d150b41407b0f6c9f34f0168e8
Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1611746
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index eb028b403d..1ffd5fad75 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -321,7 +321,8 @@ enum ish_i2c_port { /* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */ #define LAPIC_EOI_REG_ADDR 0xFEE000B0 #define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR) -#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x170) +#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x100) +#define LAPIC_ISR_LAST_REG REG32(ISH_LAPIC_BASE + 0x170) #define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200) #define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280) #define LAPIC_ERR_RECV_ILLEGAL BIT(6) |