diff options
| author | yangcao <yang.a.cao@intel.com> | 2019-02-18 15:29:12 +0800 |
|---|---|---|
| committer | Jett Rink <jettrink@chromium.org> | 2019-02-26 14:32:39 +0000 |
| commit | 456d85195c3ceede52d4c219dfccc51f67b78544 (patch) | |
| tree | 30bb78da742d08083cb26996a5809b2874daa947 /chip/ish/registers.h | |
| parent | 8df604fec43740653366a79f53ec6378b97255f9 (diff) | |
| download | chrome-ec-456d85195c3ceede52d4c219dfccc51f67b78544.tar.gz | |
ish: add reset prep interrupt handle
Upon reset prep interrupt from PMC, ISH HW will do warm reset.
Before full stack of power management in place, this workaround will
help fix S5 issue.
BRANCH=none
BUG=b:123528909
TEST=run "reboot" from host, ISH reboots too.
Change-Id: I421ec25a198eb91672ffe770566a4edbe4855fee
Signed-off-by: yangcao <yang.a.cao@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/1476299
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 00eb5626b9..f245665ca9 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -37,6 +37,7 @@ enum ish_i2c_port { #define ISH_UART_BASE 0x00103000 #define ISH_GPIO_BASE 0x001F0000 #define ISH_PMU_BASE 0x00800000 +#define ISH_CCU_BASE 0x00900000 #define ISH_IPC_BASE 0x00B00000 #define ISH_IOAPIC_BASE 0xFEC00000 #define ISH_HPET_BASE 0xFED00000 @@ -54,6 +55,7 @@ enum ish_i2c_port { #define ISH_IPC_ISH2HOST_CLR_IRQ 24 #define ISH_UART0_IRQ 34 #define ISH_UART1_IRQ 35 +#define ISH_RESET_PREP_IRQ 62 /* Interrupt vectors 0-31 are architecture reserved. * Vectors 32-255 are user-defined. @@ -95,6 +97,7 @@ enum ish_i2c_port { #define ISH_UART0_VEC IRQ_TO_VEC(ISH_UART0_IRQ) #define ISH_UART1_VEC IRQ_TO_VEC(ISH_UART1_IRQ) #define ISH_IPC_VEC IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ) +#define ISH_RESET_PREP_VEC IRQ_TO_VEC(ISH_RESET_PREP_IRQ) #ifdef CONFIG_ISH_UART_0 #define ISH_DEBUG_UART UART_PORT_0 @@ -123,6 +126,21 @@ enum ish_i2c_port { #define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40) #define PMU_VNN_REQ_ACK_STATUS (1 << 0) /* VNN req and ack status */ +#define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c) +#define PMU_RST_PREP_GET (1 << 0) +#define PMU_RST_PREP_AVAIL (1 << 1) +#define PMU_RST_PREP_INT_MASK (1 << 31) + +/* CCU Registers */ +#define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0) +#define CCU_BCG_EN REG32(ISH_CCU_BASE + 0x4) +#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x34) +#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x38) +#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x3c) + +/* CSME Registers */ +#define ISH_RST_REG REG32(ISH_IPC_BASE + 0x44) + /* IOAPIC registers */ #define IOAPIC_IDX 0xFEC00000 #define IOAPIC_WDW 0xFEC00010 |