diff options
author | Hu, Hebo <hebo.hu@intel.com> | 2019-07-04 10:32:52 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2019-07-12 01:11:10 +0000 |
commit | 5c2243bb6b5b0b8a7afe2f79a0388c8ed8391a1a (patch) | |
tree | fb7f43cd306bae68b798313c055542695e0f49d3 /chip/ish/aontaskfw/ish_aontask.lds.S | |
parent | 220d0bf43c6ec01bac79360b99b75199b04d4ada (diff) | |
download | chrome-ec-5c2243bb6b5b0b8a7afe2f79a0388c8ed8391a1a.tar.gz |
ish: fix aon task not auto rebuild issue in increment build
aon task image build rules are lack of dependent rules of source code,
so can't track the source code changes and trigger auto build.
Refactor build rules for aon task to make sure always auto rebuild when
aon task's source code and dependent header files update
BUG=b:136691893
BRANCH=none
TEST= ish aon task should always rebuild when it's code and dependent
header files update
Change-Id: I0d8c7c6a4a2b7e99d724b88b233e09a29b8facea
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688701
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'chip/ish/aontaskfw/ish_aontask.lds.S')
-rw-r--r-- | chip/ish/aontaskfw/ish_aontask.lds.S | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/chip/ish/aontaskfw/ish_aontask.lds.S b/chip/ish/aontaskfw/ish_aontask.lds.S new file mode 100644 index 0000000000..b5361432a2 --- /dev/null +++ b/chip/ish/aontaskfw/ish_aontask.lds.S @@ -0,0 +1,90 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <config_chip.h> + +ENTRY(ish_aon_main); + +#define SRAM_START CONFIG_AON_RAM_BASE +#define SRAM_RW_LEN (CONFIG_AON_RAM_SIZE - CONFIG_AON_PERSISTENT_SIZE) + +/* reserved stack size */ +#define STACK_SIZE (256) + +/** + * resered 8 bytes for GDB showing correct stack + * information during source code level debuging + */ +#define RESERVED_GDB_SIZE (8) + +#define RAM_LEN (SRAM_RW_LEN - STACK_SIZE - RESERVED_GDB_SIZE) + +/** + * AON memory layout + * +---------+------------+-----------------+-----------------+ + * | RAM_LEN | STACK_SIZE | 8 Bytes for GDB | ROM (384 Bytes) | + * +---------+------------+-----------------+-----------------+ + * + * The first 256 bytes of the AON ROM is reserved for ECOS use. + * The remaining 128 bytes of the AON ROM may be used by the shim + * loader. + */ + +/** + * Snowball data + */ +#if defined(CHIP_FAMILY_ISH3) +/* on ISH3, reused ISH2PMC IPC message registers */ +#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE +#else +/* from ISH4, used reserved rom part of AON memory */ +#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256) +#endif +#define SNOWBALL_LEN (4*32) + +MEMORY +{ + /* leave STACK_SIZE bytes in the end of memory for stack */ + RAM : ORIGIN = SRAM_START, LENGTH = RAM_LEN + SNOWBALL : ORIGIN = SNOWBALL_BASE, LENGTH = SNOWBALL_LEN +} + +SECTIONS +{ + /* AON parts visible to FW are linked to the beginning of the AON area */ + .data.aon_share : AT(SRAM_START) + { + KEEP(*(.data.aon_share)) + } > RAM + + .data.snowball : AT(SNOWBALL_BASE) + { + KEEP(*(.data.snowball)) + } > SNOWBALL + + .data : + { + *(.data) + *(.data*) + } > RAM + + .text : + { + *(.text) + *(.text*) + } > RAM + + .bss : + { + *(.bss) + *(.bss*) + } > RAM + + .stack_tag : + { + KEEP(*(.stack_tag)) + } > RAM + +} |