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authorNamyoon Woo <namyoon@google.com>2020-05-13 19:09:35 -0700
committerCommit Bot <commit-bot@chromium.org>2020-06-01 17:49:45 +0000
commit77f11cd9e99bc1d6a63acee45a3d457b7f205523 (patch)
tree801ab6fb0ad27213797a09026645d62d8c3708d4 /board
parent5a60b3b215125e8d2c145e17867fcfaaae682dcd (diff)
downloadchrome-ec-77f11cd9e99bc1d6a63acee45a3d457b7f205523.tar.gz
Introduce TPM_BOARD_CFG register
This patch adds the TPM vendor-defined register, TPM_BOARD_CFG, which indicates the board configuration status. This register is attributed as one-time-programmable and the value is maintained across deep sleeps. Cr50 allows a write on this register right after a cr50 reset until it receives a TPM2_PCR_Extend command. BUG=b:148691139 TEST=none Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I89ae5a53c15990ef78812aec5da81a59f04d7d98 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202838 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
Diffstat (limited to 'board')
-rw-r--r--board/cr50/board.c30
-rw-r--r--board/cr50/board.h22
2 files changed, 52 insertions, 0 deletions
diff --git a/board/cr50/board.c b/board/cr50/board.c
index 355c92ff97..3c73181cc5 100644
--- a/board/cr50/board.c
+++ b/board/cr50/board.c
@@ -1779,3 +1779,33 @@ int board_nvmem_legacy_check_needed(void)
return (h->major_ <= 2) || (h->minor_ <= 18);
}
+
+/*
+ * TPM_BOARD_CFG write is allowed from TPM reset until TPM2_PCR_Extend command
+ * is requested.
+ */
+static bool board_cfg_reg_write_disabled_;
+
+void board_cfg_reg_write_disable(void)
+{
+ board_cfg_reg_write_disabled_ = true;
+}
+
+void board_cfg_reg_write(uint32_t value)
+{
+ /*
+ * If BIOS requested TPM2_PCR_Extended command already or
+ * PWRDN_SCRATCH21 is already written, then do not allow the register
+ * write but return.
+ */
+ if (GREG32(PMU, PWRDN_SCRATCH21) || board_cfg_reg_write_disabled_)
+ return;
+
+ /* Store the tpm_board_cfg in power-down scratch. */
+ GREG32(PMU, PWRDN_SCRATCH21) = value|BOARD_CFG_LOCKED_BIT;
+}
+
+uint32_t board_cfg_reg_read(void)
+{
+ return GREG32(PMU, PWRDN_SCRATCH21);
+}
diff --git a/board/cr50/board.h b/board/cr50/board.h
index ea0ac15dae..67cd0f7faf 100644
--- a/board/cr50/board.h
+++ b/board/cr50/board.h
@@ -407,6 +407,28 @@ void board_unwedge_i2cs(void);
int board_in_prod_mode(void);
+/* Bit masks for each bit in TPM_BOARD_CFG register */
+enum board_cfg_reg_bitmask {
+ BOARD_CFG_LOCKED_BIT = BIT(31),
+};
+
+/* Disable write on TPM_BOARD_CFG register. */
+void board_cfg_reg_write_disable(void);
+
+/*
+ * Write on TPM_BOARD_CFG register if BOARD_CFG_LOCKED_BIT is clear.
+ *
+ * @param value: value to write on TPM_BOARD_CFG
+ */
+void board_cfg_reg_write(unsigned int value);
+
+/*
+ * Read TPM_BOARD_CFG register.
+ *
+ * @param TPM_BOARD_CFG register value in uint32_t type.
+ */
+unsigned int board_cfg_reg_read(void);
+
#endif /* !__ASSEMBLER__ */
/* USB interface indexes (use define rather than enum to expand them) */