diff options
| author | Diana Z <dzigterman@chromium.org> | 2018-10-01 15:14:12 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-08-23 00:12:12 +0000 |
| commit | 15660c77e7e6431874bbcef057f90530daf294e7 (patch) | |
| tree | 907c5477860d5c6b60832107e6ca16d9f9338615 /board | |
| parent | 1181f8fae2abf7ee24d256d8527e5096f264a008 (diff) | |
| download | chrome-ec-15660c77e7e6431874bbcef057f90530daf294e7.tar.gz | |
Octopus: add reset logic for C0 TCPC
This change adds a call to the C0 TCPC reset for standalone TCPC boards
which have that pin hooked up in hardware, and adds the GPIO as
unimplemented for boards which do not have this yet.
BRANCH=None
BUG=b:112756630
TEST=Added a log print and rebooted EC on bobba to verify TCPC C0 reset,
then verified that charging on C0 worked. Also imaged yorp proto 2 and
rebooted, verifying C0 reset was not attempted.
Change-Id: I615861f0d9ce9b5a89692e3982ed2e19c7e0b237
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1257647
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767501
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Tested-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/bobba/gpio.inc | 1 | ||||
| -rw-r--r-- | board/fleex/gpio.inc | 2 | ||||
| -rw-r--r-- | board/meep/gpio.inc | 3 | ||||
| -rw-r--r-- | board/phaser/gpio.inc | 5 | ||||
| -rw-r--r-- | board/yorp/gpio.inc | 3 |
5 files changed, 10 insertions, 4 deletions
diff --git a/board/bobba/gpio.inc b/board/bobba/gpio.inc index 87549022c9..90897bd7a9 100644 --- a/board/bobba/gpio.inc +++ b/board/bobba/gpio.inc @@ -99,7 +99,6 @@ GPIO(EN_USB_A0_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0 5V Charging */ GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_OUT_LOW) /* Enable A1 5V Charging */ GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */ -/* TODO(b/112756630): octopus: add reset logic for C0 TCPC */ GPIO(USB_C0_PD_RST, PIN(8, 3), GPIO_OUT_LOW) /* C0 PD Reset */ GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */ GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */ diff --git a/board/fleex/gpio.inc b/board/fleex/gpio.inc index 3775e7dc70..eeb181bcef 100644 --- a/board/fleex/gpio.inc +++ b/board/fleex/gpio.inc @@ -102,8 +102,6 @@ GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_OUT_LOW) /* Enable A1 5V Charging */ GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */ /* - * TODO(b/112756630): octopus: add reset logic for C0 TCPC - * * Proto USB2_OTG_ID pin * Configure as default since on proto boards this pin should not be driven high */ diff --git a/board/meep/gpio.inc b/board/meep/gpio.inc index a52cac7352..0f95a654e4 100644 --- a/board/meep/gpio.inc +++ b/board/meep/gpio.inc @@ -129,6 +129,9 @@ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) +/* Not implemented in hardware yet */ +UNIMPLEMENTED(USB_C0_PD_RST) + /* * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc index d894541eb6..fbabafd859 100644 --- a/board/phaser/gpio.inc +++ b/board/phaser/gpio.inc @@ -118,7 +118,6 @@ GPIO(EN_USB_A0_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0 5V Charging */ GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_OUT_LOW) /* Enable A1 5V Charging */ GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */ -/* USB_C0_PD_RST_L isn't connected to PIN(6,2) since ANX TCPC doesn't have reset */ GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */ GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */ GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT | /* C0 DP Hotplug Detect */ @@ -128,6 +127,10 @@ GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) + +/* Not implemented in hardware yet */ +UNIMPLEMENTED(USB_C0_PD_RST) + /* * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc index 3fc0394dcc..7f9e804d9a 100644 --- a/board/yorp/gpio.inc +++ b/board/yorp/gpio.inc @@ -126,6 +126,9 @@ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) +/* Not implemented in hardware */ +UNIMPLEMENTED(USB_C0_PD_RST) + /* * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it |