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| author | Gwendal Grignou <gwendal@chromium.org> | 2015-07-25 02:14:13 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-30 19:57:55 +0000 |
| commit | 5b71b33aba6cb0108a864cc7000918b8f06b139a (patch) | |
| tree | aa49a59a306d91b189e9fcdddc3bbb0e2deba628 /board/strago | |
| parent | 9008c7a4fd131a96ccb0078a46ec545cff2f43b1 (diff) | |
| download | chrome-ec-5b71b33aba6cb0108a864cc7000918b8f06b139a.tar.gz | |
common: change interface to SPI flash
Allow more than one SPI master.
Add CONFIG variables to address the system SPI flash.
To have SPI master ports, spi_ports array must be defined.
BRANCH=smaug
TEST=compile
BUG=chrome-os-partner:42304
Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288512
Commit-Queue: David James <davidjames@chromium.org>
Diffstat (limited to 'board/strago')
| -rw-r--r-- | board/strago/board.c | 7 | ||||
| -rw-r--r-- | board/strago/board.h | 3 |
2 files changed, 8 insertions, 2 deletions
diff --git a/board/strago/board.c b/board/strago/board.c index 783b2152bb..24c8fabef0 100644 --- a/board/strago/board.c +++ b/board/strago/board.c @@ -30,6 +30,7 @@ #include "pwm.h" #include "pwm_chip.h" #include "registers.h" +#include "spi.h" #include "temp_sensor.h" #include "temp_sensor_chip.h" #include "thermal.h" @@ -125,6 +126,12 @@ const struct i2c_port_t i2c_ports[] = { }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); +/* SPI master ports */ +const struct spi_device_t spi_devices[] = { + { CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0}, +}; +const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); + const enum gpio_signal hibernate_wake_pins[] = { GPIO_AC_PRESENT, GPIO_LID_OPEN, diff --git a/board/strago/board.h b/board/strago/board.h index 04828dc73f..4a5e783b73 100644 --- a/board/strago/board.h +++ b/board/strago/board.h @@ -46,8 +46,7 @@ #define CONFIG_USBC_SS_MUX #define CONFIG_USBC_VCONN -#define CONFIG_SPI_PORT 1 -#define CONFIG_SPI_CS_GPIO GPIO_PVT_CS0 +#define CONFIG_SPI_FLASH_PORT 1 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SIZE 524288 #define CONFIG_SPI_FLASH_W25Q64 |