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| author | Denis Brockus <dbrockus@chromium.org> | 2019-06-25 12:44:16 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-08-23 00:12:30 +0000 |
| commit | ee8d481a027b78796ce30a48224e043fdf5f7491 (patch) | |
| tree | be23edd0a16a6548302c45da04740ba19809a40e /board/servo_micro | |
| parent | 220205c8480433cb72f7c738ba141d5afa6d1968 (diff) | |
| download | chrome-ec-ee8d481a027b78796ce30a48224e043fdf5f7491.tar.gz | |
Use 7bit I2C/SPI slave addresses in EC
Opt for 7bit slave addresses in EC code. If 8bit is
expected by a driver, make it local and show this in
the naming.
Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase. __7b indicates a
7bit address by itself. __7bf indicates a 7bit address
with optional flags attached. __8b indicates a 8bit
address by itself.
Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.
These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767525
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Tested-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'board/servo_micro')
| -rw-r--r-- | board/servo_micro/board.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/board/servo_micro/board.c b/board/servo_micro/board.c index a06978b84d..cbc5f18f95 100644 --- a/board/servo_micro/board.c +++ b/board/servo_micro/board.c @@ -248,8 +248,8 @@ DECLARE_CONSOLE_COMMAND(baud, command_uart_baud, * enable_ite_dfu stops working, or does not work on a new ITE EC chip revision. */ -#define ITE_DFU_I2C_CMD_ADDR 0xB4 /* 7 bit form is 0x5A */ -#define ITE_DFU_I2C_DATA_ADDR 0x6A /* 7 bit form is 0x35 */ +#define ITE_DFU_I2C_CMD_ADDR__7bf 0x5A +#define ITE_DFU_I2C_DATA_ADDR__7bf 0x35 #define SMCLK_WAVEFORM_PERIOD_HZ (100 * KHz) #define SMDAT_WAVEFORM_PERIOD_HZ (200 * KHz) @@ -287,14 +287,17 @@ static int ite_i2c_read_register(uint8_t register_offset, uint8_t *output) */ int ret; /* Tell the ITE EC which register we want to read. */ - ret = i2c_xfer_unlocked(I2C_PORT_MASTER, ITE_DFU_I2C_CMD_ADDR, - ®ister_offset, sizeof(register_offset), - NULL, 0, I2C_XFER_SINGLE); + ret = i2c_xfer_unlocked__7bf(I2C_PORT_MASTER, + ITE_DFU_I2C_CMD_ADDR__7bf, + ®ister_offset, sizeof(register_offset), + NULL, 0, I2C_XFER_SINGLE); if (ret != EC_SUCCESS) return ret; /* Read in the 1 byte register value. */ - ret = i2c_xfer_unlocked(I2C_PORT_MASTER, ITE_DFU_I2C_DATA_ADDR, NULL, 0, - output, sizeof(*output), I2C_XFER_SINGLE); + ret = i2c_xfer_unlocked__7bf(I2C_PORT_MASTER, + ITE_DFU_I2C_DATA_ADDR__7bf, + NULL, 0, + output, sizeof(*output), I2C_XFER_SINGLE); return ret; } |