quiche: Add support for C2 usbc port

The 3rd usbc port (C2) is type-c only port which is managed directly
by the PS8803 TCPC, but C2 has a PPC and the EC needs to control VBUS
on/off via the PPC.

This CL adds an interrupt handler to track the signal that indicates
when the TCPC is in Attached.SRC or Unattached.SRC. In addition, the
PPC for C2 must be initialized at the board level as this port is not
managed by the TCPMv2 stack.

BUG=b:171915198
BRANCH=None
TEST=Used C -> A adapter, verifed that when connected C2 is in
Attached.src and removed in Unattached.SRC. Validated bus signals with
TotalPhase trace. Also checked have a device connected to this port
enumerates at the host.

> [28.613330 C2: State = Unattached.SRC]
[36.500398 C2: State = Attached.SRC ]

[135240.133949] usb 1-2.2.1: new full-speed USB device number 87 ...
[135240.229223] usb 1-2.2.1: New USB device found, idVendor=046d, ...
[135240.229246] usb 1-2.2.1: New USB device strings: Mfr=1, ...
[135240.229257] usb 1-2.2.1: Product: BOOM 3
[135240.229267] usb 1-2.2.1: Manufacturer: Logitech
[135240.229276] usb 1-2.2.1: SerialNumber: 000001

Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Ie2583ae9271333e2ecd9561eed60fab6cdb4fda1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2519799
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>

3 files changed, 71 insertions, 7 deletions

diff --git a/board/quiche/board.c b/board/quiche/board.c
index 45dbe7d2dc..a7f354e654 100644
--- a/board/quiche/board.c
+++ b/board/quiche/board.c
@@ -78,6 +78,25 @@ void hpd_interrupt(enum gpio_signal signal)
 {
 	usb_pd_hpd_edge_event(signal);
 }
+
+void board_uf_manage_vbus(void)
+{
+	int level = gpio_get_level(GPIO_USBC_UF_MUX_VBUS_EN);
+
+	/*
+	 * GPIO_USBC_UF_MUX_VBUS_EN is an output from the PS8803 which tracks if
+	 * C2 is attached. When it's attached, this signal will be high. Use
+	 * this level to control PPC VBUS on/off.
+	 */
+	ppc_vbus_source_enable(USB_PD_PORT_USB3, level);
+	CPRINTS("C2: State = %s", level ? "Attached.SRC " : "Unattached.SRC");
+}
+DECLARE_DEFERRED(board_uf_manage_vbus);
+
+static void board_uf_manage_vbus_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&board_uf_manage_vbus_data, 0);
+}
 #endif /* SECTION_IS_RW */
 
 #include "gpio_list.h" /* Must come after other header files. */
@@ -182,6 +201,11 @@ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.i2c_addr_flags = SN5S330_ADDR2_FLAGS,
 		.drv = &sn5s330_drv
 	},
+	[USB_PD_PORT_USB3] = {
+		.i2c_port = I2C_PORT_I2C3,
+		.i2c_addr_flags = SN5S330_ADDR1_FLAGS,
+		.drv = &sn5s330_drv
+	},
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -221,6 +245,40 @@ enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
 	return pd_dual_role_init[port];
 }
 
+static void board_config_usbc_uf_ppc(void)
+{
+	int vbus_level;
+
+	/*
+	 * This port is not usb-pd capable, but there is a ppc which must be
+	 * initialized, and keep the VBUS switch enabled.
+	 */
+	ppc_init(USB_PD_PORT_USB3);
+	vbus_level = gpio_get_level(GPIO_USBC_UF_MUX_VBUS_EN);
+
+	CPRINTS("usbc: UF PPC configured. VBUS = %s",
+		vbus_level ? "on" : "off");
+
+	/*
+	 * Check initial state as there there may not be an edge event after
+	 * interrupts are enabled if the port is attached at EC reboot time.
+	 */
+	ppc_vbus_source_enable(USB_PD_PORT_USB3, vbus_level);
+
+	/* Enable VBUS control interrupt for C2 */
+	gpio_enable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
+}
+
+__override uint8_t board_get_usb_pd_port_count(void)
+{
+	/*
+	 * CONFIG_USB_PD_PORT_MAX_COUNT must be defined to account for C0, C1,
+	 * and C2, but TCPMv2 only knows about C0 and C1, as C2 is a type-c only
+	 * port that is managed directly by the PS8803 TCPC.
+	 */
+	return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
+}
+
 int ppc_get_alert_status(int port)
 {
 	if (port == USB_PD_PORT_HOST)
@@ -251,7 +309,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 static void board_init(void)
 {
 #ifdef SECTION_IS_RW
-
+	board_config_usbc_uf_ppc();
 #endif
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/quiche/board.h b/board/quiche/board.h
index 16bd2de2b7..0de8572604 100644
--- a/board/quiche/board.h
+++ b/board/quiche/board.h
@@ -16,9 +16,16 @@
 
 /* USB Type C and USB PD defines */
 #define USB_PD_PORT_HOST   0
-#define USB_PD_PORT_DP   1
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define USB_PD_PORT_DP     1
+#define USB_PD_PORT_USB3   2
+
+/*
+ * The host (C0) and display (C1) usbc ports are usb-pd capable. There is
+ * also a type-c only port (C2). C2 must be accounted for in PORT_MAX_COUNT so
+ * the PPC config table is correctly sized and the PPC driver can be used to
+ * control VBUS on/off.
+ */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 3
 #define CONFIG_USB_MUX_PS8822
 
 #define CONFIG_USB_PID 0x5048
@@ -26,13 +33,11 @@
 #define CONFIG_USB_PD_IDENTITY_HW_VERS 1
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 
-/* USB Type A Features */
-
-
 /* I2C port names */
 #define I2C_PORT_I2C1	0
 #define I2C_PORT_I2C2	1
 #define I2C_PORT_I2C3	2
+
 /* Required symbolic I2C port names */
 #define I2C_PORT_MP4245 I2C_PORT_I2C3
 #define I2C_PORT_EEPROM I2C_PORT_I2C3
diff --git a/board/quiche/gpio.inc b/board/quiche/gpio.inc
index 7e3b9345e6..76b1dfb90e 100644
--- a/board/quiche/gpio.inc
+++ b/board/quiche/gpio.inc
@@ -13,6 +13,7 @@ GPIO_INT(HOST_USBC_PPC_INT_ODL,  PIN(D,  9),      GPIO_INT_FALLING | GPIO_PULL_U
 GPIO_INT(USBC_DP_MUX_ALERT_ODL,  PIN(B,  1),      GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
 GPIO_INT(USBC_DP_PPC_INT_ODL,    PIN(E,  7),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
 GPIO_INT(DDI_MST_IN_HPD,         PIN(C,  14),     GPIO_INT_BOTH, hpd_interrupt)
+GPIO_INT(USBC_UF_MUX_VBUS_EN,    PIN(C,  12),     GPIO_INT_BOTH, board_uf_manage_vbus_interrupt)
 #endif
 
 /* Power sequencing signals */