diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2015-08-18 13:09:59 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-19 08:10:27 +0000 |
| commit | 8c633e5af603687d178047930dc502c7deefe0ae (patch) | |
| tree | 18ef227d5d2f8ae071ceb819ae4beb9383956eef /board/npcx_evb | |
| parent | b3d1171d42803d40e7a1f83375a1f3c69b1fbd07 (diff) | |
| download | chrome-ec-8c633e5af603687d178047930dc502c7deefe0ae.tar.gz | |
nuc:
Modified i2c driver into controllers and ports to support I2C0 port 0/1 at
the same time.
Modified drivers:
1. i2c.c: Support i2c controller mechanism and fixed bug for i2c_raw functions
used by i2c_wedge and i2c_unwedge.
2. gpio.c: Fixed bug for gpio_alt_sel since wrong type of func.
3. lpc.c: Fixed bug for port80. Since disabling SUPPORT_P80_SEG, we should
replace GLUE_SDP0/1 with DP80BUF.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I9919269e4f5e795d9ceb8a4cd2c39abbd7bb6b1a
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/294015
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board/npcx_evb')
| -rw-r--r-- | board/npcx_evb/board.c | 7 | ||||
| -rw-r--r-- | board/npcx_evb/board.h | 3 | ||||
| -rw-r--r-- | board/npcx_evb/gpio.inc | 19 |
3 files changed, 18 insertions, 11 deletions
diff --git a/board/npcx_evb/board.c b/board/npcx_evb/board.c index 8b3a72304d..3e438bb6b0 100644 --- a/board/npcx_evb/board.c +++ b/board/npcx_evb/board.c @@ -110,8 +110,11 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - {"master", I2C_PORT_MASTER, 100, - GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA}, + {"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0}, + {"master0-1", NPCX_I2C_PORT0_1, 100, GPIO_I2C0_SCL1, GPIO_I2C0_SDA1}, + {"master1", NPCX_I2C_PORT1, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA}, + {"master2", NPCX_I2C_PORT2, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, + {"master3", NPCX_I2C_PORT3, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA}, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); diff --git a/board/npcx_evb/board.h b/board/npcx_evb/board.h index 1553edba3f..7f1b3529a4 100644 --- a/board/npcx_evb/board.h +++ b/board/npcx_evb/board.h @@ -46,7 +46,6 @@ /* Optional feature - used by nuvoton */ #define NPCX_PWM_INPUT_LFCLK /* PWM use LFCLK for input clock */ #define NPCX_MFT_INPUT_LFCLK /* MFT use LFCLK for input clock */ -#define NPCX_I2C0_BUS2 0 /* 0:GPIOB4/B5 1:GPIOB2/B3 as I2C0 */ #define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ #define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ @@ -56,7 +55,7 @@ #undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ /* Single I2C port, where the EC is the master. */ -#define I2C_PORT_MASTER 0 +#define I2C_PORT_MASTER NPCX_I2C_PORT0_0 #define I2C_PORT_HOST 0 #ifndef __ASSEMBLER__ diff --git a/board/npcx_evb/gpio.inc b/board/npcx_evb/gpio.inc index 149b045a7a..7c7ae2f10d 100644 --- a/board/npcx_evb/gpio.inc +++ b/board/npcx_evb/gpio.inc @@ -27,8 +27,16 @@ GPIO(SPI_CS_L, PIN(A, 5), GPIO_OUT_HIGH) * I2C pins should be configured as inputs until I2C module is * initialized. This will avoid driving the lines unintentionally. */ -GPIO(MASTER_I2C_SCL, PIN(B, 5), GPIO_INPUT) -GPIO(MASTER_I2C_SDA, PIN(B, 4), GPIO_INPUT) +GPIO(I2C0_SCL0, PIN(B, 5), GPIO_ODR_HIGH) +GPIO(I2C0_SDA0, PIN(B, 4), GPIO_ODR_HIGH) +GPIO(I2C0_SCL1, PIN(B, 3), GPIO_ODR_HIGH) +GPIO(I2C0_SDA1, PIN(B, 2), GPIO_ODR_HIGH) +GPIO(I2C1_SCL, PIN(9, 0), GPIO_ODR_HIGH) +GPIO(I2C1_SDA, PIN(8, 7), GPIO_ODR_HIGH) +GPIO(I2C2_SCL, PIN(9, 2), GPIO_ODR_HIGH) +GPIO(I2C2_SDA, PIN(9, 1), GPIO_ODR_HIGH) +GPIO(I2C3_SCL, PIN(D, 1), GPIO_ODR_HIGH) +GPIO(I2C3_SDA, PIN(D, 0), GPIO_ODR_HIGH) /* Used for board version command */ GPIO(BOARD_VERSION1, PIN(6, 4), GPIO_INPUT) /* Board version stuffing resistor 1 */ @@ -45,11 +53,8 @@ ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0) /* CR_SIN/SOUT #else ALTERNATE(PIN_MASK(1, 0x03), 1, MODULE_UART, 0) /* CR_SIN/SOUT GPIO10/11 */ #endif -#if NPCX_I2C0_BUS2 -ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* I2C0SDA/I2C0SCL GPIOB2/B3 */ -#else -ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0) /* I2C0SDA/I2C0SCL GPIOB4/B5 */ -#endif +ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* I2C0SDA1/I2C0SCL1 GPIOB2/B3 */ +ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0) /* I2C0SDA0/I2C0SCL0 GPIOB4/B5 */ ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* I2C1SDA GPIO87 */ ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0) /* I2C1SCL/I2C2SDA/I2C2SCL GPIO90/91/92 */ ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3SDA/I2C3SCL GPIOD0/D1 */ |