nuc: Simplify adc/pwm/fan drivers and related structures in boards

Modified drivers:
1. register.h: Add marco field operation funcs for muti-bits field of register.
2. adc.c/fan.c/pwm.c: Simplify field operations by marco funcs.
3. adc.c: Add support for ADC_CH3/4
4. pwm.c: Add PWM_CONFIG_DSLEEP_CLK flag
6. fan.c: Support multi-fans mechanism

BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none

Change-Id: Iaaeb6c4ae8d55b4245a1cefb9c20feae4c0fdec2
Reviewed-on: https://chromium-review.googlesource.com/300673
Commit-Ready: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

3 files changed, 10 insertions, 45 deletions

diff --git a/board/npcx_evb/board.c b/board/npcx_evb/board.c
index 3e438bb6b0..e5b70d7f7d 100644
--- a/board/npcx_evb/board.c
+++ b/board/npcx_evb/board.c
@@ -36,43 +36,17 @@
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_INPUT_CH0, ADC_MAX_VOLT,
-			ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_INPUT_CH1, ADC_MAX_VOLT,
-			ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_INPUT_CH2, ADC_MAX_VOLT,
-			ADC_READ_MAX+1, 0},
+	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] =	{
-			.channel = 0,
-			/*
-			 * flags can reverse the PWM output signal according to
-			 * the board design
-			 */
-			.flags = PWM_CONFIG_ACTIVE_LOW,
-			/*
-			 * freq_operation = freq_input / prescaler_divider
-			 * freq_output = freq_operation / cycle_pulses
-			 * and freq_output <= freq_mft
-			 */
-			.freq = 34,
-			/*
-			 * cycle_pulses = (cycle_pulses * freq_output) *
-			 * RPM_EDGES * RPM_SCALE * 60 / poles / rpm_min
-			 */
-			.cycle_pulses = 480,
-	},
-	[PWM_CH_KBLIGHT] = {
-			.channel = 1,
-			.flags = 0,
-			.freq = 10000,
-			.cycle_pulses = 100,
-			},
+	[PWM_CH_FAN] = { 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP_CLK, 100},
+	[PWM_CH_KBLIGHT] = { 1, 0, 10000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -84,7 +58,7 @@ const struct fan_t fans[] = {
 		.rpm_min = 1020,
 		.rpm_start = 1020,
 		.rpm_max = 8190,
-		.ch = 0,/* Use PWM/MFT to control fan */
+		.ch = 0,/* Use MFT id to control fan */
 		.pgood_gpio = GPIO_PGOOD_FAN,
 		.enable_gpio = -1,
 	},
@@ -94,16 +68,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from mft_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] =    {
-			.module = NPCX_MFT_MODULE_1,
-			.port = NPCX_MFT_MODULE_PORT_TA,
-			.default_count = 0xFFFF,
-#ifdef NPCX_MFT_INPUT_LFCLK
-			.freq = 32768,
-#else
-			.freq = 2000000,
-#endif
-			},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, 0xFFFF, TCKC_LFCLK, PWM_CH_FAN},
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
diff --git a/board/npcx_evb/board.h b/board/npcx_evb/board.h
index fd0ff65e75..316ca3ede7 100644
--- a/board/npcx_evb/board.h
+++ b/board/npcx_evb/board.h
@@ -10,7 +10,6 @@
 
 /* Optional modules */
 #define CONFIG_ADC
-#define CONFIG_PECI
 #define CONFIG_PWM
 #define CONFIG_SPI
 #define CONFIG_LPC /* Used in Intel-based platform for host interface */
@@ -41,8 +40,6 @@
 #define CONFIG_FANS                     1
 
 /* Optional feature - used by nuvoton */
-#define NPCX_PWM_INPUT_LFCLK   /* PWM use LFCLK for input clock */
-#define NPCX_MFT_INPUT_LFCLK   /* MFT use LFCLK for input clock */
 #define NPCX_UART_MODULE2    0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
 #define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
 #define NPCX_TACH_SEL2       0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */
diff --git a/board/npcx_evb/gpio.inc b/board/npcx_evb/gpio.inc
index 7c7ae2f10d..027855620b 100644
--- a/board/npcx_evb/gpio.inc
+++ b/board/npcx_evb/gpio.inc
@@ -62,9 +62,12 @@ ALTERNATE(PIN_MASK(4, 0x38), 1,  MODULE_ADC,         0)    /* ADC
 ALTERNATE(PIN_MASK(A, 0x0A), 1,  MODULE_SPI,         0)    /* SPIP_MOSI/SPIP_SCLK     GPIOA3/A1	   */
 ALTERNATE(PIN_MASK(9, 0x20), 1,  MODULE_SPI,         0)    /* SPIP_MISO               GPIO95       */
 ALTERNATE(PIN_MASK(C, 0x04), 3,  MODULE_PWM_KBLIGHT, 0)    /* PWM1 for PWM/KBLIGHT Test GPIOC2     */
+/* Alternative functionality for FANS */
+#ifdef CONFIG_FANS
 ALTERNATE(PIN_MASK(C, 0x08), 7,  MODULE_PWM_FAN,     0)    /* PWM0 for PWM/FAN Test   GPIOC3       */
 #if NPCX_TACH_SEL2
 ALTERNATE(PIN_MASK(9, 0x08), 3,  MODULE_PWM_FAN,     0)    /* MFT-1/TA1_TACH1 for FAN GPIO93       */
 #else
 ALTERNATE(PIN_MASK(4, 0x01), 3,  MODULE_PWM_FAN,     0)    /* MFT-1/TA1_TACH1 for FAN Test GPIO40  */
 #endif
+#endif