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authorMulin Chao <mlchao@nuvoton.com>2017-03-22 17:42:34 +0800
committerchrome-bot <chrome-bot@chromium.org>2017-03-24 06:49:55 -0700
commite43ba03ebf3c921f2abfd4e9153725e87f28da62 (patch)
treee25bf9ac0b742400e88b83ea95b673fa40ccedeb /board/npcx_evb
parent61f61b368eeacc3c4d4627bdfa8d81e9b6538675 (diff)
downloadchrome-ec-e43ba03ebf3c921f2abfd4e9153725e87f28da62.tar.gz
npcx: Move pwm open-drain functionality from gpio to pwm driver.
Setting PWM IO type in gpio driver seems not a proper way. This CL moves this functionality to pwm driver and introduces a new flag PWM_CONFIG_OPEN_DRAIN to achieve it when user declared it in board driver. BRANCH=none BUG=none TEST=test pwm functionality on npcx_evb. Change-Id: I90c60445d1fb10902244ddf0f635d8304e72f4ab Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/458043 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'board/npcx_evb')
-rw-r--r--board/npcx_evb/board.c2
-rw-r--r--board/npcx_evb/gpio.inc8
2 files changed, 5 insertions, 5 deletions
diff --git a/board/npcx_evb/board.c b/board/npcx_evb/board.c
index 8a3d1b8c5d..baaf040e15 100644
--- a/board/npcx_evb/board.c
+++ b/board/npcx_evb/board.c
@@ -45,7 +45,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/******************************************************************************/
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
- [PWM_CH_FAN] = { 0, PWM_CONFIG_DSLEEP, 100},
+ [PWM_CH_FAN] = { 0, PWM_CONFIG_DSLEEP | PWM_CONFIG_OPEN_DRAIN, 100},
[PWM_CH_KBLIGHT] = { 1, 0, 10000 },
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/board/npcx_evb/gpio.inc b/board/npcx_evb/gpio.inc
index b8d08ec9a4..25454bd7fb 100644
--- a/board/npcx_evb/gpio.inc
+++ b/board/npcx_evb/gpio.inc
@@ -70,14 +70,14 @@ ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3SDA/I2C3SCL
ALTERNATE(PIN_MASK(4, 0x38), 1, MODULE_ADC, 0) /* ADC GPIO45/44/43 */
ALTERNATE(PIN_MASK(A, 0x0A), 1, MODULE_SPI, 0) /* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0) /* SPIP_MISO GPIO95 */
-ALTERNATE(PIN_MASK(C, 0x04), 3, MODULE_PWM, 0) /* PWM1 for PWM/KBLIGHT Test GPIOC2 */
+ALTERNATE(PIN_MASK(C, 0x04), 1, MODULE_PWM, 0) /* PWM1 for PWM/KBLIGHT Test GPIOC2 */
/* Alternative functionality for FANS */
#ifdef CONFIG_FANS
-ALTERNATE(PIN_MASK(C, 0x08), 7, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */
+ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */
#if NPCX_TACH_SEL2
-ALTERNATE(PIN_MASK(9, 0x08), 3, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN GPIO93 */
+ALTERNATE(PIN_MASK(9, 0x08), 1, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN GPIO93 */
#else
-ALTERNATE(PIN_MASK(4, 0x01), 3, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN Test GPIO40 */
+ALTERNATE(PIN_MASK(4, 0x01), 1, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN Test GPIO40 */
#endif
#endif