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| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-08-05 13:59:28 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-07 05:05:21 +0000 |
| commit | 265cafd2bdd62c6b4c7900b4fc5024558637ed1e (patch) | |
| tree | 1de92b0fb5d1fccccb03921fffe7e2dd7ed45caa /board/it8xxx2_pdevb | |
| parent | c91b9e81055ede0c67f0126a104bbd9afa703c7c (diff) | |
| download | chrome-ec-265cafd2bdd62c6b4c7900b4fc5024558637ed1e.tar.gz | |
it8xxx2_pdevb ,reef_it8320: enable TCPMv2
Enable TCPMv2 on board it8xxx2_pdevb and reef_it8320.
BUG=none
BRANCH=none
TEST=TCPMv2 can run on board it8xxx2_pdevb and reef_it8320.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I8bdfc2f2b0642bb406f360c6d0a3b1f1c637b5ba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2334433
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'board/it8xxx2_pdevb')
| -rw-r--r-- | board/it8xxx2_pdevb/board.c | 7 | ||||
| -rw-r--r-- | board/it8xxx2_pdevb/board.h | 6 |
2 files changed, 12 insertions, 1 deletions
diff --git a/board/it8xxx2_pdevb/board.c b/board/it8xxx2_pdevb/board.c index df242908b7..015a0e6d89 100644 --- a/board/it8xxx2_pdevb/board.c +++ b/board/it8xxx2_pdevb/board.c @@ -5,6 +5,7 @@ /* IT8xxx2 PD development board configuration */ #include "adc_chip.h" +#include "battery.h" #include "console.h" #include "it83xx_pd.h" #include "pwm.h" @@ -25,6 +26,12 @@ int board_get_battery_soc(void) return 100; } +enum battery_present battery_is_present(void) +{ + CPRINTS("%s", __func__); + return BP_NO; +} + const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USB_PD_PORT_ITE_0] = { .bus_type = EC_BUS_TYPE_EMBEDDED, diff --git a/board/it8xxx2_pdevb/board.h b/board/it8xxx2_pdevb/board.h index 55c335a9d8..79062b5594 100644 --- a/board/it8xxx2_pdevb/board.h +++ b/board/it8xxx2_pdevb/board.h @@ -47,7 +47,11 @@ #define CONFIG_USB_PD_DUAL_ROLE #define CONFIG_USB_PD_PORT_MAX_COUNT 3 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 3 -#define CONFIG_USB_PD_TCPMV1 +#define CONFIG_USB_PD_TCPMV2 +#define CONFIG_USB_DRP_ACC_TRYSRC +#define CONFIG_USB_PD_REV30 +#define CONFIG_USB_PID 0x1234 /* Invalid PID for development board */ +#define CONFIG_USB_PD_DEBUG_LEVEL 2 #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP #define CONFIG_USB_PD_TRY_SRC #define CONFIG_USB_PD_VBUS_DETECT_GPIO |