diff options
| author | Steven Jian <steven.jian@intel.com> | 2015-04-01 01:25:42 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-27 03:58:16 +0000 |
| commit | 937cc8a64e5971def21303e7a19a4ad9553e0ace (patch) | |
| tree | 321543152e0c4d61e686ca7b92edd0d027bb168b /board/glados/lfw | |
| parent | e216906c9327655d71b8758b7f11c2f744e55018 (diff) | |
| download | chrome-ec-937cc8a64e5971def21303e7a19a4ad9553e0ace.tar.gz | |
mec1322: Simplify GPIO lists
Our existing GPIO macros use port# / gpio#, but the concept of different
GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros
for chips which do not have distinct GPIO ports.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b
Signed-off-by: Steven Jian <steven.jian@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/262841
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Diffstat (limited to 'board/glados/lfw')
| -rw-r--r-- | board/glados/lfw/gpio.inc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/glados/lfw/gpio.inc b/board/glados/lfw/gpio.inc index f7500436eb..b7743916bc 100644 --- a/board/glados/lfw/gpio.inc +++ b/board/glados/lfw/gpio.inc @@ -8,12 +8,12 @@ */ /* SPI PVT chip select */ -GPIO(PVT_CS0, PORT(14), 6, GPIO_ODR_HIGH) +GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH) /* Alternate functions GPIO definition */ /* UART */ -ALTERNATE(PORT(16), 0x24, 1, MODULE_UART, 0) +ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0) /* SPI pins */ -ALTERNATE(PORT(5), 0x10, 1, MODULE_SPI, 0) -ALTERNATE(PORT(16), 0x10, 1, MODULE_SPI, 0) -ALTERNATE(PORT(15), 0x08, 1, MODULE_SPI, 0) +ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0) +ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0) +ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0) |