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author | Namyoon Woo <namyoon@google.com> | 2020-05-14 12:18:42 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-06-01 17:49:45 +0000 |
commit | ea0fd78e5e218ef50ba947f4c921ae91a69b5442 (patch) | |
tree | 70b56acd6b6e8218c0b9ab5e940a2bdfd616f9c1 /board/cr50/board.c | |
parent | 77f11cd9e99bc1d6a63acee45a3d457b7f205523 (diff) | |
download | chrome-ec-ea0fd78e5e218ef50ba947f4c921ae91a69b5442.tar.gz |
Introduce BOARD_CFG_LONG_INT_AP_BIT in TPM_BOARD_CFG register
This patch assigns the bit offset 0 in TPM_BOARD_CFG register to
indicate the status of INT_AP_L extension. The bit 1 means INT_AP_L
pulse extension is activated, and 0 means it is not.
BUG=b:148691139
TEST=tested on atlas and on careena.
1. Checked the default TPM_BOARD_CFG (PWRDN_SCRATCH21) value was zero
and the INT_AP_L assertion duration was 4~10 microseconds.
> md 0x400000f4 1 // memory dump on GC_PMU_PWRDN_SCRATCH21
400000F4: 0x00000000
2. Attempted to change the board configuration (with a hacked UART
command.). The register value was unchanged.
> brdcfg 0x01
TPM_BOARD_CFG = 0x00000000
> md 0x400000f4 1
400000F4: 0x00000000
3. Forced to write the board configuration with a hacked UART command.
The register value was changed.
> brdcfg 0x01 force
TPM_BOARD_CFG = 0x80000001
> md 0x400000f4 1
400000F4: 0x80000001
4. Checked the INT_AP_L assertion duration extended to 110
microseconds or longer.
5. After cr50 deep sleep, checked the pulse duration was still
extended.
- turned AP off.
- disconnected Suzy-Qable.
- waited three seconds
- connected Suzy-Qable, and checked the reset cause was 'hibernate
rbox'.
> md 0x400000f4 1
400000F4: 0x8000001
6. With 100 usec long INT_AP pulse, checked trunks_cliend
regression_test, stress_test and ext_command_test runs good.
Checked dmesg and found no TPM errors through all tests.
(ap) $ trunks_client --regression_test
(ap) $ trunks_client --stress_test
(ap) $ trunks_client --ext_command_test
7.checked no character loss during uart_stress_tester.
(chroot) $ uart_stress_tester.py -c -t 600 /dev/ttyUSB2 /dev/ttyUSB1
8. the shortest duration of INT_AP_L assertion and deassertion
observed in logic analyzer were 110 usec and 152 usec.
9. measured the depthcharge exit timestamp and cr50 flash time with
or without INT_AP pulse extended to 100 usec, on atlas and helios:
-----------------+-------------------+------------------
| atlas | helios
-----------------+-------------------+------------------
boot (sec) | 1.398 -> 1.402 | 1.004 -> 1.011
cr50 flash (sec) | 10.800 -> 14.609 | 16.024 -> 16.466
-----------------+-------------------+------------------
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: I2b9f9defb63cf05f9d91b741ccb4b49c4c6bc8e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202839
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
Diffstat (limited to 'board/cr50/board.c')
-rw-r--r-- | board/cr50/board.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/board/cr50/board.c b/board/cr50/board.c index 3c73181cc5..e20810cd42 100644 --- a/board/cr50/board.c +++ b/board/cr50/board.c @@ -763,6 +763,15 @@ static void maybe_trigger_ite_sync(void) generate_ite_sync(); } +static void process_board_cfg(void) +{ + uint32_t tpm_board_cfg = board_cfg_reg_read(); + + if (tpm_board_cfg & BOARD_CFG_LONG_INT_AP_BIT) + int_ap_extension_enable(); +} +DECLARE_DEFERRED(process_board_cfg); + /* Initialize board. */ static void board_init(void) { @@ -856,6 +865,8 @@ static void board_init(void) * machines run in HOOK_SECOND, which first triggers right after * HOOK_INIT, not at +1.0 seconds. */ + + process_board_cfg(); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_CR50_BOARD); @@ -1803,6 +1814,9 @@ void board_cfg_reg_write(uint32_t value) /* Store the tpm_board_cfg in power-down scratch. */ GREG32(PMU, PWRDN_SCRATCH21) = value|BOARD_CFG_LOCKED_BIT; + + /* Process board_configuration change in a deferred function */ + hook_call_deferred(&process_board_cfg_data, 0); } uint32_t board_cfg_reg_read(void) |