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| author | Furquan Shaikh <furquan@chromium.org> | 2017-09-23 01:15:53 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-10-03 17:28:28 -0700 |
| commit | 04db902fee7dc7ae615fbb22454dc247a534c1f0 (patch) | |
| tree | 4edb40bb519b0ce9acae506b0d899ed529649ae3 /board/coral | |
| parent | 81682e06bc94d1b9e702b9794349bd34594896b3 (diff) | |
| download | chrome-ec-04db902fee7dc7ae615fbb22454dc247a534c1f0.tar.gz | |
intel_x86: Enable/disable SLP_S0 signal based on S0ix entry/exit
Runtime S0ix results in SLP_S0 signal being toggled continuously
resulting in an interrupt storm on the EC. In order to avoid this,
enable SLP_S0 power signal only when host indicates intent to enter
S0ix and disable when host exits from S0ix.
BUG=b:65421825
BRANCH=None
TEST=Verified that runtime S0ix no longer results in interrupt storm
on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0
using powerindebug.
Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'board/coral')
| -rw-r--r-- | board/coral/board.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/board/coral/board.c b/board/coral/board.c index ee5db6d899..e8d7ad537d 100644 --- a/board/coral/board.c +++ b/board/coral/board.c @@ -127,7 +127,9 @@ void tablet_mode_interrupt(enum gpio_signal signal) /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { #ifdef CONFIG_POWER_S0IX - {GPIO_PCH_SLP_S0_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S0_DEASSERTED"}, + {GPIO_PCH_SLP_S0_L, + POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT, + "SLP_S0_DEASSERTED"}, #endif {GPIO_RSMRST_L_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "RSMRST_L"}, {GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"}, |