diff options
| author | Caveh Jalali <caveh@chromium.org> | 2018-05-04 15:07:16 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-05-08 01:22:00 -0700 |
| commit | 72343b097eeb51eff76e8478914b1f5d83a16610 (patch) | |
| tree | a34163b755722dc1792e8ed24e3e402c814a021e /board/atlas | |
| parent | 0f9a4fba96dbef6755a21c96eabf445075b182ef (diff) | |
| download | chrome-ec-72343b097eeb51eff76e8478914b1f5d83a16610.tar.gz | |
atlas: config PROCHOT GPIO as input
we need to configure EC_PROCHOT_ODL as an input because the EC isn't
driving it correctly. we changed the polarity of EC_PROCHOT for atlas
and similar boards, but the EC codebase has this hard-coded as
active-high.
this is a short-term fix until we implement a more general PROCHOT
"polarity" feature.
BUG=b:78911901,b:79266467
BRANCH=none
TEST=checked voltage drop across in-line resistor on EC_PROCHOT and
AP can now run above 400MHz
Change-Id: I8c3224c62ea7af4f386062d39c248d418e73fa53
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1045556
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Diffstat (limited to 'board/atlas')
| -rw-r--r-- | board/atlas/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/atlas/gpio.inc b/board/atlas/gpio.inc index 55fde47e58..dde97eb886 100644 --- a/board/atlas/gpio.inc +++ b/board/atlas/gpio.inc @@ -30,7 +30,7 @@ GPIO(RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* SOC Resume Reset */ GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) /* Power button to SOC */ GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* RTC Reset (broken) */ GPIO(EC_PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* PCH wake */ -GPIO(EC_PROCHOT_ODL, PIN(3, 4), GPIO_ODR_HIGH) /* SOC PROCHOT# */ +GPIO(EC_PROCHOT_ODL, PIN(3, 4), GPIO_INPUT) /* SOC PROCHOT# */ GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* SOC reset */ GPIO(USB_C0_DP_HPD, PIN(C, 5), GPIO_OUT_LOW) /* C0 Hotplug */ GPIO(USB_C1_DP_HPD, PIN(C, 6), GPIO_OUT_LOW) /* C1 Hotplug */ |