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author | Edward Hill <ecgh@chromium.org> | 2018-01-22 12:46:36 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-04 16:53:49 -0700 |
commit | 6b28dab8239564dd8024abf36b22dcb4b179c113 (patch) | |
tree | df804dc3b6f31b8962a1a9fa7bbd5b145609c7e9 /baseboard | |
parent | 571eb5939ef2f353cc16d725c3ce33100eab60ec (diff) | |
download | chrome-ec-6b28dab8239564dd8024abf36b22dcb4b179c113.tar.gz |
Add CONFIG_GPIO_INIT_POWER_ON_DELAY_MS
On power on, H1 releases the EC from reset but then quickly asserts and
releases the reset a second time (so that the EC comes out of reset the
second time after the SPI buffers have been configured by H1).
Add a delay so the EC can wait for this second reset before configuring
GPIO outputs, to avoid extra output toggles.
Unfortunate the timer is not set up by the time gpio_pre_init() is called,
so we add a new __hw_early_init_hwtimer() function to set it up so that
mdelay() worked. Without that, mdelay() hangs.
BUG=b:72132384
BRANCH=none
TEST=GPIO_OUT_HIGH has a single rising edge after power on
(before it would rise-fall-rise)
Check that mdelay(10) delays for about 10ms (actually perhaps a little
more using a scope line on KB_BL_EN
Change-Id: Iadc96fceb190e43ac0758f291f22e03aef81c379
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/879353
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'baseboard')
-rw-r--r-- | baseboard/grunt/baseboard.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h index fcc5f60371..b47befb418 100644 --- a/baseboard/grunt/baseboard.h +++ b/baseboard/grunt/baseboard.h @@ -88,6 +88,15 @@ #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 +/* + * On power-on, H1 releases the EC from reset but then quickly asserts and + * releases the reset a second time. This means the EC sees 2 resets: + * (1) power-on reset, (2) reset-pin reset. If we add a delay between reset (1) + * and configuring GPIO output levels, then reset (2) will happen before the + * end of the delay so we avoid extra output toggles. + */ +#define CONFIG_GPIO_INIT_POWER_ON_DELAY_MS 100 + #define CONFIG_KEYBOARD_BOARD_CONFIG #define CONFIG_KEYBOARD_COL2_INVERTED #define CONFIG_KEYBOARD_PROTOCOL_8042 |