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| author | Zhuohao Lee <zhuohao@chromium.org> | 2022-04-22 10:51:13 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-04-22 18:56:20 +0000 |
| commit | c46179983817ce526da5ef59ab20af047feccbb5 (patch) | |
| tree | bc539e41fbd12749d49de337810457c9518c5cf4 /baseboard/brya | |
| parent | 019b4aa1a8636f1347c3d7605f24c5aab5f17c37 (diff) | |
| download | chrome-ec-c46179983817ce526da5ef59ab20af047feccbb5.tar.gz | |
brya: add CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
When we use C2D2 to program the AP firmware, we need to enable the
EN_S5_RAILS. However, the power sequence ic will deassert the
SEQ_EC_RSMRST_ODL and the EC will bypass the RSMRST to the PCH and
make the AP starting to run. To avoid the spi bus contention with the
C2D2 during ap spi flash, we add CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
to avoid the RSMRST be passed to the PCH before the S5.
BUG=b:223084533, b:226438219
BRANCH=None
TEST=1. use C2D2 to flash the ap firmware
2. use CCD to flash the ap firmware
Change-Id: I83ba9b8ff06d5f9d32dea07a2575969e3a4d425d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3595412
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'baseboard/brya')
| -rw-r--r-- | baseboard/brya/baseboard.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h index a46b4dba45..31f987ab87 100644 --- a/baseboard/brya/baseboard.h +++ b/baseboard/brya/baseboard.h @@ -99,6 +99,7 @@ /* Chipset config */ #define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 +#define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_CPU_PROCHOT_ACTIVE_LOW |