cr50: add ability to include two identical RW sections in the EC image

A typical EC image includes two similar in their functionality
subsections, RO and RW. CR50 has a small RO subsection, all it does -
detects a proper RW image to run and starts it up. To provide for
reliable firmware updates, the CR50 image needs to include two RW
sections, while the code is running from one RW subsection, the other
one can be upgraded.

This patch adds the ability to generate two identical RW sections,
mapped half flash size apart, and include them into the resulting EC
image.

To keep things simple the previously existing RW section's name is not
being changed, while the new (identical) RW section is named RW_B.

Two configuration options need to be defined to enable building of the
new image type: CONFIG_RW_B to enable the feature and
CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the
flash.

A new rule added to Makefile.rules allows to generate a different lds
file from the same source (core/cortex-m/ec.lds.S) by defining a
compile time variable to pick a different base address for the
rewritable section, when RW_B is built.

BRANCH=none
BUG=chromium:43025
TEST=as follows:
    - make buildall -j still succeeds
    - verified that regular CR50 image starts successfully

    - modified chip/g/loader/main.c to launch RW_B first, re-built and
      re-run the image, observed on the console:

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
  cr50 bootloader, 20151118_11218@80881, no USB, full crypto
  Valid image found at 0x00084000, jumping

  --- UART initialized after reboot ---
  [Reset cause: power-on]
  [Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com]
  [0.001148 Inits done]
  This FPGA image has no USB support
  Console is enabled; type HELP for help.
  > [0.002212 task 2 waiting for events...]
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

    (note that the image base address is 0x840000, which is RW_B).

Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316703
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/Makefile.rules b/Makefile.rules
index 425a5e84ef..1f776303ff 100644
--- a/Makefile.rules
+++ b/Makefile.rules
@@ -33,6 +33,7 @@ silent_err = $(if $(V),,2>/dev/null)
 
 # commands to build all targets
 cmd_lds = $(CPP) -P -C -MMD -MF $@.d -MT $@ $(CPPFLAGS) $< -o $@
+cmd_lds_b = $(cmd_lds) -DRW_B_LDS
 # Allow obj_to_bin to be overridden by board or chip specific commands
 cmd_obj_to_bin ?= $(OBJCOPY) --gap-fill=0xff -O binary $^ $(out)/$*.bin.tmp
 cmd_flat_to_obj = $(CC) -T $(out)/firmware_image.lds -nostdlib $(CPPFLAGS) \
@@ -186,6 +187,9 @@ $(out)/firmware_image.lds: common/firmware_image.lds.S
 $(out)/%.lds: core/$(CORE)/ec.lds.S
 	$(call quiet,lds,LDS    )
 
+$(out)/%_B.lds: core/$(CORE)/ec.lds.S
+	$(call quiet,lds_b,LDS_B  )
+
 $(out)/%.bin: $(out)/%.obj
 	$(call quiet,obj_to_bin,OBJCOPY)
 	$(if $(wildcard $(PEM)),$(call quiet,rsasign,SIGN   ),)