cheza: Change GPIO for the rev-1 board

Reflect the chanages on the rev-1 board.

BRANCH=none
BUG=b:79548010
TEST=Verified on the rev-1 board, power-on and off, USB boot to kernel.

Change-Id: I933ff8dc171954dd6c44e0031016b300f15aa24e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1080995
Reviewed-by: Alexandru M Stan <amstan@chromium.org>

2 files changed, 22 insertions, 17 deletions

diff --git a/board/cheza/gpio.inc b/board/cheza/gpio.inc
index 6dae084476..64048cc13a 100644
--- a/board/cheza/gpio.inc
+++ b/board/cheza/gpio.inc
@@ -20,11 +20,7 @@ GPIO_INT(USB_C0_CABLE_DET,     PIN(3, 7), GPIO_INT_RISING, anx74xx_cable_det_int
 GPIO_INT(ACCEL_GYRO_INT_L,     PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
 
 /* System interrupts */
-/*
- * The ACOK_OD is also a PMIC power-on trigger, resulting some side-efforts.
- * Check the bug (b/78035750) for details. The next hardware rev will fix it.
- */
-GPIO_INT(AC_PRESENT,        PIN(0, 0), GPIO_INT_BOTH | GPIO_PULL_UP, extpower_interrupt) /* ACOK_OD */
+GPIO_INT(AC_PRESENT,        PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt) /* ACOK_OD */
 GPIO_INT(POWER_BUTTON_L,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* EC_PWR_BTN_ODL */
 GPIO_INT(VOLUME_DOWN_L,     PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* EC_VOLDN_BTN_ODL */
 GPIO_INT(VOLUME_UP_L,       PIN(1, 1), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* EC_VOLUP_BTN_ODL */
@@ -33,22 +29,28 @@ GPIO_INT(LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* LID_OPE
 GPIO_INT(AP_RST_REQ,        PIN(C, 2), GPIO_INT_RISING | GPIO_PULL_DOWN, chipset_reset_request_interrupt)  /* Reset request from AP */
 /* AP_RST_L is used for PMIC and AP negotiation. Don't change its state. */
 GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH, chipset_power_signal_interrupt)
-GPIO_INT(SHI_CS_L,          PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)
+GPIO_INT(SHI_CS_L,          PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* AP_EC_SPI_CS_L */
 
 GPIO(EC_SELF_RST,           PIN(E, 0), GPIO_OUT_LOW)   /* Self-reset EC */
-GPIO(SYS_RST_L,             PIN(0, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* Wake source: EC reset */
+GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
+GPIO(WARM_RESET_L,          PIN(F, 4), GPIO_ODR_HIGH)  /* AP warm reset */
 /* PS_HOLD is used for PMIC and AP negotiation. Don't change its state. */
 GPIO(PS_HOLD,               PIN(D, 4), GPIO_INPUT)     /* Indicate when AP triggers reset/shutdown */
 GPIO(ENTERING_RW,           PIN(E, 1), GPIO_OUT_LOW)   /* EC_ENTERING_RW: Indicate when EC is entering RW code */
 GPIO(CCD_MODE_ODL,          PIN(E, 3), GPIO_INPUT)     /* Case Closed Debug Mode */
 GPIO(BATT_PRES_ODL,         PIN(E, 5), GPIO_INPUT)     /* EC_BATT_PRES_ODL: Battery Present */
 GPIO(PMIC_FAULT_L,          PIN(7, 6), GPIO_INPUT)     /* Any PMIC fault? */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_OUT_HIGH)  /* TP10, rework jumps to PMIC power button */
+GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
 GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
+GPIO(POWER_GOOD,            PIN(5, 4), GPIO_INPUT)     /* SRC_PP1800_S4A from PMIC */
+GPIO(AP_SUSPEND_L,          PIN(5, 7), GPIO_INPUT)     /* Suspend signal from AP */
+GPIO(PROCHOT_L,             PIN(3, 4), GPIO_INPUT)
 
 /* Power enables */
-GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_OUT_HIGH)  /* Enable switch cap. XXX: It's active-high */
-GPIO(VBOB_EN,               PIN(9, 5), GPIO_OUT_HIGH)  /* Enable VBOB */
+GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap. XXX: It's active-high */
+GPIO(VBOB_EN,               PIN(9, 5), GPIO_OUT_LOW)   /* Enable VBOB */
+/* TODO(b/110988793): Default it to LOW and make it a S3 rail once the bug is fixed. */
 GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_HIGH)  /* Enable PP3300 */
 GPIO(EN_PP5000,             PIN(6, 7), GPIO_OUT_LOW)   /* EN_PP5000_A: Enable PP5000 */
 GPIO(BL_DISABLE_L,          PIN(2, 6), GPIO_OUT_HIGH)  /* EC_BL_DISABLE_L: Backlight disable signal from EC */
@@ -63,6 +65,8 @@ GPIO(EN_PPVAR_VAR_BASE,     PIN(1, 2), GPIO_OUT_LOW)   /* Power to the base */
 GPIO(EN_CC_LID_BASE_PH,     PIN(0, 7), GPIO_ODR_HIGH)
 GPIO(EN_CC_LID_BASE_PULLDN, PIN(1, 5), GPIO_ODR_HIGH)
 GPIO(REVERSE_DOCK_EC,       PIN(C, 6), GPIO_INPUT)     /* Indicate if the dock is reversed */
+GPIO(CC_LID_RX_BASE_TX,     PIN(7, 5), GPIO_INPUT)
+GPIO(CC_LID_RX_BASE_RX,     PIN(8, 6), GPIO_INPUT)
 
 /* LEDs */
 GPIO(CHG_LED_Y_C0,          PIN(C, 3), GPIO_OUT_LOW)   /* EC_CHG_LED_Y_C0 */
@@ -90,7 +94,7 @@ GPIO(CHG_LED_W_C1,          PIN(3, 0), GPIO_OUT_LOW)   /* EC_CHG_LED_W_C1 */
 GPIO(USB_C0_HS_MUX_OE_L,    PIN(A, 4), GPIO_OUT_LOW)
 GPIO(USB_C0_HS_MUX_SEL,     PIN(A, 3), GPIO_OUT_HIGH)  /* L:D1(AP), H:D2(hub) */
 GPIO(USB_C1_HS_MUX_OE_L,    PIN(7, 3), GPIO_OUT_LOW)
-GPIO(USB_C1_HS_MUX_SEL,     PIN(B, 7), GPIO_OUT_LOW)   /* L:D1(hub), H:D2(AP) */
+GPIO(USB_C1_HS_MUX_SEL,     PIN(7, 4), GPIO_OUT_LOW)   /* L:D1(hub), H:D2(AP) */
 
 /* USB-C port-0 controls */
 GPIO(USB_C0_PD_RST_R_L,     PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
@@ -100,7 +104,8 @@ GPIO(EN_USB_C0_TCPC_PWR,    PIN(6, 0), GPIO_OUT_LOW)   /* Port-0 TCPC power enab
 GPIO(USB_C1_PD_RST_ODL,     PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset */
 GPIO(EN_USB_C1_5V_OUT,      PIN(C, 0), GPIO_OUT_LOW)   /* Port-1 power switch 5V output */
 GPIO(EN_USB_C1_3A,          PIN(5, 6), GPIO_OUT_LOW)   /* Port-1 power switch 3A current */
-GPIO(EN_USB_C1_CHARGE_EC_L, PIN(B, 1), GPIO_OUT_LOW) /* Port-1 enable charging */
+GPIO(EN_USB_C1_CHARGE_EC_L, PIN(B, 1), GPIO_OUT_LOW)   /* Port-1 enable charging */
+GPIO(USBC_MUX_CONF1,        PIN(5, 1), GPIO_OUT_HIGH)  /* Port-1 enable DP switch */
 
 /* USB-C port-1 interrupts */
 GPIO(USB_C1_DP_HPD,         PIN(9, 6), GPIO_INPUT)     /* DP HPD from port-1 TCPC */
diff --git a/power/sdm845.c b/power/sdm845.c
index 350e940504..08b2539ccf 100644
--- a/power/sdm845.c
+++ b/power/sdm845.c
@@ -305,16 +305,16 @@ static void set_pmic_pwron(int enable)
 	 * 5. Release PMIC_KPD_PWR_ODL
 	 *
 	 * Power-off sequence:
-	 * 1. Hold down PMIC_KPD_PWR_ODL and SYS_RST_L, which is a power-off
+	 * 1. Hold down PMIC_KPD_PWR_ODL and PM845_RESIN_L, which is a power-off
 	 *    trigger (requiring reprogramming PMIC registers to make
-	 *    PMIC_KPD_PWR_ODL + SYS_RST_L as a shutdown trigger)
+	 *    PMIC_KPD_PWR_ODL + PM845_RESIN_L as a shutdown trigger)
 	 * 2. PM845 pulls down AP_RST_L signal to power-off SDM845 (requreing
 	 *    reprogramming PMIC to set the stage-1 and stage-2 reset timers to
 	 *    0 such that the pull down happens just after the deboucing time
 	 *    of the trigger, like 2ms)
 	 * 3. SDM845 pulls down PS_HOLD signal
 	 * 4. Wait for PS_HOLD down
-	 * 5. Release PMIC_KPD_PWR_ODL and SYS_RST_L
+	 * 5. Release PMIC_KPD_PWR_ODL and PM845_RESIN_L
 	 *
 	 * If the above PMIC registers not programmed or programmed wrong, it
 	 * falls back to the next functions, which cuts off the system power.
@@ -322,11 +322,11 @@ static void set_pmic_pwron(int enable)
 
 	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 0);
 	if (!enable)
-		gpio_set_level(GPIO_SYS_RST_L, 0);
+		gpio_set_level(GPIO_PM845_RESIN_L, 0);
 	wait_pmic_pwron(enable);
 	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 1);
 	if (!enable)
-		gpio_set_level(GPIO_SYS_RST_L, 1);
+		gpio_set_level(GPIO_PM845_RESIN_L, 1);
 }
 
 enum power_state power_chipset_init(void)