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| author | Dino Li <Dino.Li@ite.com.tw> | 2018-09-05 13:41:38 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-10 01:13:28 -0700 |
| commit | 68d10c79fb7ce9ff5ce58147465dab56b3e43233 (patch) | |
| tree | 8dfac5dd04863ef1a094f4354c6f5ef1ccddd996 | |
| parent | a426c81612527354a14f45c9a43d9bd1f7fa8d0e (diff) | |
| download | chrome-ec-68d10c79fb7ce9ff5ce58147465dab56b3e43233.tar.gz | |
it83xx/fpu: restore ALU at the beginning of exception handler
This change prevents CPU might execute a arithmetic instruction before
ALU is restored in the exception handler (Apply to floating point
division by zero).
We also make the change to use GP register to set system DLMB register,
so we can save R4 properly and print the correct panic information.
BUG=b:112452221
BRANCH=none
TEST=get a panic information if we do a floating point division
and divide by zero.
Change-Id: I20cb20500569c004af0336d1358ab0dd4b9452b9
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1201641
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | core/nds32/init.S | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/core/nds32/init.S b/core/nds32/init.S index 6c8f9e2055..b96ed44bb8 100644 --- a/core/nds32/init.S +++ b/core/nds32/init.S @@ -208,25 +208,25 @@ unhandled_irq: .global excep_handler excep_handler: - /* safety: reload GP even though it should be already set */ - la $gp, _SDA_BASE_ - /* save r0 to free one register */ - swi.gp $r0, [ + saved_regs] - /* save the remaining 15 registers */ - la $r0, saved_regs + 4 - smw.bim $r1, [$r0], $r10, 0 - smw.bim $r15,[$r0], $r15, 0xF #ifdef CONFIG_FPU /* * We have to restore ALU so that we can continue the next * sequence if arithmetic instructions are used. * (Apply to floating point division by zero) */ - sethi $r4, 0x80 - ori $r4, $r4,0x9 - mtsr $r4, $dlmb + sethi $gp, 0x80 + ori $gp, $gp,0x9 + mtsr $gp, $dlmb dsb #endif + /* safety: reload GP even though it should be already set */ + la $gp, _SDA_BASE_ + /* save r0 to free one register */ + swi.gp $r0, [ + saved_regs] + /* save the remaining 15 registers */ + la $r0, saved_regs + 4 + smw.bim $r1, [$r0], $r10, 0 + smw.bim $r15,[$r0], $r15, 0xF /* put a sane stack pointer */ la $sp, stack_end /* add IPC, IPSW to the context */ |