diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-09-13 13:31:04 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-14 12:08:22 -0700 |
| commit | 1b78a4e99c0ab9642e708114e11c8d7ee10f148e (patch) | |
| tree | f4bee8d7b4bcf55d2fcbe994566327ceb2f87208 | |
| parent | a7666732094a81ffc322f52d8b29b0018e0367fb (diff) | |
| download | chrome-ec-1b78a4e99c0ab9642e708114e11c8d7ee10f148e.tar.gz | |
fleex: Enable PSL
This change enables PSL hibernate mode on fleex by:
1. Selecting CONFIG_HIBERNATE_PSL
2. Configure alternate mode on PSL pins
3. Configuring EC_RST_ODL for wake
BUG=b:115660922
BRANCH=None
TEST=make -j buildall
Change-Id: Ic0e31f7fd1cc18061a819a61a5d5a8badcaed2ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1225351
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | board/fleex/board.h | 3 | ||||
| -rw-r--r-- | board/fleex/gpio.inc | 20 |
2 files changed, 23 insertions, 0 deletions
diff --git a/board/fleex/board.h b/board/fleex/board.h index 8ccecb5f25..96cee33cff 100644 --- a/board/fleex/board.h +++ b/board/fleex/board.h @@ -16,6 +16,9 @@ /* Optional features */ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */ +/* Enable PSL hibernate mode. */ +#define CONFIG_HIBERNATE_PSL + /* EC console commands */ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO diff --git a/board/fleex/gpio.inc b/board/fleex/gpio.inc index 3b340a8a64..3073fc8e20 100644 --- a/board/fleex/gpio.inc +++ b/board/fleex/gpio.inc @@ -74,6 +74,20 @@ GPIO(EN_P3300_TRACKPAD_ODL, PIN(3, 3), GPIO_ODR_HIGH) GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT) /* + * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does + * not need to be an interrupt for normal EC operations. Thus, configure it as + * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL + * common code can configure PSL_IN correctly. + * + * Reason for choosing low-to-high edge for waking from hibernate is to avoid + * the double reset - one because of PSL_IN wake and other because of VCC1_RST + * being asserted. Also, it should be fine to have the EC in hibernate when H1 + * or servo wants to hold the EC in reset since VCC1 will be down and so entire + * EC logic (except PSL) as well as AP will be in reset. + */ +GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) + +/* * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is * normally driven by the PMIC. The EC can also drive this signal in the event * that the ambient or charger temperature sensors exceeds their thresholds. @@ -148,3 +162,9 @@ ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0) /* I2C4 */ ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 - 1.8V */ ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0) /* ADC0-1 */ ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* PWM3: KB_BL_PWM */ + +/* Power Switch Logic (PSL) inputs */ +ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0) /* GPIOD2 = LID_OPEN */ +ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0) /* GPIO00 = ACOK_OD, + GPIO01 = MECH_PWR_BTN_ODL + GPIO02 = EC_RST_ODL */ |