NPCX797WC: correct image size to avoid overflowing WP_RO

The -WC chip has half as much flash as the -WB but the same amount
of RAM, which causes the EC_RO section in the output FMAP to be larger
than the actual read-only section of flash because code RAM is not more
than twice the size of the on-chip flash, which is required because RO
also contains the bootloader header.

Update the definitions for this chip to generate a smaller image that
still fits in Flash after the RO header is added. Because this breaks
assumptions about used memory being equal to available memory, remove
the RAM size checks and reorganize the chip blocks to define code and
data memory in the same block to obviate any need for RAM size checks.

BUG=b:158052612
TEST=Verify flash map is not broken: dump_fmap -hh build/dalboz/ec.bin,
     where prior to this change it complains that sections overlap:
         0x00000000:0x0003f03f EC_RO
         0x00000040:0x0003f03f FR_MAIN
         0x00000184:0x000001a3 RO_FRID
         0x0002bf40:0x0002c09d FMAP
         0x00000000:0x0003ffff WP_RO
         0x00040000:0x0007efff EC_RW
         0x00040144:0x00040163 RW_FWID

     Flashing the new image to a Dalboz boots and jumps to RW correctly.
BRANCH=None

Change-Id: I2ac28a7f973c4ae715828687edaad5f0110a2950
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2230949
Reviewed-by: Andrew McRae <amcrae@chromium.org>

1 files changed, 39 insertions, 37 deletions

diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h
index 27d7920a3a..d3c6d4e367 100644
--- a/chip/npcx/config_chip-npcx7.h
+++ b/chip/npcx/config_chip-npcx7.h
@@ -64,48 +64,50 @@
 /* Memory mapping */
 #define NPCX_BTRAM_SIZE    0x800 /* 2KB data ram used by booter. */
 
-#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
-#define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-/* 62 KB data RAM + 2 KB BT RAM size */
-#define CONFIG_DATA_RAM_SIZE    0x00010000
-#elif defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
-/* 126 KB data RAM + 2 KB BT RAM size */
-#define CONFIG_DATA_RAM_SIZE    0x00020000
-#endif
-#define CONFIG_RAM_SIZE         (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
-/* no low power ram in npcx7 series */
+#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
 
-/* Use chip variant to specify the size and start address of program memory */
 #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
-/* 192KB RAM for FW code */
-#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-/* program memory base address for 192KB Code RAM (ie. 0x100C0000 - 192KB) */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#elif defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-/* 256KB RAM for FW code */
-#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
-/* program memory base address for 256KB Code RAM (ie. 0x100B0000 - 256KB) */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
+	/* 192KB RAM for FW code */
+#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
+	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
+#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
+#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
+	/* 62 KB data RAM + 2 KB BT RAM size */
+#	define CONFIG_DATA_RAM_SIZE    0x00010000
+#elif defined(CHIP_VARIANT_NPCX7M7WB)
+	/* 256KB RAM for FW code */
+#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
+	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
+#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
+#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
+	/* 126 KB data RAM + 2 KB BT RAM size */
+#	define CONFIG_DATA_RAM_SIZE    0x00020000
+#elif defined(CHIP_VARIANT_NPCX7M7WC)
+	/*
+	 * 256KB program RAM, but only 512K of Flash (vs 1M for the
+	 * -WB). After the boot header is added, a 256K image would be
+	 * too large to fit in either RO or RW sections of Flash (each
+	 * of which is half of it). Because other code assumes that
+	 * image size is a multiple of Flash erase granularity, we
+	 * sacrifice a whole sector.
+	 */
+#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000)
+	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
+#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
+#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
+	/* 126 KB data RAM + 2 KB BT RAM size */
+#	define CONFIG_DATA_RAM_SIZE    0x00020000
+
+	/* Override default NPCX_RAM_SIZE because we're excluding a block. */
+#	undef NPCX_RAM_SIZE
+#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \
+			      NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
 #else
-#error "Unsupported chip variant"
+#	error "Unsupported chip variant"
 #endif
 
-/* Total RAM size checking for npcx ec */
-#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
-#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
-/* 256KB RAM in NPCX7M6F/NPCX7M6FB/NPCX7M6FC/NPCX7M6G */
-#if (NPCX_RAM_SIZE != 0x40000)
-#error "Wrong memory mapping layout for NPCX7M6F"
-#endif
-#elif defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-/* 384KB RAM in NPCX7M7WB/NPCX7M7WC */
-#if (NPCX_RAM_SIZE != 0x60000)
-#error "Wrong memory mapping layout for NPCX7M7W"
-#endif
-#endif
+#define CONFIG_RAM_SIZE         (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
+/* no low power ram in npcx7 series */
 
 #endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */