diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2016-11-18 12:26:08 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2016-11-22 17:29:33 +0000 |
| commit | 9413b1a8811a0ab91a318ca86ba0d4969612c8f2 (patch) | |
| tree | cb17a0390632fd9728968dfa7690bd3d6786aaeb | |
| parent | 746285081e7ad0f57528d6453949d6651932f151 (diff) | |
| download | chrome-ec-9413b1a8811a0ab91a318ca86ba0d4969612c8f2.tar.gz | |
npcx: hwtimer: Add consecutive reading for ITCNT32
The mux for selecting source clock of ITIM will introduce a delay
and have a chance to make ITIM's source clock and core clock are
asynchronous. We need consecutive reading for ITCNT32 no matter source
clock is APB2 or 32k.
Modified sources:
1. hwtimer.c: Add consecutive reading for ITCNT32
BRANCH=none
BUG=chrome-os-partner:34346,chrome-os-partner:59240
TEST=No time stamp symptoms occur on wheatley for 30 hours.
Change-Id: I8b54e93b320e3ea74fc3d6ea13f0d178f9c449cd
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/413098
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | chip/npcx/hwtimer.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c index 366f1624f4..5dfdc52c98 100644 --- a/chip/npcx/hwtimer.c +++ b/chip/npcx/hwtimer.c @@ -123,11 +123,12 @@ uint32_t __hw_clock_event_get(void) /* Get current counter value of event timer */ uint16_t __hw_clock_event_count(void) { - uint16_t cnt; + uint16_t cnt, cnt2; + + cnt = NPCX_ITCNT16(ITIM_EVENT_NO); /* Wait for two consecutive equal values are read */ - do { - cnt = NPCX_ITCNT16(ITIM_EVENT_NO); - } while (cnt != NPCX_ITCNT16(ITIM_EVENT_NO)); + while ((cnt2 = NPCX_ITCNT16(ITIM_EVENT_NO)) != cnt) + cnt = cnt2; return cnt; } @@ -220,7 +221,16 @@ void hw_clock_source_set_preload(uint32_t ts, uint8_t clear) /* Returns the value of the free-running counter used as clock. */ uint32_t __hw_clock_source_read(void) { - uint32_t cnt = NPCX_ITCNT32; + uint32_t cnt, cnt2; + + cnt = NPCX_ITCNT32; + /* + * Wait for two consecutive equal values are read no matter + * ITIM's source clock is APB2 or 32K since mux's delay. + */ + while ((cnt2 = NPCX_ITCNT32) != cnt) + cnt = cnt2; + #if DEBUG_TMR cur_cnt_us_dbg = TICK_ITIM32_MAX_CNT - cnt; #endif |