coil: CONFIG_SPS->CONFIG_SPP

BUG=b:175244613
TEST=make buildall -j

Change-Id: I79a65f8475e2a764720a1f37a147c3723d34b046
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615120
Reviewed-by: Namyoon Woo <namyoon@chromium.org>

6 files changed, 12 insertions, 12 deletions

diff --git a/board/cr50/board.h b/board/cr50/board.h
index 6817751699..6e139526b4 100644
--- a/board/cr50/board.h
+++ b/board/cr50/board.h
@@ -140,8 +140,8 @@
 #define CONFIG_SPI_MASTER_CONFIGURE_GPIOS
 #define CONFIG_SPI_FLASH_PORT 0
 
-/* Enable SPI Slave (SPS) module */
-#define CONFIG_SPS
+/* Enable SPI peripheral (SPP) module */
+#define CONFIG_SPP
 #define CONFIG_TPM_SPS
 
 #define CONFIG_RBOX
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc
index 3c01e4199e..c9791dffc7 100644
--- a/board/cr50/gpio.inc
+++ b/board/cr50/gpio.inc
@@ -303,7 +303,7 @@ PINMUX(GPIO(DETECT_SERVO),      B5, DIO_INPUT)
 /*
  * Both SPI master and slave buses are wired directly to specific pads
  *
- * If CONFIG_SPS is defined, these pads are used:
+ * If CONFIG_SPP is defined, these pads are used:
  *   DIOA2  = SPS_MOSI  (input)
  *   DIOA6  = SPS_CLK   (input)
  *   DIOA10 = SPS_MISO  (output)
diff --git a/chip/g/build.mk b/chip/g/build.mk
index 99e35568ce..c52e51cab3 100644
--- a/chip/g/build.mk
+++ b/chip/g/build.mk
@@ -70,7 +70,7 @@ chip-$(CONFIG_CCD_ITE_PROGRAMMING)+= ite_sync.o
 chip-$(CONFIG_ENABLE_H1_ALERTS)+= alerts.o
 chip-$(CONFIG_USB_FW_UPDATE)+= usb_upgrade.o
 chip-$(CONFIG_NON_HC_FW_UPDATE)+= upgrade_fw.o post_reset.o upgrade.o
-chip-$(CONFIG_SPS)+= sps.o
+chip-$(CONFIG_SPP)+= sps.o
 chip-$(CONFIG_TPM_SPS)+=sps_tpm.o
 chip-$(CONFIG_WATCHDOG)+=watchdog.o
 
diff --git a/chip/g/sps.c b/chip/g/sps.c
index 78d3a01570..0e4888a946 100644
--- a/chip/g/sps.c
+++ b/chip/g/sps.c
@@ -457,7 +457,7 @@ void sps0_cs_assert_interrupt_(void)
 }
 DECLARE_IRQ(GC_IRQNUM_SPS0_CS_ASSERT_INTR, sps0_cs_assert_interrupt_, 1);
 
-#ifdef CONFIG_SPS_TEST
+#ifdef CONFIG_SPP_TEST
 
 /* Function to test SPS driver. It expects the host to send SPI frames of size
  * <size> (not exceeding 1100) of the following format:
@@ -613,4 +613,4 @@ static int command_sps(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(spstest, command_sps,
 			"<num of frames>",
 			"Loop back frames (10 by default) back to the host");
-#endif /* CONFIG_SPS_TEST */
+#endif /* CONFIG_SPP_TEST */
diff --git a/include/config.h b/include/config.h
index 259d533008..c335e757f8 100644
--- a/include/config.h
+++ b/include/config.h
@@ -3089,12 +3089,12 @@
 #undef CONFIG_SPI_PROTOCOL_V2
 
 /*
- * Support SPI Slave interfaces. The first board supporting this is cr50 and
- * in its parlance SPI_SLAVE is called SPS. This convention might be
+ * Support SPI periph interfaces. The first board supporting this is cr50 and
+ * in its parlance SPI_PERIPH is called SPP. This convention might be
  * reconsidered later, and the use of "SPI" in different config options needs
  * to be cleaned up. (crbug.com/512613).
  */
-#undef CONFIG_SPS
+#undef CONFIG_SPP
 
 /* Define the SPI port to use to access SPI accelerometer */
 #undef CONFIG_SPI_ACCEL_PORT
@@ -3168,8 +3168,8 @@
  * SPI master port's hardwired CS pin. */
 #undef CONFIG_SPI_MASTER_NO_CS_GPIOS
 
-/* Support testing SPI slave controller driver. */
-#undef CONFIG_SPS_TEST
+/* Support testing SPI periph interface driver. */
+#undef CONFIG_SPP_TEST
 
 /* Default stack size to use for tasks, in bytes */
 #undef CONFIG_STACK_SIZE
diff --git a/include/console_channel.inc b/include/console_channel.inc
index c7010907c0..e96c2fdba8 100644
--- a/include/console_channel.inc
+++ b/include/console_channel.inc
@@ -76,7 +76,7 @@ CONSOLE_CHANNEL(CC_SPI,          "spi")
 #ifdef CONFIG_RBOX
 CONSOLE_CHANNEL(CC_RBOX,         "rbox")
 #endif
-#ifdef CONFIG_SPS
+#ifdef CONFIG_SPP
 CONSOLE_CHANNEL(CC_SPS,          "sps")
 #endif
 #if defined(CONFIG_SWITCH) || defined(CONFIG_LID_SWITCH)