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| author | Caveh Jalali <caveh@chromium.org> | 2018-06-11 17:35:15 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-18 13:54:52 -0700 |
| commit | a0a3066e9073513c7fc9be496cb99ea3f8bafca1 (patch) | |
| tree | 5202acad95421ec5024e5324b157e873a8eba4d6 | |
| parent | bca6aa066bde16330bf4934c132f711109702dd0 (diff) | |
| download | chrome-ec-a0a3066e9073513c7fc9be496cb99ea3f8bafca1.tar.gz | |
bd99992: add top level header file for PMIC
this introduces a top-level header file for the bd99992 PMIC.the temp
sensor portion of this chip already has an established header file, so
we can just include it.
at this point, we only need one new register definition - the SDWNCTRL
(shutdown control) register.
BUG=b:110237370
BRANCH=none
TEST=it compiles
Change-Id: I324df08ed37d6d6d85520e1217135657b18a23a0
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096484
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
| -rw-r--r-- | driver/pmic_bd99992gw.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h new file mode 100644 index 0000000000..4a40a2b15b --- /dev/null +++ b/driver/pmic_bd99992gw.h @@ -0,0 +1,16 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * ROHM BD99992GW PMIC register map. + */ + +#ifndef __CROS_EC_PMIC_BD99992GW_H +#define __CROS_EC_PMIC_BD99992GW_H + +#include "temp_sensor/bd99992gw.h" + +#define BD99992GW_REG_SDWNCTRL 0x49 +#define BD99992GW_SDWNCTRL_SWDN (1 << 0) /* SWDN mask */ + +#endif /* __CROS_EC_PMIC_BD99992GW_H */ |