diff options
| author | Caveh Jalali <caveh@chromium.org> | 2018-06-19 15:38:38 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-20 14:23:47 -0700 |
| commit | 7fdaa393dfd0b4da381f62ee50e4b1c056d6eda4 (patch) | |
| tree | 3164333c669deec42185533d99a54149d731de1b | |
| parent | 7711af5291b755cc55f38723b8fe4ae62fc211d1 (diff) | |
| download | chrome-ec-7fdaa393dfd0b4da381f62ee50e4b1c056d6eda4.tar.gz | |
atlas: config CPU_PROCHOT polarity
atlas's CPU_PROCHOT signal is active low which is inverted compared
with previous designs. we recently added support for configuring
PROCHOT polarity, so we can now configure this pin correctly.
BUG=b:79266467
BRANCH=none
TEST=prochot pin reads back correctly on EC and CPU is not throttled.
explicitly asserting PROCHOT gpio on EC throttles CPU.
Change-Id: Ie44352855d36f43f5767a99684dd17a509826190
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1107121
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
| -rw-r--r-- | board/atlas/board.h | 1 | ||||
| -rw-r--r-- | board/atlas/gpio.inc | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/board/atlas/board.h b/board/atlas/board.h index 13782dfb49..ae290ca666 100644 --- a/board/atlas/board.h +++ b/board/atlas/board.h @@ -60,6 +60,7 @@ #define CONFIG_CHIPSET_SKYLAKE #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET #define CONFIG_CHIPSET_RESET_HOOK +#define CONFIG_CPU_PROCHOT_ACTIVE_LOW #define CONFIG_HOSTCMD_ESPI #define CONFIG_HOSTCMD_ESPI_VW_SIGNALS #define CONFIG_KEYBOARD_BOARD_CONFIG diff --git a/board/atlas/gpio.inc b/board/atlas/gpio.inc index 8d3c665fac..aa21ee5fa9 100644 --- a/board/atlas/gpio.inc +++ b/board/atlas/gpio.inc @@ -30,7 +30,7 @@ GPIO(RSMRST_L, PIN(3, 7), GPIO_OUT_LOW) /* SOC Resume Reset */ GPIO(EC_PCH_PWR_BTN_L, PIN(C, 1), GPIO_OUT_HIGH) /* Power button to SOC */ GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* RTC Reset (broken) */ GPIO(EC_PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* PCH wake */ -GPIO(EC_PROCHOT_ODL, PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* SOC PROCHOT# */ +GPIO(EC_PROCHOT_ODL, PIN(3, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* SOC PROCHOT# */ GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* SOC reset */ GPIO(USB_C0_DP_HPD, PIN(C, 5), GPIO_INPUT) /* C0 Hotplug Detect */ GPIO(USB_C1_DP_HPD, PIN(C, 6), GPIO_INPUT) /* C1 Hotplug Detect */ |