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| author | Furquan Shaikh <furquan@chromium.org> | 2017-07-17 23:06:44 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-07-18 19:39:06 -0700 |
| commit | 592805e75fc742709c7db82020f3b3e38b30f314 (patch) | |
| tree | a97a3744b9c3ce1622b2dc28821abaea85881b10 | |
| parent | 6a23fc7244025b2c079f583282759195bdeb13ad (diff) | |
| download | chrome-ec-592805e75fc742709c7db82020f3b3e38b30f314.tar.gz | |
poppy: Keep power to base enabled in deep S3
In deep S3, SLP_SUS# goes low which results in power to base being
cut. For such cases, PMIC needs to be configured so that it keeps the
power to base up. Use VREN register to keep PP5000_A rail enabled in
deep S3.
BUG=b:63251418
BRANCH=None
TEST=make -j buildall. Verified that wake from base works in deep S3.
Change-Id: Ice3ba56f1a7e52275c3afa332c29b5b252dded4d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/574619
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
| -rw-r--r-- | board/poppy/board.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/board/poppy/board.c b/board/poppy/board.c index 1b909fde89..412944dd0c 100644 --- a/board/poppy/board.c +++ b/board/poppy/board.c @@ -930,6 +930,33 @@ static void board_chipset_suspend(void) } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); +static void board_chipset_startup(void) +{ + /* + * Enable V5A in deep sleep state: + * VREN (bit 0) : EC_DS4 enable + * - Enables V5A voltage regulator in deep Sx states + * V5ADS3CNT (bits 1:0) : AUTO + * - Control to the VR (0 = off, 1 = PFM, 2 = AUTO, 3 = Forced PWM) + */ + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x41, 0x01); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x2a, 0x02); +} +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); + +static void board_chipset_shutdown(void) +{ + /* + * V5A VREN needs to be reset when chipset is shutdown. This is required + * because VREN keeps the V5A powered in all deep Sx states including + * deep S5. There is no need to power this rail in deep S5 as wake from + * base is not required. + */ + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x41, 0x0); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x2a, 0x0); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); + int board_has_working_reset_flags(void) { int version = system_get_board_version(); |