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| author | Nicolas Boichat <drinkcat@google.com> | 2017-07-06 14:43:16 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-07-06 05:00:28 -0700 |
| commit | c869b0f15c8d73f97cba4a6b2d3e0715a8a3c367 (patch) | |
| tree | 8abc0bdddaf4e02d2d3b4654637c15873daa6855 | |
| parent | d33618ce9f9a6b95632d0de3ebed1eca196cd982 (diff) | |
| download | chrome-ec-c869b0f15c8d73f97cba4a6b2d3e0715a8a3c367.tar.gz | |
chip/stm32/registers.h: Fix STM32_FLASH_OPT_LOCKED polarity
We currently set STM32_FLASH_OPT_LOCKED
to (STM32_FLASH_CR & FLASH_CR_OPTWRE), however the bit is set
when option byte are _unlocked_.
From STM32F0 Reference Manual:
Bit 9 OPTWRE: Option byte write enable
When set, the option byte can be programmed. This bit is set
on writing the correct key sequence to the FLASH_OPTKEYR register.
This bit can be reset by software
BRANCH=none
BUG=chromium:739608
TEST=Flash hammer, flashwp true; reboot; flashinfo
=> hammer does not hang on reboot, RO is protected
Change-Id: I1b6eb5d638534ece90d6d5164586f49bdb0c151d
Reviewed-on: https://chromium-review.googlesource.com/561036
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 7be2059486..b8035620f0 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1347,7 +1347,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define FLASH_CR_LOCK (1 << 7) #define FLASH_CR_OPTWRE (1 << 9) #define FLASH_CR_OBL_LAUNCH (1 << 13) -#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_CR & FLASH_CR_OPTWRE) +#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) #define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) #define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) #define STM32_FLASH_OBR_RDP_MASK (3 << 1) |