eve_fp: setup SPI slave communication on STM32L442

Enable properly the SPI slave command interface to drive the FP MCU from
the main CPU using the EC SPI protocol V3.

Fix the SPI slave driver on STM32L4 along the way:
- the STM32L4 family has the same FIFOs as STM32F0
- on STM32L4, we need to map the DMA requests
- set explicitly the data size (rather than setting an invalid value
  which defaults to 8-bit).

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=b:36025702
TEST=On Eve, use the kernel cros_ec_spi driver to communicate with the
FPMCU using the Cros EC SPI protocol V3.

Change-Id: Ib641c141808aa60b3a74611319e18e7a6c3736f0
Reviewed-on: https://chromium-review.googlesource.com/452373
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>

4 files changed, 17 insertions, 7 deletions

diff --git a/board/eve_fp/board.c b/board/eve_fp/board.c
index a84826833d..5846f304ee 100644
--- a/board/eve_fp/board.c
+++ b/board/eve_fp/board.c
@@ -36,5 +36,8 @@ static void board_init(void)
 	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00000fc0;
 	/* Enable clocks to SPI3 module (master) */
 	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI3;
+
+	/* we are ready for host transactions */
+	hook_notify(HOOK_CHIPSET_RESUME);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/eve_fp/board.h b/board/eve_fp/board.h
index 454b4e7f93..b8a9e1c51a 100644
--- a/board/eve_fp/board.h
+++ b/board/eve_fp/board.h
@@ -24,6 +24,7 @@
 
 /* Optional features */
 #define CONFIG_CMD_SPI_XFER
+#define CONFIG_HOST_COMMAND_STATUS
 #undef  CONFIG_LID_SWITCH
 #define CONFIG_SPI
 #define CONFIG_SPI_MASTER
diff --git a/board/eve_fp/gpio.inc b/board/eve_fp/gpio.inc
index 9ab359479e..ee8da2a179 100644
--- a/board/eve_fp/gpio.inc
+++ b/board/eve_fp/gpio.inc
@@ -20,7 +20,7 @@ UNIMPLEMENTED(WP_L)
 
 /* USART1: PA9/10 */
 ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_F7, MODULE_UART, 0)
-/* SPI1 slave from PCH: PA5/6/7 */
-ALTERNATE(PIN_MASK(A, 0x00e0), GPIO_ALT_F5, MODULE_SPI,  0)
+/* SPI1 slave from PCH: PA4/5/6/7 */
+ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_F5, MODULE_SPI,  0)
 /* SPI3 master to sensor: PB3/4/5 */
 ALTERNATE(PIN_MASK(B, 0x0038), GPIO_ALT_F6, MODULE_SPI_MASTER,  0)
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index 032dd590a9..cdb1e0666b 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -17,6 +17,7 @@
 #include "host_command.h"
 #include "registers.h"
 #include "spi.h"
+#include "stm32-dma.h"
 #include "system.h"
 #include "timer.h"
 #include "util.h"
@@ -90,7 +91,7 @@ static const uint8_t out_preamble[4] = {
  *
  * See crbug.com/31390
  */
-#ifdef CHIP_FAMILY_STM32F0
+#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
 #define EC_SPI_PAST_END_LENGTH 4
 #else
 #define EC_SPI_PAST_END_LENGTH 1
@@ -271,7 +272,7 @@ static void tx_status(uint8_t byte)
 	stm32_spi_regs_t *spi = STM32_SPI1_REGS;
 
 	spi->dr = byte;
-#ifdef CHIP_FAMILY_STM32F0
+#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
 	/* It sends the byte 4 times in order to be sure it bypassed the FIFO
 	 * from the STM32F0 line.
 	 */
@@ -309,7 +310,7 @@ static void setup_for_transaction(void)
 	 * receive DMA from getting that byte right when we start it.
 	 */
 	dummy = spi->dr;
-#ifdef CHIP_FAMILY_STM32F0
+#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
 	/* 4 Bytes makes sure the RX FIFO on the F0 is empty as well. */
 	dummy = spi->dr;
 	dummy = spi->dr;
@@ -403,7 +404,7 @@ static void spi_send_response_packet(struct host_packet *pkt)
 
 	/* Append our past-end byte, which we reserved space for. */
 	((uint8_t *)pkt->response)[pkt->response_size + 0] = EC_SPI_PAST_END;
-#ifdef CHIP_FAMILY_STM32F0
+#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
 	/* Make sure we are going to be outputting it properly when the DMA
 	 * ends due to the TX FIFO bug on the F0. See crbug.com/31390
 	 */
@@ -644,12 +645,17 @@ static void spi_init(void)
 	/* Delay 1 APB clock cycle after the clock is enabled */
 	clock_wait_bus_cycles(BUS_APB, 1);
 
+	/* Select the right DMA request for the variants using it */
+#ifdef CHIP_FAMILY_STM32L4
+	dma_select_channel(STM32_DMAC_SPI1_TX, 1);
+	dma_select_channel(STM32_DMAC_SPI1_RX, 1);
+#endif
 	/*
 	 * Enable rx/tx DMA and get ready to receive our first transaction and
 	 * "disable" FIFO by setting event to happen after only 1 byte
 	 */
 	spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN |
-		STM32_SPI_CR2_FRXTH;
+		STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
 
 	/* Enable the SPI peripheral */
 	spi->cr1 |= STM32_SPI_CR1_SPE;