diff options
| author | Chris Chen <twothreecc@google.com> | 2016-08-08 17:30:19 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-08-09 12:43:21 -0700 |
| commit | 84697c60291e0e833af7be36d7752479824f5a84 (patch) | |
| tree | 6b79dffc3c0634d946ba1c4468c0aa566f05c482 | |
| parent | 40908f6f4fde6642637dc2b0269daf78d47b3844 (diff) | |
| download | chrome-ec-84697c60291e0e833af7be36d7752479824f5a84.tar.gz | |
stm32: Clarified a few comments in registers.h
BRANCH=None
BUG=None
TEST=None
Change-Id: I31bb65d89adb41cf3affd63e6ee9f73fbf11183a
Reviewed-on: https://chromium-review.googlesource.com/366887
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index f74de94e37..9007b45134 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -149,7 +149,7 @@ /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#endif /* CHIP_FAMILY_STM32F0 */ +#endif /* !CHIP_FAMILY_STM32F0 */ #ifndef __ASSEMBLER__ @@ -199,7 +199,8 @@ #define STM32_USART_SR_RXNE (1 << 5) #define STM32_USART_SR_TC (1 << 6) #define STM32_USART_SR_TXE (1 << 7) -#else /* !CHIP_FAMILY_STM32F0 */ +#else +/* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 && !CHIP_FAMILY_STM32L4 */ #define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) #define STM32_USART_SR_ORE (1 << 3) #define STM32_USART_SR_RXNE (1 << 5) @@ -224,7 +225,8 @@ /* register aliases */ #define STM32_USART_TDR(base) STM32_USART_DR(base) #define STM32_USART_RDR(base) STM32_USART_DR(base) -#endif /* !CHIP_FAMILY_STM32F0 */ +#endif +/* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 && !CHIP_FAMILY_STM32L4 */ #define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n) @@ -466,7 +468,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) #define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) #define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) -#else /* !CHIP_FAMILY_STM32F0 */ +#else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */ #define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) #define STM32_I2C_CR1_PE (1 << 0) #define STM32_I2C_CR1_START (1 << 8) @@ -493,7 +495,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) #define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) -#endif /* !CHIP_FAMILY_STM32F0 */ +#endif /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */ /* --- Power / Reset / Clocks --- */ #define STM32_PWR_BASE 0x40007000 |