diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-01-29 10:57:32 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-02-01 17:18:26 -0800 |
| commit | b7cf464b860839775412020541d8a09a8618210e (patch) | |
| tree | 4850fdf7d40e554216b13a48c3bfc237e172352b | |
| parent | 4f6f505900a0b8c2e16955b5eb69a9213fc6076d (diff) | |
| download | chrome-ec-b7cf464b860839775412020541d8a09a8618210e.tar.gz | |
chell: Enable S0ix power state support
Enable the config option for S0IX power control and set the GPIO to
use power_signal_interrupt_S0.
BUG=chrome-os-partner:49274
BRANCH=glados
TEST=echo freeze > /sys/power/state
Unfortunately currently SLP_S0_L is not asserting so this is difficult
to actually test the EC behavior
Change-Id: I302da7735c9622975e0386a0b4542f41c7231df9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324567
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | board/chell/board.h | 3 | ||||
| -rw-r--r-- | board/chell/gpio.inc | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/board/chell/board.h b/board/chell/board.h index cf6563d483..830b38c560 100644 --- a/board/chell/board.h +++ b/board/chell/board.h @@ -53,6 +53,7 @@ #define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_COMMON #define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30 +#define CONFIG_POWER_S0IX #define CONFIG_PWM #define CONFIG_PWM_KBLIGHT /* All data won't fit in data RAM. So, moving boundary slightly. */ @@ -132,7 +133,7 @@ #undef CONFIG_CONSOLE_CMDHELP #undef DEFERRABLE_MAX_COUNT -#define DEFERRABLE_MAX_COUNT 13 +#define DEFERRABLE_MAX_COUNT 14 #ifndef __ASSEMBLER__ diff --git a/board/chell/gpio.inc b/board/chell/gpio.inc index 6e31375851..5bb25820c5 100644 --- a/board/chell/gpio.inc +++ b/board/chell/gpio.inc @@ -14,7 +14,7 @@ GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt) GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(PCH_SLP_S0_L, PIN(211), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PCH_SLP_S0_L, PIN(211), GPIO_INT_BOTH, power_signal_interrupt_S0) GPIO_INT(PCH_SLP_SUS_L, PIN(12), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PMIC_INT_L, PIN(50), GPIO_INT_FALLING, power_signal_interrupt) GPIO_INT(PD_MCU_INT, PIN(122), GPIO_INT_FALLING | GPIO_PULL_UP, pd_mcu_interrupt) |