diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-18 14:43:17 -0500 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-19 08:10:09 +0000 |
| commit | eb1327ea0ccf839cb1391ef86b7c4a5b7c0491c6 (patch) | |
| tree | 855415af32593de28a8a72c35dcf670052d2113f | |
| parent | 4d382ad6401cbe178fa9c53309bdc8a460cf3413 (diff) | |
| download | chrome-ec-eb1327ea0ccf839cb1391ef86b7c4a5b7c0491c6.tar.gz | |
glados: don't pull up SLP_S0_L
The SLP_S0_L signal lives in the primary power well of skylake
while the EC's VCC is on the DSW rail. If SLP_S0_L is pulled up
then there is leakage into the primary well when it's not on.
BUG=chrome-os-partner:44098
BRANCH=None
TEST=Built and booted glados. Default powerindebug state shows SLP_S0_L
low when in deep sleep states.
Change-Id: If9c7972fb6a8b8f90738c1c0f7eea6cf2373d64b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293842
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
| -rw-r--r-- | board/glados/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/glados/gpio.inc b/board/glados/gpio.inc index 66873b68c7..66fa79072a 100644 --- a/board/glados/gpio.inc +++ b/board/glados/gpio.inc @@ -14,7 +14,7 @@ GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt) GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(PCH_SLP_S0_L, PIN(211), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) +GPIO_INT(PCH_SLP_S0_L, PIN(211), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt) GPIO_INT(PCH_SLP_SUS_L, PIN(12), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(VOLUME_UP_L, PIN(31), GPIO_INT_FALLING | GPIO_PULL_UP, button_interrupt) GPIO_INT(VOLUME_DOWN_L, PIN(47), GPIO_INT_FALLING | GPIO_PULL_UP, button_interrupt) |