diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-08-07 16:10:14 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-11 02:58:45 +0000 |
| commit | 1b53f74664ff638745745666059e56f43f5c4f14 (patch) | |
| tree | 4b85a48eafbe83e185f0498bf7bc546630fc886b | |
| parent | 953f4b75a974cb5ae074a68c1dd0d1bfc7e1593c (diff) | |
| download | chrome-ec-1b53f74664ff638745745666059e56f43f5c4f14.tar.gz | |
cr50: code modifications to support FPGA B1
The new FPGA version adds a lot of few features, while temporarily
cutting off some existing capabilities like clocking configuration
(hardwared clocks used instead), pinmux assignment for SPS interface
(hardwared connections used), etc.
This patch removes some now unused code, modifies some configuration
items and adds TODO_FGPA comment blocks highlighting code which needs
to be reviews next time FPGA version changes).
The new register definitions file is derived from hardware
description.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=with these changes in place the B1 board boots to the console
prompt.
Change-Id: I78ec6b2831a44cbfd40ee726a5d3c2cc11bf2cfa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291855
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
| -rw-r--r-- | board/cr50/gpio.inc | 5 | ||||
| -rw-r--r-- | chip/g/config_chip.h | 6 | ||||
| -rw-r--r-- | chip/g/cr50_fpga_regdefs.h | 14492 | ||||
| -rw-r--r-- | chip/g/gpio.c | 8 | ||||
| -rw-r--r-- | chip/g/pmu.c | 512 | ||||
| -rw-r--r-- | chip/g/sps.c | 6 | ||||
| -rw-r--r-- | chip/g/system.c | 16 | ||||
| -rw-r--r-- | chip/g/watchdog.c | 4 |
8 files changed, 10267 insertions, 4782 deletions
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc index 624221cc6b..3439393f68 100644 --- a/board/cr50/gpio.inc +++ b/board/cr50/gpio.inc @@ -64,9 +64,10 @@ ALTERNATE(PIN_MASK(LED_5, DIO(A12)), 0, MODULE_GPIO, DIO_INPUT) ALTERNATE(PIN_MASK(LED_6, DIO(A13)), 0, MODULE_GPIO, DIO_INPUT) ALTERNATE(PIN_MASK(LED_7, DIO(A14)), 0, MODULE_GPIO, DIO_INPUT) -/* SPS IOs */ +/* SPS IOs This is not needed for the FPGA, it is hardwired + * TODO_FPGA (might have to be modified for a new version) ALTERNATE(PIN_MASK(FUNC(SPS0_SPICLK), DIO(A2)), 0, MODULE_GPIO, DIO_INPUT) ALTERNATE(PIN_MASK(FUNC(SPS0_SPIMOSI), DIO(A3)), 0, MODULE_GPIO, DIO_INPUT) ALTERNATE(PIN_MASK(FUNC(SPS0_SPICSB), DIO(A4)), 0, MODULE_GPIO, DIO_INPUT) ALTERNATE(PIN_MASK(FUNC(SPS0_SPIMISO), DIO(A5)), 0, MODULE_GPIO, DIO_OUTPUT) - +*/ diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h index 7e5d792291..b886b5addf 100644 --- a/chip/g/config_chip.h +++ b/chip/g/config_chip.h @@ -9,7 +9,8 @@ #include "core/cortex-m/config_core.h" /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 108 +/* TODO_FPGA this should come from the generated .h file */ +#define CONFIG_IRQ_COUNT 188 /* Describe the RAM layout */ #define CONFIG_RAM_BASE 0x10000 @@ -53,4 +54,7 @@ #define GPIO_PIN(port, index) GPIO_##port, (1 << index) #define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) +/* TODO_FPGA this should come from the generated .h file */ +#define PCLK_FREQ (24 * 1000 * 1000) + #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/g/cr50_fpga_regdefs.h b/chip/g/cr50_fpga_regdefs.h index e6b3d4775c..48abe94489 100644 --- a/chip/g/cr50_fpga_regdefs.h +++ b/chip/g/cr50_fpga_regdefs.h @@ -1,50 +1,50 @@ /* - * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Copyright (c) 2015 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* This file is autogenerated. Do not edit. */ -#ifndef __CROS_EC_CR50_FPGA_REGDEFS_H -#define __CROS_EC_CR50_FPGA_REGDEFS_H +#ifndef __EC_CHIP_G_CR50_FPGA_REGDEFS_H +#define __EC_CHIP_G_CR50_FPGA_REGDEFS_H + #define GC___REVA__ 1 #define GC___REVB__ 2 #define GC___REVC__ 3 #define GC___REVD__ 4 #define GC___REVE__ 5 #define GC___HAVEN__ 1 -#define GC___MAJOR_REV__ __REVA__ +#define GC___MAJOR_REV__ __REVB__ #define GC___MINOR_REV__ 1 -#define GC_PINMUX_DIOA0_SEL 0x6 -#define GC_PINMUX_DIOA1_SEL 0x7 -#define GC_PINMUX_DIOA2_SEL 0x8 -#define GC_PINMUX_DIOA3_SEL 0x9 -#define GC_PINMUX_DIOA4_SEL 0xa -#define GC_PINMUX_DIOA5_SEL 0xb -#define GC_PINMUX_DIOA6_SEL 0xc -#define GC_PINMUX_DIOA7_SEL 0xd -#define GC_PINMUX_DIOA8_SEL 0xe -#define GC_PINMUX_DIOA9_SEL 0xf -#define GC_PINMUX_DIOA10_SEL 0x10 -#define GC_PINMUX_DIOA11_SEL 0x11 -#define GC_PINMUX_DIOA12_SEL 0x12 -#define GC_PINMUX_DIOA13_SEL 0x13 -#define GC_PINMUX_DIOA14_SEL 0x14 -#define GC_PINMUX_DIOB0_SEL 0x15 -#define GC_PINMUX_DIOB1_SEL 0x16 -#define GC_PINMUX_DIOB2_SEL 0x17 -#define GC_PINMUX_DIOB3_SEL 0x18 -#define GC_PINMUX_DIOB4_SEL 0x19 -#define GC_PINMUX_DIOB5_SEL 0x1a -#define GC_PINMUX_DIOB6_SEL 0x1b -#define GC_PINMUX_DIOB7_SEL 0x1c -#define GC_PINMUX_DIOB8_SEL 0x1d -#define GC_PINMUX_DIOM0_SEL 0x1 -#define GC_PINMUX_DIOM1_SEL 0x2 -#define GC_PINMUX_DIOM2_SEL 0x3 -#define GC_PINMUX_DIOM3_SEL 0x4 -#define GC_PINMUX_DIOM4_SEL 0x5 +#define GC_PINMUX_DIOA0_SEL 0x1b +#define GC_PINMUX_DIOA1_SEL 0x1a +#define GC_PINMUX_DIOA2_SEL 0x19 +#define GC_PINMUX_DIOA3_SEL 0x18 +#define GC_PINMUX_DIOA4_SEL 0x17 +#define GC_PINMUX_DIOA5_SEL 0x16 +#define GC_PINMUX_DIOA6_SEL 0x15 +#define GC_PINMUX_DIOA7_SEL 0x14 +#define GC_PINMUX_DIOA8_SEL 0x13 +#define GC_PINMUX_DIOA9_SEL 0x12 +#define GC_PINMUX_DIOA10_SEL 0x11 +#define GC_PINMUX_DIOA11_SEL 0x10 +#define GC_PINMUX_DIOA12_SEL 0xf +#define GC_PINMUX_DIOA13_SEL 0xe +#define GC_PINMUX_DIOA14_SEL 0xd +#define GC_PINMUX_DIOB0_SEL 0xc +#define GC_PINMUX_DIOB1_SEL 0xb +#define GC_PINMUX_DIOB2_SEL 0xa +#define GC_PINMUX_DIOB3_SEL 0x9 +#define GC_PINMUX_DIOB4_SEL 0x8 +#define GC_PINMUX_DIOB5_SEL 0x7 +#define GC_PINMUX_DIOB6_SEL 0x6 +#define GC_PINMUX_DIOB7_SEL 0x5 +#define GC_PINMUX_DIOM0_SEL 0x20 +#define GC_PINMUX_DIOM1_SEL 0x1f +#define GC_PINMUX_DIOM2_SEL 0x1e +#define GC_PINMUX_DIOM3_SEL 0x1d +#define GC_PINMUX_DIOM4_SEL 0x1c #define GC_PINMUX_GPIO0_GPIO0_SEL 0x1 #define GC_PINMUX_GPIO0_GPIO1_SEL 0x2 #define GC_PINMUX_GPIO0_GPIO2_SEL 0x3 @@ -83,73 +83,48 @@ #define GC_PINMUX_I2C1_SDA_SEL 0x26 #define GC_PINMUX_I2CS0_SCL_SEL 0x21 #define GC_PINMUX_I2CS0_SDA_SEL 0x22 -#define GC_PINMUX_PMU_TESTBUS0_SEL 0x27 -#define GC_PINMUX_PMU_TESTBUS1_SEL 0x28 -#define GC_PINMUX_PMU_TESTBUS2_SEL 0x29 -#define GC_PINMUX_PMU_TESTBUS3_SEL 0x2a -#define GC_PINMUX_PMU_TESTBUS4_SEL 0x2b -#define GC_PINMUX_PMU_TESTBUS5_SEL 0x2c -#define GC_PINMUX_PMU_TESTBUS6_SEL 0x2d -#define GC_PINMUX_PMU_TESTBUS7_SEL 0x2e -#define GC_PINMUX_RBOX0_AC_PRESENT_SEL 0x2f -#define GC_PINMUX_RBOX0_BATT_EN_SEL 0x30 -#define GC_PINMUX_RBOX0_EC_IN_RW_SEL 0x31 -#define GC_PINMUX_RBOX0_EC_RST_L_SEL 0x32 -#define GC_PINMUX_RBOX0_EC_WP_L_SEL 0x33 -#define GC_PINMUX_RBOX0_ENTERING_RW_SEL 0x34 -#define GC_PINMUX_RBOX0_FW_WP_L_SEL 0x35 -#define GC_PINMUX_RBOX0_KSI_SEL 0x36 -#define GC_PINMUX_RBOX0_KSI_SW_SEL 0x37 -#define GC_PINMUX_RBOX0_KSO_INV_SEL 0x38 -#define GC_PINMUX_RBOX0_KSO_SW_SEL 0x39 -#define GC_PINMUX_RBOX0_PWR_BTNO_L_SEL 0x3b -#define GC_PINMUX_RBOX0_PWR_BTN_L_SEL 0x3a -#define GC_PINMUX_RTC0_X_RTC_CLK_SEL 0x3c -#define GC_PINMUX_RTCXOP_SEL 0x1e -#define GC_PINMUX_SPI0_SPICLK_SEL 0x3d -#define GC_PINMUX_SPI0_SPICSB_SEL 0x3e -#define GC_PINMUX_SPI0_SPIMISO_SEL 0x3f -#define GC_PINMUX_SPI0_SPIMOSI_SEL 0x40 -#define GC_PINMUX_SPS0_SPICLK_SEL 0x41 -#define GC_PINMUX_SPS0_SPICSB_SEL 0x42 -#define GC_PINMUX_SPS0_SPIMISO_SEL 0x43 -#define GC_PINMUX_SPS0_SPIMOSI_SEL 0x44 -#define GC_PINMUX_SWDP0_TRACE2_SEL 0x46 -#define GC_PINMUX_SWDP0_TRACE_SEL 0x45 -#define GC_PINMUX_SWDPDATA_SEL 0x20 -#define GC_PINMUX_SWDPTRACE_SEL 0x1f -#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL 0x47 -#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL 0x48 -#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL 0x49 -#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL 0x4a -#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL 0x4b -#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL 0x4c -#define GC_PINMUX_UART0_CTS_SEL 0x4d -#define GC_PINMUX_UART0_RTS_SEL 0x4e -#define GC_PINMUX_UART0_RX_SEL 0x4f -#define GC_PINMUX_UART0_TX_SEL 0x50 -#define GC_PINMUX_UART1_CTS_SEL 0x51 -#define GC_PINMUX_UART1_RTS_SEL 0x52 -#define GC_PINMUX_UART1_RX_SEL 0x53 -#define GC_PINMUX_UART1_TX_SEL 0x54 -#define GC_PINMUX_UART2_CTS_SEL 0x55 -#define GC_PINMUX_UART2_RTS_SEL 0x56 -#define GC_PINMUX_UART2_RX_SEL 0x57 -#define GC_PINMUX_UART2_TX_SEL 0x58 -#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x59 -#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x5a -#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x5b -#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x5c -#define GC_PINMUX_USB0_EXT_RX_DMI_SEL 0x5d -#define GC_PINMUX_USB0_EXT_RX_DPI_SEL 0x5e -#define GC_PINMUX_USB0_EXT_RX_RCV_SEL 0x5f -#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL 0x60 -#define GC_PINMUX_USB0_EXT_TX_DMO_SEL 0x61 -#define GC_PINMUX_USB0_EXT_TX_DPO_SEL 0x62 -#define GC_PINMUX_USB0_EXT_TX_OEB_SEL 0x63 -#define GC_PINMUX_VIO0_SEL 0x21 -#define GC_PINMUX_VIO1_SEL 0x22 -#define GC_PINMUX_XO0_TESTCLK_SEL 0x64 +#define GC_PINMUX_PMU_BROWNOUT_DET_SEL 0x27 +#define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL 0x28 +#define GC_PINMUX_SPI1_SPICLK_SEL 0x29 +#define GC_PINMUX_SPI1_SPICSB_SEL 0x2a +#define GC_PINMUX_SPI1_SPIMISO_SEL 0x2b +#define GC_PINMUX_SPI1_SPIMOSI_SEL 0x2c +#define GC_PINMUX_SWDP0_TRACE2_SEL 0x2d +#define GC_PINMUX_SWDPDATA_SEL 0x3 +#define GC_PINMUX_SWDPTRACE_SEL 0x4 +#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL 0x2e +#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL 0x2f +#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL 0x30 +#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL 0x31 +#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL 0x32 +#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL 0x33 +#define GC_PINMUX_UART0_CTS_SEL 0x34 +#define GC_PINMUX_UART0_RTS_SEL 0x35 +#define GC_PINMUX_UART0_RX_SEL 0x36 +#define GC_PINMUX_UART0_TX_SEL 0x37 +#define GC_PINMUX_UART1_CTS_SEL 0x38 +#define GC_PINMUX_UART1_RTS_SEL 0x39 +#define GC_PINMUX_UART1_RX_SEL 0x3a +#define GC_PINMUX_UART1_TX_SEL 0x3b +#define GC_PINMUX_UART2_CTS_SEL 0x3c +#define GC_PINMUX_UART2_RTS_SEL 0x3d +#define GC_PINMUX_UART2_RX_SEL 0x3e +#define GC_PINMUX_UART2_TX_SEL 0x3f +#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x40 +#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x41 +#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x42 +#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x43 +#define GC_PINMUX_USB0_EXT_RX_DMI_SEL 0x44 +#define GC_PINMUX_USB0_EXT_RX_DPI_SEL 0x45 +#define GC_PINMUX_USB0_EXT_RX_RCV_SEL 0x46 +#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL 0x47 +#define GC_PINMUX_USB0_EXT_TX_DMO_SEL 0x48 +#define GC_PINMUX_USB0_EXT_TX_DPO_SEL 0x49 +#define GC_PINMUX_USB0_EXT_TX_OEB_SEL 0x4a +#define GC_PINMUX_VIO0_SEL 0x2 +#define GC_PINMUX_VIO1_SEL 0x1 +#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL 0x4b +#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL 0x4c #define GC_EXCEPTNUM_RESET 0x1 #define GC_EXCEPTNUM_NMI 0x2 #define GC_EXCEPTNUM_HARDFAULT 0x3 @@ -165,114 +140,194 @@ #define GC_EXCEPTNUM_RESERVED13 0xd #define GC_EXCEPTNUM_PENDSV 0xe #define GC_EXCEPTNUM_SYSTICK 0xf -#define GC_EXCEPTNUM_CAMO0_BREACH_INT 0x10 -#define GC_EXCEPTNUM_FLASH0_EDONEINT 0x11 -#define GC_EXCEPTNUM_FLASH0_PDONEINT 0x12 -#define GC_EXCEPTNUM_GPIO0_GPIO0INT 0x14 -#define GC_EXCEPTNUM_GPIO0_GPIO1INT 0x15 -#define GC_EXCEPTNUM_GPIO0_GPIO2INT 0x16 -#define GC_EXCEPTNUM_GPIO0_GPIO3INT 0x17 -#define GC_EXCEPTNUM_GPIO0_GPIO4INT 0x18 -#define GC_EXCEPTNUM_GPIO0_GPIO5INT 0x19 -#define GC_EXCEPTNUM_GPIO0_GPIO6INT 0x1a -#define GC_EXCEPTNUM_GPIO0_GPIO7INT 0x1b -#define GC_EXCEPTNUM_GPIO0_GPIO8INT 0x1c -#define GC_EXCEPTNUM_GPIO0_GPIO9INT 0x1d -#define GC_EXCEPTNUM_GPIO0_GPIO10INT 0x1e -#define GC_EXCEPTNUM_GPIO0_GPIO11INT 0x1f -#define GC_EXCEPTNUM_GPIO0_GPIO12INT 0x20 -#define GC_EXCEPTNUM_GPIO0_GPIO13INT 0x21 -#define GC_EXCEPTNUM_GPIO0_GPIO14INT 0x22 -#define GC_EXCEPTNUM_GPIO0_GPIO15INT 0x23 -#define GC_EXCEPTNUM_GPIO0_GPIOCOMBINT 0x13 -#define GC_EXCEPTNUM_GPIO1_GPIO0INT 0x25 -#define GC_EXCEPTNUM_GPIO1_GPIO1INT 0x26 -#define GC_EXCEPTNUM_GPIO1_GPIO2INT 0x27 -#define GC_EXCEPTNUM_GPIO1_GPIO3INT 0x28 -#define GC_EXCEPTNUM_GPIO1_GPIO4INT 0x29 -#define GC_EXCEPTNUM_GPIO1_GPIO5INT 0x2a -#define GC_EXCEPTNUM_GPIO1_GPIO6INT 0x2b -#define GC_EXCEPTNUM_GPIO1_GPIO7INT 0x2c -#define GC_EXCEPTNUM_GPIO1_GPIO8INT 0x2d -#define GC_EXCEPTNUM_GPIO1_GPIO9INT 0x2e -#define GC_EXCEPTNUM_GPIO1_GPIO10INT 0x2f -#define GC_EXCEPTNUM_GPIO1_GPIO11INT 0x30 -#define GC_EXCEPTNUM_GPIO1_GPIO12INT 0x31 -#define GC_EXCEPTNUM_GPIO1_GPIO13INT 0x32 -#define GC_EXCEPTNUM_GPIO1_GPIO14INT 0x33 -#define GC_EXCEPTNUM_GPIO1_GPIO15INT 0x34 -#define GC_EXCEPTNUM_GPIO1_GPIOCOMBINT 0x24 -#define GC_EXCEPTNUM_I2C0_I2CINT 0x38 -#define GC_EXCEPTNUM_I2C1_I2CINT 0x39 -#define GC_EXCEPTNUM_I2CS0_INTR_READ_BEGIN_INT 0x35 -#define GC_EXCEPTNUM_I2CS0_INTR_READ_COMPLETE_INT 0x36 -#define GC_EXCEPTNUM_I2CS0_INTR_WRITE_COMPLETE_INT 0x37 -#define GC_EXCEPTNUM_PMU_PMUINT 0x3a -#define GC_EXCEPTNUM_SHA0_DSHA_INT 0x3b -#define GC_EXCEPTNUM_SPI0_SPITXINT 0x3c -#define GC_EXCEPTNUM_SPS0_REGION0_BUF_LVL 0x3f -#define GC_EXCEPTNUM_SPS0_REGION1_BUF_LVL 0x40 -#define GC_EXCEPTNUM_SPS0_REGION2_BUF_LVL 0x41 -#define GC_EXCEPTNUM_SPS0_REGION3_BUF_LVL 0x42 -#define GC_EXCEPTNUM_SPS0_ROM_CMD_END 0x43 -#define GC_EXCEPTNUM_SPS0_ROM_CMD_START 0x44 -#define GC_EXCEPTNUM_SPS0_CS_ASSERT_INTR 0x3d -#define GC_EXCEPTNUM_SPS0_CS_DEASSERT_INTR 0x3e -#define GC_EXCEPTNUM_SPS0_RXFIFO_LVL_INTR 0x45 -#define GC_EXCEPTNUM_SPS0_RXFIFO_OVERFLOW_INTR 0x46 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT0 0x47 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT1 0x48 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT2 0x49 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT3 0x4a -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT4 0x4b -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT5 0x4c -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT6 0x4d -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT7 0x4e -#define GC_EXCEPTNUM_SPS0_TXFIFO_EMPTY_INTR 0x4f -#define GC_EXCEPTNUM_SPS0_TXFIFO_FULL_INTR 0x50 -#define GC_EXCEPTNUM_SPS0_TXFIFO_LVL_INTR 0x51 -#define GC_EXCEPTNUM_TEMP0_ADC_ICLKDV_INT 0x52 -#define GC_EXCEPTNUM_TEMP0_COMP_OVERFLOW_INT 0x53 -#define GC_EXCEPTNUM_TEMP0_MAX_TEMP_DIFF_INT 0x54 -#define GC_EXCEPTNUM_TEMP0_MAX_TEMP_INT 0x55 -#define GC_EXCEPTNUM_TEMP0_MIN_TEMP_INT 0x56 -#define GC_EXCEPTNUM_TIMEHS0_TIMINT1 0x58 -#define GC_EXCEPTNUM_TIMEHS0_TIMINT2 0x59 -#define GC_EXCEPTNUM_TIMEHS0_TIMINTC 0x57 -#define GC_EXCEPTNUM_TIMEHS1_TIMINT1 0x5b -#define GC_EXCEPTNUM_TIMEHS1_TIMINT2 0x5c -#define GC_EXCEPTNUM_TIMEHS1_TIMINTC 0x5a -#define GC_EXCEPTNUM_TIMELS0_TIMINT0 0x5d -#define GC_EXCEPTNUM_TIMELS0_TIMINT1 0x5e -#define GC_EXCEPTNUM_TRNG0_INTR_BUFFER_FULL_INT 0x5f -#define GC_EXCEPTNUM_TRNG0_INTR_CALC_DONE_INT 0x60 -#define GC_EXCEPTNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 0x61 -#define GC_EXCEPTNUM_TRNG0_INTR_STAT_30_70_INT 0x62 -#define GC_EXCEPTNUM_TRNG0_INTR_STAT_40_60_INT 0x63 -#define GC_EXCEPTNUM_TRNG0_INTR_TIMEOUT_INT 0x64 -#define GC_EXCEPTNUM_UART0_RXBINT 0x65 -#define GC_EXCEPTNUM_UART0_RXFINT 0x66 -#define GC_EXCEPTNUM_UART0_RXINT 0x67 -#define GC_EXCEPTNUM_UART0_RXOVINT 0x68 -#define GC_EXCEPTNUM_UART0_RXTOINT 0x69 -#define GC_EXCEPTNUM_UART0_TXINT 0x6a -#define GC_EXCEPTNUM_UART0_TXOVINT 0x6b -#define GC_EXCEPTNUM_UART1_RXBINT 0x6c -#define GC_EXCEPTNUM_UART1_RXFINT 0x6d -#define GC_EXCEPTNUM_UART1_RXINT 0x6e -#define GC_EXCEPTNUM_UART1_RXOVINT 0x6f -#define GC_EXCEPTNUM_UART1_RXTOINT 0x70 -#define GC_EXCEPTNUM_UART1_TXINT 0x71 -#define GC_EXCEPTNUM_UART1_TXOVINT 0x72 -#define GC_EXCEPTNUM_UART2_RXBINT 0x73 -#define GC_EXCEPTNUM_UART2_RXFINT 0x74 -#define GC_EXCEPTNUM_UART2_RXINT 0x75 -#define GC_EXCEPTNUM_UART2_RXOVINT 0x76 -#define GC_EXCEPTNUM_UART2_RXTOINT 0x77 -#define GC_EXCEPTNUM_UART2_TXINT 0x78 -#define GC_EXCEPTNUM_UART2_TXOVINT 0x79 -#define GC_EXCEPTNUM_USB0_USBINTR 0x7a -#define GC_EXCEPTNUM_WATCHDOG0_WDOGINT 0x7b +#define GC_EXCEPTNUM_AES0_DONE_CIPHER_INT 0x10 +#define GC_EXCEPTNUM_AES0_DONE_KEYEXPANSION_INT 0x11 +#define GC_EXCEPTNUM_AES0_DONE_WIPE_SECRETS_INT 0x12 +#define GC_EXCEPTNUM_AES0_RFIFO_OVERFLOW_INT 0x13 +#define GC_EXCEPTNUM_AES0_RFIFO_UNDERFLOW_INT 0x14 +#define GC_EXCEPTNUM_AES0_WFIFO_OVERFLOW_INT 0x15 +#define GC_EXCEPTNUM_CRYPTO0_BREAK_INT 0x16 +#define GC_EXCEPTNUM_CRYPTO0_DMEM_PTRS_OVERFLOW_INT 0x17 +#define GC_EXCEPTNUM_CRYPTO0_DONE_WIPE_SECRETS_INT 0x18 +#define GC_EXCEPTNUM_CRYPTO0_DRF_PTRS_OVERFLOW_INT 0x19 +#define GC_EXCEPTNUM_CRYPTO0_HOST_CMD_DONE_INT 0x1a +#define GC_EXCEPTNUM_CRYPTO0_HOST_CMD_RECV_INT 0x1b +#define GC_EXCEPTNUM_CRYPTO0_LOOP_STACK_OVERFLOW_INT 0x1c +#define GC_EXCEPTNUM_CRYPTO0_LOOP_STACK_UNDERFLOW_INT 0x1d +#define GC_EXCEPTNUM_CRYPTO0_PC_STACK_OVERFLOW_INT 0x1e +#define GC_EXCEPTNUM_CRYPTO0_TRAP_INT 0x1f +#define GC_EXCEPTNUM_DMA0_INTR_COMPLETE_CHAN_INT 0x20 +#define GC_EXCEPTNUM_DMA0_INTR_ERROR_CHAN_INT 0x21 +#define GC_EXCEPTNUM_DMA0_INTR_PROG_CHAN_INT 0x22 +#define GC_EXCEPTNUM_DMA0_INTR_TIMEOUT_CHAN_INT 0x23 +#define GC_EXCEPTNUM_FLASH0_EDONEINT 0x24 +#define GC_EXCEPTNUM_FLASH0_PDONEINT 0x25 +#define GC_EXCEPTNUM_GLOBALSEC_AES0_EXEC_HKEY_CTR_MAX_ALERT_INT 0x26 +#define GC_EXCEPTNUM_GLOBALSEC_AES0_EXEC_STD_CTR_MAX_ALERT_INT 0x27 +#define GC_EXCEPTNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 0x28 +#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 0x29 +#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 0x2a +#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 0x2b +#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 0x2c +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 0x2d +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 0x2e +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 0x2f +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 0x30 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 0x31 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 0x32 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 0x33 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 0x34 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 0x35 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 0x36 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 0x37 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 0x38 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 0x39 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 0x3a +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 0x3b +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 0x3c +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 0x3d +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 0x3e +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 0x3f +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 0x40 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 0x41 +#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 0x42 +#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 0x43 +#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 0x44 +#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 0x45 +#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 0x46 +#define GC_EXCEPTNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 0x47 +#define GC_EXCEPTNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 0x48 +#define GC_EXCEPTNUM_GPIO0_GPIO0INT 0x4a +#define GC_EXCEPTNUM_GPIO0_GPIO1INT 0x4b +#define GC_EXCEPTNUM_GPIO0_GPIO2INT 0x4c +#define GC_EXCEPTNUM_GPIO0_GPIO3INT 0x4d +#define GC_EXCEPTNUM_GPIO0_GPIO4INT 0x4e +#define GC_EXCEPTNUM_GPIO0_GPIO5INT 0x4f +#define GC_EXCEPTNUM_GPIO0_GPIO6INT 0x50 +#define GC_EXCEPTNUM_GPIO0_GPIO7INT 0x51 +#define GC_EXCEPTNUM_GPIO0_GPIO8INT 0x52 +#define GC_EXCEPTNUM_GPIO0_GPIO9INT 0x53 +#define GC_EXCEPTNUM_GPIO0_GPIO10INT 0x54 +#define GC_EXCEPTNUM_GPIO0_GPIO11INT 0x55 +#define GC_EXCEPTNUM_GPIO0_GPIO12INT 0x56 +#define GC_EXCEPTNUM_GPIO0_GPIO13INT 0x57 +#define GC_EXCEPTNUM_GPIO0_GPIO14INT 0x58 +#define GC_EXCEPTNUM_GPIO0_GPIO15INT 0x59 +#define GC_EXCEPTNUM_GPIO0_GPIOCOMBINT 0x49 +#define GC_EXCEPTNUM_GPIO1_GPIO0INT 0x5b +#define GC_EXCEPTNUM_GPIO1_GPIO1INT 0x5c +#define GC_EXCEPTNUM_GPIO1_GPIO2INT 0x5d +#define GC_EXCEPTNUM_GPIO1_GPIO3INT 0x5e +#define GC_EXCEPTNUM_GPIO1_GPIO4INT 0x5f +#define GC_EXCEPTNUM_GPIO1_GPIO5INT 0x60 +#define GC_EXCEPTNUM_GPIO1_GPIO6INT 0x61 +#define GC_EXCEPTNUM_GPIO1_GPIO7INT 0x62 +#define GC_EXCEPTNUM_GPIO1_GPIO8INT 0x63 +#define GC_EXCEPTNUM_GPIO1_GPIO9INT 0x64 +#define GC_EXCEPTNUM_GPIO1_GPIO10INT 0x65 +#define GC_EXCEPTNUM_GPIO1_GPIO11INT 0x66 +#define GC_EXCEPTNUM_GPIO1_GPIO12INT 0x67 +#define GC_EXCEPTNUM_GPIO1_GPIO13INT 0x68 +#define GC_EXCEPTNUM_GPIO1_GPIO14INT 0x69 +#define GC_EXCEPTNUM_GPIO1_GPIO15INT 0x6a +#define GC_EXCEPTNUM_GPIO1_GPIOCOMBINT 0x5a +#define GC_EXCEPTNUM_I2C0_I2CINT 0x6e +#define GC_EXCEPTNUM_I2C1_I2CINT 0x6f +#define GC_EXCEPTNUM_I2CS0_INTR_READ_BEGIN_INT 0x6b +#define GC_EXCEPTNUM_I2CS0_INTR_READ_COMPLETE_INT 0x6c +#define GC_EXCEPTNUM_I2CS0_INTR_WRITE_COMPLETE_INT 0x6d +#define GC_EXCEPTNUM_PMU_INTR_WAKEUP_INT 0x70 +#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_FED_INT 0x71 +#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_RED_INT 0x72 +#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 0x73 +#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 0x74 +#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 0x75 +#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_L_FED_INT 0x76 +#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_L_RED_INT 0x77 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_FED_INT 0x78 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_RED_INT 0x79 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_FED_INT 0x7a +#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_RED_INT 0x7b +#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_FED_INT 0x7c +#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_RED_INT 0x7d +#define GC_EXCEPTNUM_RDD0_INTR_NEW_STATE_DETECTED_INT 0x7e +#define GC_EXCEPTNUM_SHA0_DSHA_INT 0x7f +#define GC_EXCEPTNUM_SPI0_SPITXINT 0x80 +#define GC_EXCEPTNUM_SPI1_SPITXINT 0x81 +#define GC_EXCEPTNUM_SPS0_CS_ASSERT_INTR 0x82 +#define GC_EXCEPTNUM_SPS0_CS_DEASSERT_INTR 0x83 +#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 0x84 +#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 0x85 +#define GC_EXCEPTNUM_SPS0_INTR_CMD_MEM_OVFL_INT 0x86 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 0x87 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 0x88 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 0x89 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 0x8a +#define GC_EXCEPTNUM_SPS0_RXFIFO_LVL_INTR 0x8b +#define GC_EXCEPTNUM_SPS0_RXFIFO_OVERFLOW_INTR 0x8c +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT0 0x8d +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT1 0x8e +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT2 0x8f +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT3 0x90 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT4 0x91 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT5 0x92 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT6 0x93 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT7 0x94 +#define GC_EXCEPTNUM_SPS0_TXFIFO_EMPTY_INTR 0x95 +#define GC_EXCEPTNUM_SPS0_TXFIFO_FULL_INTR 0x96 +#define GC_EXCEPTNUM_SPS0_TXFIFO_LVL_INTR 0x97 +#define GC_EXCEPTNUM_TEMP0_ADC_ICLKDV_INT 0x98 +#define GC_EXCEPTNUM_TEMP0_COMP_OVERFLOW_INT 0x99 +#define GC_EXCEPTNUM_TIMEHS0_TIMINT1 0x9b +#define GC_EXCEPTNUM_TIMEHS0_TIMINT2 0x9c +#define GC_EXCEPTNUM_TIMEHS0_TIMINTC 0x9a +#define GC_EXCEPTNUM_TIMEHS1_TIMINT1 0x9e +#define GC_EXCEPTNUM_TIMEHS1_TIMINT2 0x9f +#define GC_EXCEPTNUM_TIMEHS1_TIMINTC 0x9d +#define GC_EXCEPTNUM_TIMELS0_TIMINT0 0xa0 +#define GC_EXCEPTNUM_TIMELS0_TIMINT1 0xa1 +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 0xa2 +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 0xa3 +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 0xa4 +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 0xa5 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 0xa6 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 0xa7 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 0xa8 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 0xa9 +#define GC_EXCEPTNUM_TRNG0_INTR_BUFFER_FULL_INT 0xaa +#define GC_EXCEPTNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 0xab +#define GC_EXCEPTNUM_TRNG0_INTR_READ_EMPTY_INT 0xac +#define GC_EXCEPTNUM_UART0_RXBINT 0xad +#define GC_EXCEPTNUM_UART0_RXFINT 0xae +#define GC_EXCEPTNUM_UART0_RXINT 0xaf +#define GC_EXCEPTNUM_UART0_RXOVINT 0xb0 +#define GC_EXCEPTNUM_UART0_RXTOINT 0xb1 +#define GC_EXCEPTNUM_UART0_TXINT 0xb2 +#define GC_EXCEPTNUM_UART0_TXOVINT 0xb3 +#define GC_EXCEPTNUM_UART1_RXBINT 0xb4 +#define GC_EXCEPTNUM_UART1_RXFINT 0xb5 +#define GC_EXCEPTNUM_UART1_RXINT 0xb6 +#define GC_EXCEPTNUM_UART1_RXOVINT 0xb7 +#define GC_EXCEPTNUM_UART1_RXTOINT 0xb8 +#define GC_EXCEPTNUM_UART1_TXINT 0xb9 +#define GC_EXCEPTNUM_UART1_TXOVINT 0xba +#define GC_EXCEPTNUM_UART2_RXBINT 0xbb +#define GC_EXCEPTNUM_UART2_RXFINT 0xbc +#define GC_EXCEPTNUM_UART2_RXINT 0xbd +#define GC_EXCEPTNUM_UART2_RXOVINT 0xbe +#define GC_EXCEPTNUM_UART2_RXTOINT 0xbf +#define GC_EXCEPTNUM_UART2_TXINT 0xc0 +#define GC_EXCEPTNUM_UART2_TXOVINT 0xc1 +#define GC_EXCEPTNUM_USB0_USBINTR 0xc2 +#define GC_EXCEPTNUM_WATCHDOG0_WDOGINT 0xc3 +#define GC_EXCEPTNUM_XO0_CLK_JTR_NOP_SEEN_INT 0xc4 +#define GC_EXCEPTNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 0xc5 +#define GC_EXCEPTNUM_XO0_CLK_TIMER_NOP_SEEN_INT 0xc6 +#define GC_EXCEPTNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 0xc7 +#define GC_EXCEPTNUM_XO0_FAST_CALIB_OVERFLOW_INT 0xc8 +#define GC_EXCEPTNUM_XO0_FAST_CALIB_UNDERRUN_INT 0xc9 +#define GC_EXCEPTNUM_XO0_SLOW_CALIB_OVERFLOW_INT 0xca +#define GC_EXCEPTNUM_XO0_SLOW_CALIB_UNDERRUN_INT 0xcb #define GC_IRQNUM_RESET 0 #define GC_IRQNUM_NMI 0 #define GC_IRQNUM_HARDFAULT 0 @@ -288,167 +343,243 @@ #define GC_IRQNUM_RESERVED13 0 #define GC_IRQNUM_PENDSV 0 #define GC_IRQNUM_SYSTICK 0 -#define GC_IRQNUM_CAMO0_BREACH_INT 0 -#define GC_IRQNUM_FLASH0_EDONEINT 1 -#define GC_IRQNUM_FLASH0_PDONEINT 2 -#define GC_IRQNUM_GPIO0_GPIO0INT 4 -#define GC_IRQNUM_GPIO0_GPIO1INT 5 -#define GC_IRQNUM_GPIO0_GPIO2INT 6 -#define GC_IRQNUM_GPIO0_GPIO3INT 7 -#define GC_IRQNUM_GPIO0_GPIO4INT 8 -#define GC_IRQNUM_GPIO0_GPIO5INT 9 -#define GC_IRQNUM_GPIO0_GPIO6INT 10 -#define GC_IRQNUM_GPIO0_GPIO7INT 11 -#define GC_IRQNUM_GPIO0_GPIO8INT 12 -#define GC_IRQNUM_GPIO0_GPIO9INT 13 -#define GC_IRQNUM_GPIO0_GPIO10INT 14 -#define GC_IRQNUM_GPIO0_GPIO11INT 15 -#define GC_IRQNUM_GPIO0_GPIO12INT 16 -#define GC_IRQNUM_GPIO0_GPIO13INT 17 -#define GC_IRQNUM_GPIO0_GPIO14INT 18 -#define GC_IRQNUM_GPIO0_GPIO15INT 19 -#define GC_IRQNUM_GPIO0_GPIOCOMBINT 3 -#define GC_IRQNUM_GPIO1_GPIO0INT 21 -#define GC_IRQNUM_GPIO1_GPIO1INT 22 -#define GC_IRQNUM_GPIO1_GPIO2INT 23 -#define GC_IRQNUM_GPIO1_GPIO3INT 24 -#define GC_IRQNUM_GPIO1_GPIO4INT 25 -#define GC_IRQNUM_GPIO1_GPIO5INT 26 -#define GC_IRQNUM_GPIO1_GPIO6INT 27 -#define GC_IRQNUM_GPIO1_GPIO7INT 28 -#define GC_IRQNUM_GPIO1_GPIO8INT 29 -#define GC_IRQNUM_GPIO1_GPIO9INT 30 -#define GC_IRQNUM_GPIO1_GPIO10INT 31 -#define GC_IRQNUM_GPIO1_GPIO11INT 32 -#define GC_IRQNUM_GPIO1_GPIO12INT 33 -#define GC_IRQNUM_GPIO1_GPIO13INT 34 -#define GC_IRQNUM_GPIO1_GPIO14INT 35 -#define GC_IRQNUM_GPIO1_GPIO15INT 36 -#define GC_IRQNUM_GPIO1_GPIOCOMBINT 20 -#define GC_IRQNUM_I2C0_I2CINT 40 -#define GC_IRQNUM_I2C1_I2CINT 41 -#define GC_IRQNUM_I2CS0_INTR_READ_BEGIN_INT 37 -#define GC_IRQNUM_I2CS0_INTR_READ_COMPLETE_INT 38 -#define GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT 39 -#define GC_IRQNUM_PMU_PMUINT 42 -#define GC_IRQNUM_SHA0_DSHA_INT 43 -#define GC_IRQNUM_SPI0_SPITXINT 44 -#define GC_IRQNUM_SPS0_REGION0_BUF_LVL 47 -#define GC_IRQNUM_SPS0_REGION1_BUF_LVL 48 -#define GC_IRQNUM_SPS0_REGION2_BUF_LVL 49 -#define GC_IRQNUM_SPS0_REGION3_BUF_LVL 50 -#define GC_IRQNUM_SPS0_ROM_CMD_END 51 -#define GC_IRQNUM_SPS0_ROM_CMD_START 52 -#define GC_IRQNUM_SPS0_CS_ASSERT_INTR 45 -#define GC_IRQNUM_SPS0_CS_DEASSERT_INTR 46 -#define GC_IRQNUM_SPS0_RXFIFO_LVL_INTR 53 -#define GC_IRQNUM_SPS0_RXFIFO_OVERFLOW_INTR 54 -#define GC_IRQNUM_SPS0_SPSCTRLINT0 55 -#define GC_IRQNUM_SPS0_SPSCTRLINT1 56 -#define GC_IRQNUM_SPS0_SPSCTRLINT2 57 -#define GC_IRQNUM_SPS0_SPSCTRLINT3 58 -#define GC_IRQNUM_SPS0_SPSCTRLINT4 59 -#define GC_IRQNUM_SPS0_SPSCTRLINT5 60 -#define GC_IRQNUM_SPS0_SPSCTRLINT6 61 -#define GC_IRQNUM_SPS0_SPSCTRLINT7 62 -#define GC_IRQNUM_SPS0_TXFIFO_EMPTY_INTR 63 -#define GC_IRQNUM_SPS0_TXFIFO_FULL_INTR 64 -#define GC_IRQNUM_SPS0_TXFIFO_LVL_INTR 65 -#define GC_IRQNUM_TEMP0_ADC_ICLKDV_INT 66 -#define GC_IRQNUM_TEMP0_COMP_OVERFLOW_INT 67 -#define GC_IRQNUM_TEMP0_MAX_TEMP_DIFF_INT 68 -#define GC_IRQNUM_TEMP0_MAX_TEMP_INT 69 -#define GC_IRQNUM_TEMP0_MIN_TEMP_INT 70 -#define GC_IRQNUM_TIMEHS0_TIMINT1 72 -#define GC_IRQNUM_TIMEHS0_TIMINT2 73 -#define GC_IRQNUM_TIMEHS0_TIMINTC 71 -#define GC_IRQNUM_TIMEHS1_TIMINT1 75 -#define GC_IRQNUM_TIMEHS1_TIMINT2 76 -#define GC_IRQNUM_TIMEHS1_TIMINTC 74 -#define GC_IRQNUM_TIMELS0_TIMINT0 77 -#define GC_IRQNUM_TIMELS0_TIMINT1 78 -#define GC_IRQNUM_TRNG0_INTR_BUFFER_FULL_INT 79 -#define GC_IRQNUM_TRNG0_INTR_CALC_DONE_INT 80 -#define GC_IRQNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 81 -#define GC_IRQNUM_TRNG0_INTR_STAT_30_70_INT 82 -#define GC_IRQNUM_TRNG0_INTR_STAT_40_60_INT 83 -#define GC_IRQNUM_TRNG0_INTR_TIMEOUT_INT 84 -#define GC_IRQNUM_UART0_RXBINT 85 -#define GC_IRQNUM_UART0_RXFINT 86 -#define GC_IRQNUM_UART0_RXINT 87 -#define GC_IRQNUM_UART0_RXOVINT 88 -#define GC_IRQNUM_UART0_RXTOINT 89 -#define GC_IRQNUM_UART0_TXINT 90 -#define GC_IRQNUM_UART0_TXOVINT 91 -#define GC_IRQNUM_UART1_RXBINT 92 -#define GC_IRQNUM_UART1_RXFINT 93 -#define GC_IRQNUM_UART1_RXINT 94 -#define GC_IRQNUM_UART1_RXOVINT 95 -#define GC_IRQNUM_UART1_RXTOINT 96 -#define GC_IRQNUM_UART1_TXINT 97 -#define GC_IRQNUM_UART1_TXOVINT 98 -#define GC_IRQNUM_UART2_RXBINT 99 -#define GC_IRQNUM_UART2_RXFINT 100 -#define GC_IRQNUM_UART2_RXINT 101 -#define GC_IRQNUM_UART2_RXOVINT 102 -#define GC_IRQNUM_UART2_RXTOINT 103 -#define GC_IRQNUM_UART2_TXINT 104 -#define GC_IRQNUM_UART2_TXOVINT 105 -#define GC_IRQNUM_USB0_USBINTR 106 -#define GC_IRQNUM_WATCHDOG0_WDOGINT 107 -#define GC_AES0_BASE_ADDR 0x40440000 -#define GC_AES1_BASE_ADDR 0x40450000 -#define GC_CAMO0_BASE_ADDR 0x40470000 +#define GC_IRQNUM_AES0_DONE_CIPHER_INT 0 +#define GC_IRQNUM_AES0_DONE_KEYEXPANSION_INT 1 +#define GC_IRQNUM_AES0_DONE_WIPE_SECRETS_INT 2 +#define GC_IRQNUM_AES0_RFIFO_OVERFLOW_INT 3 +#define GC_IRQNUM_AES0_RFIFO_UNDERFLOW_INT 4 +#define GC_IRQNUM_AES0_WFIFO_OVERFLOW_INT 5 +#define GC_IRQNUM_CRYPTO0_BREAK_INT 6 +#define GC_IRQNUM_CRYPTO0_DMEM_PTRS_OVERFLOW_INT 7 +#define GC_IRQNUM_CRYPTO0_DONE_WIPE_SECRETS_INT 8 +#define GC_IRQNUM_CRYPTO0_DRF_PTRS_OVERFLOW_INT 9 +#define GC_IRQNUM_CRYPTO0_HOST_CMD_DONE_INT 10 +#define GC_IRQNUM_CRYPTO0_HOST_CMD_RECV_INT 11 +#define GC_IRQNUM_CRYPTO0_LOOP_STACK_OVERFLOW_INT 12 +#define GC_IRQNUM_CRYPTO0_LOOP_STACK_UNDERFLOW_INT 13 +#define GC_IRQNUM_CRYPTO0_PC_STACK_OVERFLOW_INT 14 +#define GC_IRQNUM_CRYPTO0_TRAP_INT 15 +#define GC_IRQNUM_DMA0_INTR_COMPLETE_CHAN_INT 16 +#define GC_IRQNUM_DMA0_INTR_ERROR_CHAN_INT 17 +#define GC_IRQNUM_DMA0_INTR_PROG_CHAN_INT 18 +#define GC_IRQNUM_DMA0_INTR_TIMEOUT_CHAN_INT 19 +#define GC_IRQNUM_FLASH0_EDONEINT 20 +#define GC_IRQNUM_FLASH0_PDONEINT 21 +#define GC_IRQNUM_GLOBALSEC_AES0_EXEC_HKEY_CTR_MAX_ALERT_INT 22 +#define GC_IRQNUM_GLOBALSEC_AES0_EXEC_STD_CTR_MAX_ALERT_INT 23 +#define GC_IRQNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 24 +#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 25 +#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 26 +#define GC_IRQNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 27 +#define GC_IRQNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 28 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 29 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 30 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 31 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 32 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 33 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 34 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 35 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 36 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 37 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 38 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 39 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 40 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 41 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 42 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 43 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 44 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 45 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 46 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 47 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 48 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 49 +#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 50 +#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 51 +#define GC_IRQNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 52 +#define GC_IRQNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 53 +#define GC_IRQNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 54 +#define GC_IRQNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 55 +#define GC_IRQNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 56 +#define GC_IRQNUM_GPIO0_GPIO0INT 58 +#define GC_IRQNUM_GPIO0_GPIO1INT 59 +#define GC_IRQNUM_GPIO0_GPIO2INT 60 +#define GC_IRQNUM_GPIO0_GPIO3INT 61 +#define GC_IRQNUM_GPIO0_GPIO4INT 62 +#define GC_IRQNUM_GPIO0_GPIO5INT 63 +#define GC_IRQNUM_GPIO0_GPIO6INT 64 +#define GC_IRQNUM_GPIO0_GPIO7INT 65 +#define GC_IRQNUM_GPIO0_GPIO8INT 66 +#define GC_IRQNUM_GPIO0_GPIO9INT 67 +#define GC_IRQNUM_GPIO0_GPIO10INT 68 +#define GC_IRQNUM_GPIO0_GPIO11INT 69 +#define GC_IRQNUM_GPIO0_GPIO12INT 70 +#define GC_IRQNUM_GPIO0_GPIO13INT 71 +#define GC_IRQNUM_GPIO0_GPIO14INT 72 +#define GC_IRQNUM_GPIO0_GPIO15INT 73 +#define GC_IRQNUM_GPIO0_GPIOCOMBINT 57 +#define GC_IRQNUM_GPIO1_GPIO0INT 75 +#define GC_IRQNUM_GPIO1_GPIO1INT 76 +#define GC_IRQNUM_GPIO1_GPIO2INT 77 +#define GC_IRQNUM_GPIO1_GPIO3INT 78 +#define GC_IRQNUM_GPIO1_GPIO4INT 79 +#define GC_IRQNUM_GPIO1_GPIO5INT 80 +#define GC_IRQNUM_GPIO1_GPIO6INT 81 +#define GC_IRQNUM_GPIO1_GPIO7INT 82 +#define GC_IRQNUM_GPIO1_GPIO8INT 83 +#define GC_IRQNUM_GPIO1_GPIO9INT 84 +#define GC_IRQNUM_GPIO1_GPIO10INT 85 +#define GC_IRQNUM_GPIO1_GPIO11INT 86 +#define GC_IRQNUM_GPIO1_GPIO12INT 87 +#define GC_IRQNUM_GPIO1_GPIO13INT 88 +#define GC_IRQNUM_GPIO1_GPIO14INT 89 +#define GC_IRQNUM_GPIO1_GPIO15INT 90 +#define GC_IRQNUM_GPIO1_GPIOCOMBINT 74 +#define GC_IRQNUM_I2C0_I2CINT 94 +#define GC_IRQNUM_I2C1_I2CINT 95 +#define GC_IRQNUM_I2CS0_INTR_READ_BEGIN_INT 91 +#define GC_IRQNUM_I2CS0_INTR_READ_COMPLETE_INT 92 +#define GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT 93 +#define GC_IRQNUM_PMU_INTR_WAKEUP_INT 96 +#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_FED_INT 97 +#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_RED_INT 98 +#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 99 +#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 100 +#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 101 +#define GC_IRQNUM_RBOX0_INTR_EC_RST_L_FED_INT 102 +#define GC_IRQNUM_RBOX0_INTR_EC_RST_L_RED_INT 103 +#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_FED_INT 104 +#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_RED_INT 105 +#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_FED_INT 106 +#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_RED_INT 107 +#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT 108 +#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT 109 +#define GC_IRQNUM_RDD0_INTR_NEW_STATE_DETECTED_INT 110 +#define GC_IRQNUM_SHA0_DSHA_INT 111 +#define GC_IRQNUM_SPI0_SPITXINT 112 +#define GC_IRQNUM_SPI1_SPITXINT 113 +#define GC_IRQNUM_SPS0_CS_ASSERT_INTR 114 +#define GC_IRQNUM_SPS0_CS_DEASSERT_INTR 115 +#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 116 +#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 117 +#define GC_IRQNUM_SPS0_INTR_CMD_MEM_OVFL_INT 118 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 119 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 120 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 121 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 122 +#define GC_IRQNUM_SPS0_RXFIFO_LVL_INTR 123 +#define GC_IRQNUM_SPS0_RXFIFO_OVERFLOW_INTR 124 +#define GC_IRQNUM_SPS0_SPSCTRLINT0 125 +#define GC_IRQNUM_SPS0_SPSCTRLINT1 126 +#define GC_IRQNUM_SPS0_SPSCTRLINT2 127 +#define GC_IRQNUM_SPS0_SPSCTRLINT3 128 +#define GC_IRQNUM_SPS0_SPSCTRLINT4 129 +#define GC_IRQNUM_SPS0_SPSCTRLINT5 130 +#define GC_IRQNUM_SPS0_SPSCTRLINT6 131 +#define GC_IRQNUM_SPS0_SPSCTRLINT7 132 +#define GC_IRQNUM_SPS0_TXFIFO_EMPTY_INTR 133 +#define GC_IRQNUM_SPS0_TXFIFO_FULL_INTR 134 +#define GC_IRQNUM_SPS0_TXFIFO_LVL_INTR 135 +#define GC_IRQNUM_TEMP0_ADC_ICLKDV_INT 136 +#define GC_IRQNUM_TEMP0_COMP_OVERFLOW_INT 137 +#define GC_IRQNUM_TIMEHS0_TIMINT1 139 +#define GC_IRQNUM_TIMEHS0_TIMINT2 140 +#define GC_IRQNUM_TIMEHS0_TIMINTC 138 +#define GC_IRQNUM_TIMEHS1_TIMINT1 142 +#define GC_IRQNUM_TIMEHS1_TIMINT2 143 +#define GC_IRQNUM_TIMEHS1_TIMINTC 141 +#define GC_IRQNUM_TIMELS0_TIMINT0 144 +#define GC_IRQNUM_TIMELS0_TIMINT1 145 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 146 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 147 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 148 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 149 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 150 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 151 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 152 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 153 +#define GC_IRQNUM_TRNG0_INTR_BUFFER_FULL_INT 154 +#define GC_IRQNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 155 +#define GC_IRQNUM_TRNG0_INTR_READ_EMPTY_INT 156 +#define GC_IRQNUM_UART0_RXBINT 157 +#define GC_IRQNUM_UART0_RXFINT 158 +#define GC_IRQNUM_UART0_RXINT 159 +#define GC_IRQNUM_UART0_RXOVINT 160 +#define GC_IRQNUM_UART0_RXTOINT 161 +#define GC_IRQNUM_UART0_TXINT 162 +#define GC_IRQNUM_UART0_TXOVINT 163 +#define GC_IRQNUM_UART1_RXBINT 164 +#define GC_IRQNUM_UART1_RXFINT 165 +#define GC_IRQNUM_UART1_RXINT 166 +#define GC_IRQNUM_UART1_RXOVINT 167 +#define GC_IRQNUM_UART1_RXTOINT 168 +#define GC_IRQNUM_UART1_TXINT 169 +#define GC_IRQNUM_UART1_TXOVINT 170 +#define GC_IRQNUM_UART2_RXBINT 171 +#define GC_IRQNUM_UART2_RXFINT 172 +#define GC_IRQNUM_UART2_RXINT 173 +#define GC_IRQNUM_UART2_RXOVINT 174 +#define GC_IRQNUM_UART2_RXTOINT 175 +#define GC_IRQNUM_UART2_TXINT 176 +#define GC_IRQNUM_UART2_TXOVINT 177 +#define GC_IRQNUM_USB0_USBINTR 178 +#define GC_IRQNUM_WATCHDOG0_WDOGINT 179 +#define GC_IRQNUM_XO0_CLK_JTR_NOP_SEEN_INT 180 +#define GC_IRQNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 181 +#define GC_IRQNUM_XO0_CLK_TIMER_NOP_SEEN_INT 182 +#define GC_IRQNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 183 +#define GC_IRQNUM_XO0_FAST_CALIB_OVERFLOW_INT 184 +#define GC_IRQNUM_XO0_FAST_CALIB_UNDERRUN_INT 185 +#define GC_IRQNUM_XO0_SLOW_CALIB_OVERFLOW_INT 186 +#define GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT 187 +#define GC_AES0_BASE_ADDR 0x40420000 +#define GC_CAMO0_BASE_ADDR 0x40440000 +#define GC_CRYPTO0_BASE_ADDR 0x40430000 +#define GC_DMA0_BASE_ADDR 0x40450000 #define GC_FLASH0_BASE_ADDR 0x40710000 +#define GC_FUSE0_BASE_ADDR 0x40470000 +#define GC_GLOBALSEC_BASE_ADDR 0x40090000 #define GC_GPIO0_BASE_ADDR 0x40200000 #define GC_GPIO1_BASE_ADDR 0x40210000 -#define GC_I2C0_BASE_ADDR 0x40520000 -#define GC_I2C1_BASE_ADDR 0x40530000 -#define GC_I2CS0_BASE_ADDR 0x40480000 +#define GC_I2C0_BASE_ADDR 0x40630000 +#define GC_I2C1_BASE_ADDR 0x40640000 +#define GC_I2CS0_BASE_ADDR 0x40530000 #define GC_MAU_BASE_ADDR 0x40080000 -#define GC_PAU_BASE_ADDR 0x40090000 #define GC_PINMUX_BASE_ADDR 0x40060000 #define GC_PMU_BASE_ADDR 0x40000000 #define GC_M3_BASE_ADDR 0xe0000000 -#define GC_RBOX0_BASE_ADDR 0x40460000 -#define GC_RTC0_BASE_ADDR 0x40400000 +#define GC_RBOX0_BASE_ADDR 0x40550000 +#define GC_RDD0_BASE_ADDR 0x40460000 +#define GC_RTC0_BASE_ADDR 0x400a0000 #define GC_SHA0_BASE_ADDR 0x40700000 -#define GC_SPI0_BASE_ADDR 0x40500000 +#define GC_SPI0_BASE_ADDR 0x40680000 +#define GC_SPI1_BASE_ADDR 0x40690000 #define GC_SPS0_BASE_ADDR 0x40510000 -#define GC_SWDP0_BASE_ADDR 0x40590000 -#define GC_TEMP0_BASE_ADDR 0x40490000 -#define GC_TIMEHS0_BASE_ADDR 0x40570000 -#define GC_TIMEHS1_BASE_ADDR 0x40580000 -#define GC_TIMELS0_BASE_ADDR 0x40430000 -#define GC_TRNG0_BASE_ADDR 0x404a0000 -#define GC_UART0_BASE_ADDR 0x40540000 -#define GC_UART1_BASE_ADDR 0x40550000 -#define GC_UART2_BASE_ADDR 0x40560000 +#define GC_SWDP0_BASE_ADDR 0x40520000 +#define GC_TEMP0_BASE_ADDR 0x40400000 +#define GC_TIMEHS0_BASE_ADDR 0x40650000 +#define GC_TIMEHS1_BASE_ADDR 0x40660000 +#define GC_TIMELS0_BASE_ADDR 0x40540000 +#define GC_TIMEUS0_BASE_ADDR 0x40670000 +#define GC_TRNG0_BASE_ADDR 0x40410000 +#define GC_UART0_BASE_ADDR 0x40600000 +#define GC_UART1_BASE_ADDR 0x40610000 +#define GC_UART2_BASE_ADDR 0x40620000 #define GC_USB0_BASE_ADDR 0x40300000 -#define GC_WATCHDOG0_BASE_ADDR 0x40410000 -#define GC_XO0_BASE_ADDR 0x40420000 -#define GC_AES_CTRL_OFFSET 0x0 +#define GC_VOLT0_BASE_ADDR 0x40480000 +#define GC_WATCHDOG0_BASE_ADDR 0x40500000 +#define GC_XO0_BASE_ADDR 0x400b0000 +#define GC_AES_VERSION_OFFSET 0x0 +#define GC_AES_VERSION_DEFAULT 0x401052c +#define GC_AES_CTRL_OFFSET 0x4 #define GC_AES_CTRL_DEFAULT 0x0 -#define GC_AES_B0_START_OFFSET 0x4 -#define GC_AES_B0_START_DEFAULT 0x0 -#define GC_AES_B0_DATA0_OFFSET 0x8 -#define GC_AES_B0_DATA0_DEFAULT 0x0 -#define GC_AES_B0_DATA1_OFFSET 0xc -#define GC_AES_B0_DATA1_DEFAULT 0x0 -#define GC_AES_B0_DATA2_OFFSET 0x10 -#define GC_AES_B0_DATA2_DEFAULT 0x0 -#define GC_AES_B0_DATA3_OFFSET 0x14 -#define GC_AES_B0_DATA3_DEFAULT 0x0 -#define GC_AES_B1_START_OFFSET 0x18 -#define GC_AES_B1_START_DEFAULT 0x0 -#define GC_AES_B1_DATA0_OFFSET 0x1c -#define GC_AES_B1_DATA0_DEFAULT 0x0 -#define GC_AES_B1_DATA1_OFFSET 0x20 -#define GC_AES_B1_DATA1_DEFAULT 0x0 -#define GC_AES_B1_DATA2_OFFSET 0x24 -#define GC_AES_B1_DATA2_DEFAULT 0x0 -#define GC_AES_B1_DATA3_OFFSET 0x28 -#define GC_AES_B1_DATA3_DEFAULT 0x0 +#define GC_AES_WFIFO_DATA_OFFSET 0x8 +#define GC_AES_WFIFO_DATA_DEFAULT 0xdeadbeef +#define GC_AES_RFIFO_DATA_OFFSET 0xc +#define GC_AES_RFIFO_DATA_DEFAULT 0xdeadbeef +#define GC_AES_HKEY_OFFSET 0x18 +#define GC_AES_HKEY_DEFAULT 0x0 +#define GC_AES_HKEY_READ_OFFSET 0x1c +#define GC_AES_HKEY_READ_DEFAULT 0x0 #define GC_AES_KEY0_OFFSET 0x2c #define GC_AES_KEY0_DEFAULT 0x0 #define GC_AES_KEY1_OFFSET 0x30 @@ -475,32 +606,278 @@ #define GC_AES_CTR2_DEFAULT 0x0 #define GC_AES_CTR3_OFFSET 0x5c #define GC_AES_CTR3_DEFAULT 0x0 -#define GC_AES_LFSR_CTL_OFFSET 0x60 -#define GC_AES_LFSR_CTL_DEFAULT 0x1f -#define GC_AES_VERSION_OFFSET 0x64 -#define GC_AES_VERSION_DEFAULT 0x800be5c +#define GC_AES_RAND_STALL_CTL_OFFSET 0x60 +#define GC_AES_RAND_STALL_CTL_DEFAULT 0x7 +#define GC_AES_WFIFO_LEVEL_OFFSET 0x64 +#define GC_AES_WFIFO_LEVEL_DEFAULT 0x0 +#define GC_AES_WFIFO_FULL_OFFSET 0x68 +#define GC_AES_WFIFO_FULL_DEFAULT 0x0 +#define GC_AES_RFIFO_LEVEL_OFFSET 0x6c +#define GC_AES_RFIFO_LEVEL_DEFAULT 0x0 +#define GC_AES_RFIFO_EMPTY_OFFSET 0x70 +#define GC_AES_RFIFO_EMPTY_DEFAULT 0x1 +#define GC_AES_EXECUTE_COUNT_STD_STATE_OFFSET 0x74 +#define GC_AES_EXECUTE_COUNT_STD_STATE_DEFAULT 0x0 +#define GC_AES_EXECUTE_COUNT_HKEY_STATE_OFFSET 0x78 +#define GC_AES_EXECUTE_COUNT_HKEY_STATE_DEFAULT 0x0 +#define GC_AES_EXECUTE_COUNT_STD_MAX_OFFSET 0x7c +#define GC_AES_EXECUTE_COUNT_STD_MAX_DEFAULT 0x0 +#define GC_AES_EXECUTE_COUNT_HKEY_MAX_OFFSET 0x80 +#define GC_AES_EXECUTE_COUNT_HKEY_MAX_DEFAULT 0x0 +#define GC_AES_GCM_LEN0_OFFSET 0x84 +#define GC_AES_GCM_LEN0_DEFAULT 0x0 +#define GC_AES_GCM_LEN1_OFFSET 0x88 +#define GC_AES_GCM_LEN1_DEFAULT 0x0 +#define GC_AES_GCM_LEN2_OFFSET 0x8c +#define GC_AES_GCM_LEN2_DEFAULT 0x0 +#define GC_AES_GCM_LEN3_OFFSET 0x90 +#define GC_AES_GCM_LEN3_DEFAULT 0x0 +#define GC_AES_GCM_EOP_MASK_OFFSET 0x94 +#define GC_AES_GCM_EOP_MASK_DEFAULT 0xffff +#define GC_AES_GCM_STATE_OFFSET 0x98 +#define GC_AES_GCM_STATE_DEFAULT 0x0 +#define GC_AES_GCM_H0_OFFSET 0x9c +#define GC_AES_GCM_H0_DEFAULT 0x0 +#define GC_AES_GCM_H1_OFFSET 0xa0 +#define GC_AES_GCM_H1_DEFAULT 0x0 +#define GC_AES_GCM_H2_OFFSET 0xa4 +#define GC_AES_GCM_H2_DEFAULT 0x0 +#define GC_AES_GCM_H3_OFFSET 0xa8 +#define GC_AES_GCM_H3_DEFAULT 0x0 +#define GC_AES_GCM_E0_OFFSET 0xac +#define GC_AES_GCM_E0_DEFAULT 0x0 +#define GC_AES_GCM_E1_OFFSET 0xb0 +#define GC_AES_GCM_E1_DEFAULT 0x0 +#define GC_AES_GCM_E2_OFFSET 0xb4 +#define GC_AES_GCM_E2_DEFAULT 0x0 +#define GC_AES_GCM_E3_OFFSET 0xb8 +#define GC_AES_GCM_E3_DEFAULT 0x0 +#define GC_AES_GCM_TAG0_OFFSET 0xbc +#define GC_AES_GCM_TAG0_DEFAULT 0x0 +#define GC_AES_GCM_TAG1_OFFSET 0xc0 +#define GC_AES_GCM_TAG1_DEFAULT 0x0 +#define GC_AES_GCM_TAG2_OFFSET 0xc4 +#define GC_AES_GCM_TAG2_DEFAULT 0x0 +#define GC_AES_GCM_TAG3_OFFSET 0xc8 +#define GC_AES_GCM_TAG3_DEFAULT 0x0 +#define GC_AES_WIPE_SECRETS_OFFSET 0xcc +#define GC_AES_WIPE_SECRETS_DEFAULT 0x0 +#define GC_AES_DAES_INT_ENABLE_OFFSET 0xd0 +#define GC_AES_DAES_INT_ENABLE_DEFAULT 0x0 +#define GC_AES_DAES_INT_STATE_OFFSET 0xd4 +#define GC_AES_DAES_INT_STATE_DEFAULT 0x0 +#define GC_AES_DAES_INT_TEST_OFFSET 0xd8 +#define GC_AES_DAES_INT_TEST_DEFAULT 0x0 #define GC_CAMO_CLKPERIOD_X256_OFFSET 0x0 #define GC_CAMO_CLKPERIOD_X256_DEFAULT 0x4 #define GC_CAMO_RESTART_PRBS_OFFSET 0x4 #define GC_CAMO_RESTART_PRBS_DEFAULT 0x0 -#define GC_CAMO_INT_ENABLE_OFFSET 0x8 -#define GC_CAMO_INT_ENABLE_DEFAULT 0x0 -#define GC_CAMO_INT_STATE_OFFSET 0xc -#define GC_CAMO_INT_STATE_DEFAULT 0x0 -#define GC_CAMO_INT_TEST_OFFSET 0x10 -#define GC_CAMO_INT_TEST_DEFAULT 0x0 -#define GC_CAMO_BREACH_COUNT_OFFSET 0x14 +#define GC_CAMO_BREACH_COUNT_OFFSET 0x8 #define GC_CAMO_BREACH_COUNT_DEFAULT 0x0 -#define GC_CAMO_CUR_VAL0_OFFSET 0x18 -#define GC_CAMO_CUR_VAL0_DEFAULT 0x0 -#define GC_CAMO_CUR_VAL1_OFFSET 0x1c -#define GC_CAMO_CUR_VAL1_DEFAULT 0x0 -#define GC_CAMO_CUR_VAL2_OFFSET 0x20 -#define GC_CAMO_CUR_VAL2_DEFAULT 0x0 -#define GC_CAMO_CUR_VAL3_OFFSET 0x24 -#define GC_CAMO_CUR_VAL3_DEFAULT 0x0 -#define GC_CAMO_VERSION_OFFSET 0x28 -#define GC_CAMO_VERSION_DEFAULT 0x500ba73 +#define GC_CAMO_CLEAR_COUNTER_OFFSET 0xc +#define GC_CAMO_CLEAR_COUNTER_DEFAULT 0x0 +#define GC_CAMO_VERSION_OFFSET 0x10 +#define GC_CAMO_VERSION_DEFAULT 0x200e1a1 +#define GC_CRYPTO_VERSION_OFFSET 0x0 +#define GC_CRYPTO_VERSION_DEFAULT 0x230105b6 +#define GC_CRYPTO_CONTROL_OFFSET 0x4 +#define GC_CRYPTO_CONTROL_DEFAULT 0x0 +#define GC_CRYPTO_CONFIG_OFFSET 0x8 +#define GC_CRYPTO_CONFIG_DEFAULT 0x10 +#define GC_CRYPTO_IMEM_SCRUB_RANGE_OFFSET 0xc +#define GC_CRYPTO_IMEM_SCRUB_RANGE_DEFAULT 0x3ff +#define GC_CRYPTO_DMEM_SCRUB_RANGE_OFFSET 0x10 +#define GC_CRYPTO_DMEM_SCRUB_RANGE_DEFAULT 0x7f +#define GC_CRYPTO_INT_ENABLE_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_DEFAULT 0x0 +#define GC_CRYPTO_HOST_CMD_OFFSET 0x20 +#define GC_CRYPTO_HOST_CMD_DEFAULT 0xffffffff +#define GC_CRYPTO_INSTR_OFFSET 0x24 +#define GC_CRYPTO_INSTR_DEFAULT 0x0 +#define GC_CRYPTO_STATUS_OFFSET 0x28 +#define GC_CRYPTO_STATUS_DEFAULT 0x0 +#define GC_CRYPTO_AUX_CC_OFFSET 0x2c +#define GC_CRYPTO_AUX_CC_DEFAULT 0x0 +#define GC_CRYPTO_RAND_STALL_CTL_OFFSET 0x30 +#define GC_CRYPTO_RAND_STALL_CTL_DEFAULT 0x5 +#define GC_CRYPTO_IMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x34 +#define GC_CRYPTO_IMEM_PARITY_ERRS_CTR_STATE_DEFAULT 0x0 +#define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x38 +#define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_DEFAULT 0x0 +#define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_OFFSET 0x3c +#define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_DEFAULT 0x0 +#define GC_CRYPTO_IMEM_PARITY_CFG_OFFSET 0x40 +#define GC_CRYPTO_IMEM_PARITY_CFG_DEFAULT 0x0 +#define GC_CRYPTO_DMEM_PARITY_CFG_OFFSET 0x44 +#define GC_CRYPTO_DMEM_PARITY_CFG_DEFAULT 0x0 +#define GC_CRYPTO_DRF_PARITY_CFG_OFFSET 0x48 +#define GC_CRYPTO_DRF_PARITY_CFG_DEFAULT 0x0 +#define GC_CRYPTO_PGM_LFSR_OFFSET 0x4c +#define GC_CRYPTO_PGM_LFSR_DEFAULT 0x0 +#define GC_CRYPTO_DEBUG_BRKPT0_OFFSET 0x50 +#define GC_CRYPTO_DEBUG_BRKPT0_DEFAULT 0x0 +#define GC_CRYPTO_DEBUG_BRKPT1_OFFSET 0x54 +#define GC_CRYPTO_DEBUG_BRKPT1_DEFAULT 0x0 +#define GC_CRYPTO_WIPE_SECRETS_OFFSET 0x58 +#define GC_CRYPTO_WIPE_SECRETS_DEFAULT 0x0 +#define GC_CRYPTO_DMEM_DUMMY_OFFSET 0x4000 +#define GC_CRYPTO_IMEM_DUMMY_OFFSET 0x8000 +#define GC_DMA_VERSION_OFFSET 0x0 +#define GC_DMA_VERSION_DEFAULT 0xf010532 +#define GC_DMA_INT_ENABLE_OFFSET 0x4 +#define GC_DMA_INT_ENABLE_DEFAULT 0x0 +#define GC_DMA_INT_STATE_OFFSET 0x8 +#define GC_DMA_INT_STATE_DEFAULT 0x0 +#define GC_DMA_INT_TEST_OFFSET 0xc +#define GC_DMA_INT_TEST_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_DEFAULT 0x28 +#define GC_DMA_SRC_ADDR_CHAN0_OFFSET 0x104 +#define GC_DMA_SRC_ADDR_CHAN0_DEFAULT 0x0 +#define GC_DMA_DST_ADDR_CHAN0_OFFSET 0x108 +#define GC_DMA_DST_ADDR_CHAN0_DEFAULT 0x0 +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x10c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN0_DEFAULT 0x3ff +#define GC_DMA_PROG_COUNT_CHAN0_OFFSET 0x110 +#define GC_DMA_PROG_COUNT_CHAN0_DEFAULT 0x0 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x114 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_DEFAULT 0x0 +#define GC_DMA_RETRY_WAIT_TIME_CHAN0_OFFSET 0x118 +#define GC_DMA_RETRY_WAIT_TIME_CHAN0_DEFAULT 0x80 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_OFFSET 0x11c +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_DEFAULT 0x64 +#define GC_DMA_FSM_STATE_CHAN0_OFFSET 0x120 +#define GC_DMA_FSM_STATE_CHAN0_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN1_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_DEFAULT 0x28 +#define GC_DMA_SRC_ADDR_CHAN1_OFFSET 0x204 +#define GC_DMA_SRC_ADDR_CHAN1_DEFAULT 0x0 +#define GC_DMA_DST_ADDR_CHAN1_OFFSET 0x208 +#define GC_DMA_DST_ADDR_CHAN1_DEFAULT 0x0 +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x20c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN1_DEFAULT 0x3ff +#define GC_DMA_PROG_COUNT_CHAN1_OFFSET 0x210 +#define GC_DMA_PROG_COUNT_CHAN1_DEFAULT 0x0 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x214 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_DEFAULT 0x0 +#define GC_DMA_RETRY_WAIT_TIME_CHAN1_OFFSET 0x218 +#define GC_DMA_RETRY_WAIT_TIME_CHAN1_DEFAULT 0x80 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_OFFSET 0x21c +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_DEFAULT 0x64 +#define GC_DMA_FSM_STATE_CHAN1_OFFSET 0x220 +#define GC_DMA_FSM_STATE_CHAN1_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN2_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_DEFAULT 0x28 +#define GC_DMA_SRC_ADDR_CHAN2_OFFSET 0x304 +#define GC_DMA_SRC_ADDR_CHAN2_DEFAULT 0x0 +#define GC_DMA_DST_ADDR_CHAN2_OFFSET 0x308 +#define GC_DMA_DST_ADDR_CHAN2_DEFAULT 0x0 +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x30c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN2_DEFAULT 0x3ff +#define GC_DMA_PROG_COUNT_CHAN2_OFFSET 0x310 +#define GC_DMA_PROG_COUNT_CHAN2_DEFAULT 0x0 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x314 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_DEFAULT 0x0 +#define GC_DMA_RETRY_WAIT_TIME_CHAN2_OFFSET 0x318 +#define GC_DMA_RETRY_WAIT_TIME_CHAN2_DEFAULT 0x80 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_OFFSET 0x31c +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_DEFAULT 0x64 +#define GC_DMA_FSM_STATE_CHAN2_OFFSET 0x320 +#define GC_DMA_FSM_STATE_CHAN2_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN3_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_DEFAULT 0x28 +#define GC_DMA_SRC_ADDR_CHAN3_OFFSET 0x404 +#define GC_DMA_SRC_ADDR_CHAN3_DEFAULT 0x0 +#define GC_DMA_DST_ADDR_CHAN3_OFFSET 0x408 +#define GC_DMA_DST_ADDR_CHAN3_DEFAULT 0x0 +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x40c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN3_DEFAULT 0x3ff +#define GC_DMA_PROG_COUNT_CHAN3_OFFSET 0x410 +#define GC_DMA_PROG_COUNT_CHAN3_DEFAULT 0x0 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x414 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_DEFAULT 0x0 +#define GC_DMA_RETRY_WAIT_TIME_CHAN3_OFFSET 0x418 +#define GC_DMA_RETRY_WAIT_TIME_CHAN3_DEFAULT 0x80 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_OFFSET 0x41c +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_DEFAULT 0x64 +#define GC_DMA_FSM_STATE_CHAN3_OFFSET 0x420 +#define GC_DMA_FSM_STATE_CHAN3_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN4_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_DEFAULT 0x28 +#define GC_DMA_SRC_ADDR_CHAN4_OFFSET 0x504 +#define GC_DMA_SRC_ADDR_CHAN4_DEFAULT 0x0 +#define GC_DMA_DST_ADDR_CHAN4_OFFSET 0x508 +#define GC_DMA_DST_ADDR_CHAN4_DEFAULT 0x0 +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x50c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN4_DEFAULT 0x3ff +#define GC_DMA_PROG_COUNT_CHAN4_OFFSET 0x510 +#define GC_DMA_PROG_COUNT_CHAN4_DEFAULT 0x0 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x514 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_DEFAULT 0x0 +#define GC_DMA_RETRY_WAIT_TIME_CHAN4_OFFSET 0x518 +#define GC_DMA_RETRY_WAIT_TIME_CHAN4_DEFAULT 0x80 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_OFFSET 0x51c +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_DEFAULT 0x64 +#define GC_DMA_FSM_STATE_CHAN4_OFFSET 0x520 +#define GC_DMA_FSM_STATE_CHAN4_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN5_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_DEFAULT 0x28 +#define GC_DMA_SRC_ADDR_CHAN5_OFFSET 0x604 +#define GC_DMA_SRC_ADDR_CHAN5_DEFAULT 0x0 +#define GC_DMA_DST_ADDR_CHAN5_OFFSET 0x608 +#define GC_DMA_DST_ADDR_CHAN5_DEFAULT 0x0 +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x60c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN5_DEFAULT 0x3ff +#define GC_DMA_PROG_COUNT_CHAN5_OFFSET 0x610 +#define GC_DMA_PROG_COUNT_CHAN5_DEFAULT 0x0 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x614 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_DEFAULT 0x0 +#define GC_DMA_RETRY_WAIT_TIME_CHAN5_OFFSET 0x618 +#define GC_DMA_RETRY_WAIT_TIME_CHAN5_DEFAULT 0x80 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_OFFSET 0x61c +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_DEFAULT 0x64 +#define GC_DMA_FSM_STATE_CHAN5_OFFSET 0x620 +#define GC_DMA_FSM_STATE_CHAN5_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN6_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_DEFAULT 0x28 +#define GC_DMA_SRC_ADDR_CHAN6_OFFSET 0x704 +#define GC_DMA_SRC_ADDR_CHAN6_DEFAULT 0x0 +#define GC_DMA_DST_ADDR_CHAN6_OFFSET 0x708 +#define GC_DMA_DST_ADDR_CHAN6_DEFAULT 0x0 +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x70c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN6_DEFAULT 0x3ff +#define GC_DMA_PROG_COUNT_CHAN6_OFFSET 0x710 +#define GC_DMA_PROG_COUNT_CHAN6_DEFAULT 0x0 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x714 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_DEFAULT 0x0 +#define GC_DMA_RETRY_WAIT_TIME_CHAN6_OFFSET 0x718 +#define GC_DMA_RETRY_WAIT_TIME_CHAN6_DEFAULT 0x80 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_OFFSET 0x71c +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_DEFAULT 0x64 +#define GC_DMA_FSM_STATE_CHAN6_OFFSET 0x720 +#define GC_DMA_FSM_STATE_CHAN6_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN7_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_DEFAULT 0x28 +#define GC_DMA_SRC_ADDR_CHAN7_OFFSET 0x804 +#define GC_DMA_SRC_ADDR_CHAN7_DEFAULT 0x0 +#define GC_DMA_DST_ADDR_CHAN7_OFFSET 0x808 +#define GC_DMA_DST_ADDR_CHAN7_DEFAULT 0x0 +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x80c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN7_DEFAULT 0x3ff +#define GC_DMA_PROG_COUNT_CHAN7_OFFSET 0x810 +#define GC_DMA_PROG_COUNT_CHAN7_DEFAULT 0x0 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x814 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_DEFAULT 0x0 +#define GC_DMA_RETRY_WAIT_TIME_CHAN7_OFFSET 0x818 +#define GC_DMA_RETRY_WAIT_TIME_CHAN7_DEFAULT 0x80 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_OFFSET 0x81c +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_DEFAULT 0x64 +#define GC_DMA_FSM_STATE_CHAN7_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_DEFAULT 0x1 #define GC_FLASH_FSH_PE_CONTROL0_OFFSET 0x0 #define GC_FLASH_FSH_PE_CONTROL0_DEFAULT 0x0 #define GC_FLASH_FSH_PE_CONTROL0_PROG 0x27182818 @@ -700,6 +1077,732 @@ #define GC_FLASH_FSH_ITCR_DEFAULT 0x0 #define GC_FLASH_FSH_ITOP_OFFSET 0xf04 #define GC_FLASH_FSH_ITOP_DEFAULT 0x0 +#define GC_FUSE_STATUS_OFFSET 0x0 +#define GC_FUSE_STATUS_DEFAULT 0x0 +#define GC_FUSE_STATUS_CLR_OFFSET 0x4 +#define GC_FUSE_STATUS_CLR_DEFAULT 0x0 +#define GC_FUSE_READ_START_OFFSET 0x8 +#define GC_FUSE_READ_START_DEFAULT 0x0 +#define GC_FUSE_READ_START_ENABLE 0x0 +#define GC_FUSE_READ_START_DISABLE 0x0 +#define GC_FUSE_WRITE_START_OFFSET 0xc +#define GC_FUSE_WRITE_START_DEFAULT 0x0 +#define GC_FUSE_WRITE_START_ENABLE 0x0 +#define GC_FUSE_WRITE_START_DISABLE 0x0 +#define GC_FUSE_SCRUB_LFSR_OFFSET 0x10 +#define GC_FUSE_SCRUB_LFSR_DEFAULT 0x0 +#define GC_FUSE_SCRUB_CTRL_OFFSET 0x14 +#define GC_FUSE_SCRUB_CTRL_DEFAULT 0xffff +#define GC_FUSE_ERROR_INJECTION_OFFSET 0x18 +#define GC_FUSE_ERROR_INJECTION_DEFAULT 0x0 +#define GC_FUSE_VDDQ_RAMP_TIMING_OFFSET 0x1c +#define GC_FUSE_VDDQ_RAMP_TIMING_DEFAULT 0x1d4c0 +#define GC_FUSE_VERSION_OFFSET 0x20 +#define GC_FUSE_VERSION_DEFAULT 0x3010240 +#define GC_FUSE_INT_ENABLE_OFFSET 0x24 +#define GC_FUSE_INT_ENABLE_DEFAULT 0x0 +#define GC_FUSE_INT_STATE_OFFSET 0x28 +#define GC_FUSE_INT_STATE_DEFAULT 0x0 +#define GC_FUSE_INT_TEST_OFFSET 0x2c +#define GC_FUSE_INT_TEST_DEFAULT 0x0 +#define GC_FUSE_DS_GRP0_OFFSET 0x30 +#define GC_FUSE_DS_GRP0_DEFAULT 0x0 +#define GC_FUSE_DS_GRP1_OFFSET 0x34 +#define GC_FUSE_DS_GRP1_DEFAULT 0x0 +#define GC_FUSE_DS_GRP2_OFFSET 0x38 +#define GC_FUSE_DS_GRP2_DEFAULT 0x0 +#define GC_FUSE_DEV_ID0_OFFSET 0x3c +#define GC_FUSE_DEV_ID0_DEFAULT 0x0 +#define GC_FUSE_DEV_ID1_OFFSET 0x40 +#define GC_FUSE_DEV_ID1_DEFAULT 0x0 +#define GC_FUSE_BNK0_INTG_N_WR_LOCK_OFFSET 0x44 +#define GC_FUSE_BNK0_INTG_N_WR_LOCK_DEFAULT 0x0 +#define GC_FUSE_BNK0_INTG_CHKSUM_OFFSET 0x48 +#define GC_FUSE_BNK0_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_LB0_POST_OVRD_OFFSET 0x4c +#define GC_FUSE_LB0_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_LB0_POST_PATCNT_OFFSET 0x50 +#define GC_FUSE_LB0_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_OFFSET 0x54 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_LB0_POST_WARMUP_CNT_OFFSET 0x58 +#define GC_FUSE_LB0_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_LB1_POST_OVRD_OFFSET 0x5c +#define GC_FUSE_LB1_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_LB1_POST_PATCNT_OFFSET 0x60 +#define GC_FUSE_LB1_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_OFFSET 0x64 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_LB1_POST_WARMUP_CNT_OFFSET 0x68 +#define GC_FUSE_LB1_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_LB2_POST_OVRD_OFFSET 0x6c +#define GC_FUSE_LB2_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_LB2_POST_PATCNT_OFFSET 0x70 +#define GC_FUSE_LB2_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_OFFSET 0x74 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_LB2_POST_WARMUP_CNT_OFFSET 0x78 +#define GC_FUSE_LB2_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_LB3_POST_OVRD_OFFSET 0x7c +#define GC_FUSE_LB3_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_LB3_POST_PATCNT_OFFSET 0x80 +#define GC_FUSE_LB3_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_OFFSET 0x84 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_LB3_POST_WARMUP_CNT_OFFSET 0x88 +#define GC_FUSE_LB3_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_MBIST_POST_SEQ_OFFSET 0x8c +#define GC_FUSE_MBIST_POST_SEQ_DEFAULT 0x0 +#define GC_FUSE_LBIST_POST_SEQ_OFFSET 0x90 +#define GC_FUSE_LBIST_POST_SEQ_DEFAULT 0x0 +#define GC_FUSE_LBIST_VIA_TAP_DIS_OFFSET 0x94 +#define GC_FUSE_LBIST_VIA_TAP_DIS_DEFAULT 0x0 +#define GC_FUSE_MBIST_VIA_TAP_DIS_OFFSET 0x98 +#define GC_FUSE_MBIST_VIA_TAP_DIS_DEFAULT 0x0 +#define GC_FUSE_TAP_DISABLE_OFFSET 0x9c +#define GC_FUSE_TAP_DISABLE_DEFAULT 0x0 +#define GC_FUSE_RNGBIST_AR_EN_OFFSET 0xa0 +#define GC_FUSE_RNGBIST_AR_EN_DEFAULT 0x0 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0xa4 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x0 +#define GC_FUSE_BOOT_MODE_CFG_OFFSET 0xa8 +#define GC_FUSE_BOOT_MODE_CFG_DEFAULT 0x0 +#define GC_FUSE_TESTMODE_KEYS_EN_OFFSET 0xac +#define GC_FUSE_TESTMODE_KEYS_EN_DEFAULT 0x0 +#define GC_FUSE_PKG_ID_OFFSET 0xb0 +#define GC_FUSE_PKG_ID_DEFAULT 0x0 +#define GC_FUSE_BIN_ID_OFFSET 0xb4 +#define GC_FUSE_BIN_ID_DEFAULT 0x0 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_OFFSET 0xb8 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_OFFSET 0xbc +#define GC_FUSE_RC_JTR_OSC48_CC_EN_DEFAULT 0x0 +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_OFFSET 0xc0 +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_OFFSET 0xc4 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_DEFAULT 0x0 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_OFFSET 0xc8 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_OFFSET 0xcc +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_DEFAULT 0x0 +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_OFFSET 0xd0 +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x0 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_OFFSET 0xd4 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_DEFAULT 0x0 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_OFFSET 0xd8 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_OFFSET 0xdc +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_DEFAULT 0x0 +#define GC_FUSE_SEL_VREG_REG_EN_OFFSET 0xe0 +#define GC_FUSE_SEL_VREG_REG_EN_DEFAULT 0x0 +#define GC_FUSE_SEL_VREF_REG_OFFSET 0xe4 +#define GC_FUSE_SEL_VREF_REG_DEFAULT 0x0 +#define GC_FUSE_SEL_VREF_BATMON_EN_OFFSET 0xe8 +#define GC_FUSE_SEL_VREF_BATMON_EN_DEFAULT 0x0 +#define GC_FUSE_SEL_VREF_BATMON_OFFSET 0xec +#define GC_FUSE_SEL_VREF_BATMON_DEFAULT 0x0 +#define GC_FUSE_X_OSC_LDO_CTRL_EN_OFFSET 0xf0 +#define GC_FUSE_X_OSC_LDO_CTRL_EN_DEFAULT 0x0 +#define GC_FUSE_X_OSC_LDO_CTRL_OFFSET 0xf4 +#define GC_FUSE_X_OSC_LDO_CTRL_DEFAULT 0x0 +#define GC_FUSE_EXT_XTAL_PDB_OFFSET 0xf8 +#define GC_FUSE_EXT_XTAL_PDB_DEFAULT 0x0 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_OFFSET 0xfc +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x0 +#define GC_FUSE_HIK_CREATE_LOCK_OFFSET 0x100 +#define GC_FUSE_HIK_CREATE_LOCK_DEFAULT 0x0 +#define GC_FUSE_BNK1_INTG_N_WR_LOCK_OFFSET 0x104 +#define GC_FUSE_BNK1_INTG_N_WR_LOCK_DEFAULT 0x0 +#define GC_FUSE_BNK1_INTG_CHKSUM_OFFSET 0x108 +#define GC_FUSE_BNK1_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_TESTMODE_OTPW_DIS_OFFSET 0x10c +#define GC_FUSE_TESTMODE_OTPW_DIS_DEFAULT 0x0 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_OFFSET 0x110 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_DEFAULT 0x0 +#define GC_FUSE_FLASH_BASED_FUSE_LOCK_OFFSET 0x114 +#define GC_FUSE_FLASH_BASED_FUSE_LOCK_DEFAULT 0x0 +#define GC_FUSE_ALERT_RSP_CFG_OFFSET 0x118 +#define GC_FUSE_ALERT_RSP_CFG_DEFAULT 0x0 +#define GC_FUSE_BNK2_INTG_LOCK_OFFSET 0x11c +#define GC_FUSE_BNK2_INTG_LOCK_DEFAULT 0x0 +#define GC_FUSE_BNK2_INTG_CHKSUM_OFFSET 0x120 +#define GC_FUSE_BNK2_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_OFFSET 0x124 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK1_OFFSET 0x128 +#define GC_FUSE_FW_DEFINED_DATA_BLK1_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK2_OFFSET 0x12c +#define GC_FUSE_FW_DEFINED_DATA_BLK2_DEFAULT 0x0 +#define GC_FUSE_BNK3_INTG_LOCK_OFFSET 0x130 +#define GC_FUSE_BNK3_INTG_LOCK_DEFAULT 0x0 +#define GC_FUSE_BNK3_INTG_CHKSUM_OFFSET 0x134 +#define GC_FUSE_BNK3_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_RBOX_CLK10HZ_COUNT_OFFSET 0x138 +#define GC_FUSE_RBOX_CLK10HZ_COUNT_DEFAULT 0x0 +#define GC_FUSE_RBOX_DELAY5MS_COUNT_OFFSET 0x13c +#define GC_FUSE_RBOX_DELAY5MS_COUNT_DEFAULT 0x0 +#define GC_FUSE_RBOX_DELAY5SEC_COUNT_OFFSET 0x140 +#define GC_FUSE_RBOX_DELAY5SEC_COUNT_DEFAULT 0x0 +#define GC_FUSE_RBOX_DEBOUNCE_OFFSET 0x144 +#define GC_FUSE_RBOX_DEBOUNCE_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_OFFSET 0x148 +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_OFFSET 0x14c +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_OFFSET 0x150 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_OFFSET 0x154 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_OFFSET 0x158 +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_OFFSET 0x15c +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY0_OFFSET 0x160 +#define GC_FUSE_RBOX_BLOCK_KEY0_DEFAULT 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY1_OFFSET 0x164 +#define GC_FUSE_RBOX_BLOCK_KEY1_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_AC_PRESENT_OFFSET 0x168 +#define GC_FUSE_RBOX_POL_AC_PRESENT_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_PWRB_IN_OFFSET 0x16c +#define GC_FUSE_RBOX_POL_PWRB_IN_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_PWRB_OUT_OFFSET 0x170 +#define GC_FUSE_RBOX_POL_PWRB_OUT_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_KEY0_IN_OFFSET 0x174 +#define GC_FUSE_RBOX_POL_KEY0_IN_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_KEY0_OUT_OFFSET 0x178 +#define GC_FUSE_RBOX_POL_KEY0_OUT_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_KEY1_IN_OFFSET 0x17c +#define GC_FUSE_RBOX_POL_KEY1_IN_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_KEY1_OUT_OFFSET 0x180 +#define GC_FUSE_RBOX_POL_KEY1_OUT_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_OFFSET 0x184 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_PWRB_IN_OFFSET 0x188 +#define GC_FUSE_RBOX_TERM_PWRB_IN_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_OFFSET 0x18c +#define GC_FUSE_RBOX_TERM_PWRB_OUT_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_KEY0_IN_OFFSET 0x190 +#define GC_FUSE_RBOX_TERM_KEY0_IN_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_KEY0_OUT_OFFSET 0x194 +#define GC_FUSE_RBOX_TERM_KEY0_OUT_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_KEY1_IN_OFFSET 0x198 +#define GC_FUSE_RBOX_TERM_KEY1_IN_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_OFFSET 0x19c +#define GC_FUSE_RBOX_TERM_KEY1_OUT_DEFAULT 0x0 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_OFFSET 0x1a0 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x0 +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_OFFSET 0x1a4 +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x0 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_OFFSET 0x1a8 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_DS_GRP0_OFFSET 0x1ac +#define GC_FUSE_WRITE_SHADOW_DS_GRP0_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_DS_GRP1_OFFSET 0x1b0 +#define GC_FUSE_WRITE_SHADOW_DS_GRP1_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_DS_GRP2_OFFSET 0x1b4 +#define GC_FUSE_WRITE_SHADOW_DS_GRP2_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_DEV_ID0_OFFSET 0x1b8 +#define GC_FUSE_WRITE_SHADOW_DEV_ID0_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_DEV_ID1_OFFSET 0x1bc +#define GC_FUSE_WRITE_SHADOW_DEV_ID1_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BNK0_INTG_N_WR_LOCK_OFFSET 0x1c0 +#define GC_FUSE_WRITE_SHADOW_BNK0_INTG_N_WR_LOCK_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BNK0_INTG_CHKSUM_OFFSET 0x1c4 +#define GC_FUSE_WRITE_SHADOW_BNK0_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB0_POST_OVRD_OFFSET 0x1c8 +#define GC_FUSE_WRITE_SHADOW_LB0_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB0_POST_PATCNT_OFFSET 0x1cc +#define GC_FUSE_WRITE_SHADOW_LB0_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB0_POST_WARMUP_OVRD_OFFSET 0x1d0 +#define GC_FUSE_WRITE_SHADOW_LB0_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB0_POST_WARMUP_CNT_OFFSET 0x1d4 +#define GC_FUSE_WRITE_SHADOW_LB0_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB1_POST_OVRD_OFFSET 0x1d8 +#define GC_FUSE_WRITE_SHADOW_LB1_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB1_POST_PATCNT_OFFSET 0x1dc +#define GC_FUSE_WRITE_SHADOW_LB1_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB1_POST_WARMUP_OVRD_OFFSET 0x1e0 +#define GC_FUSE_WRITE_SHADOW_LB1_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB1_POST_WARMUP_CNT_OFFSET 0x1e4 +#define GC_FUSE_WRITE_SHADOW_LB1_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB2_POST_OVRD_OFFSET 0x1e8 +#define GC_FUSE_WRITE_SHADOW_LB2_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB2_POST_PATCNT_OFFSET 0x1ec +#define GC_FUSE_WRITE_SHADOW_LB2_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB2_POST_WARMUP_OVRD_OFFSET 0x1f0 +#define GC_FUSE_WRITE_SHADOW_LB2_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB2_POST_WARMUP_CNT_OFFSET 0x1f4 +#define GC_FUSE_WRITE_SHADOW_LB2_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB3_POST_OVRD_OFFSET 0x1f8 +#define GC_FUSE_WRITE_SHADOW_LB3_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB3_POST_PATCNT_OFFSET 0x1fc +#define GC_FUSE_WRITE_SHADOW_LB3_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB3_POST_WARMUP_OVRD_OFFSET 0x200 +#define GC_FUSE_WRITE_SHADOW_LB3_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LB3_POST_WARMUP_CNT_OFFSET 0x204 +#define GC_FUSE_WRITE_SHADOW_LB3_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_MBIST_POST_SEQ_OFFSET 0x208 +#define GC_FUSE_WRITE_SHADOW_MBIST_POST_SEQ_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LBIST_POST_SEQ_OFFSET 0x20c +#define GC_FUSE_WRITE_SHADOW_LBIST_POST_SEQ_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_LBIST_VIA_TAP_DIS_OFFSET 0x210 +#define GC_FUSE_WRITE_SHADOW_LBIST_VIA_TAP_DIS_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_MBIST_VIA_TAP_DIS_OFFSET 0x214 +#define GC_FUSE_WRITE_SHADOW_MBIST_VIA_TAP_DIS_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_TAP_DISABLE_OFFSET 0x218 +#define GC_FUSE_WRITE_SHADOW_TAP_DISABLE_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RNGBIST_AR_EN_OFFSET 0x21c +#define GC_FUSE_WRITE_SHADOW_RNGBIST_AR_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x220 +#define GC_FUSE_WRITE_SHADOW_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BOOT_MODE_CFG_OFFSET 0x224 +#define GC_FUSE_WRITE_SHADOW_BOOT_MODE_CFG_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_TESTMODE_KEYS_EN_OFFSET 0x228 +#define GC_FUSE_WRITE_SHADOW_TESTMODE_KEYS_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_PKG_ID_OFFSET 0x22c +#define GC_FUSE_WRITE_SHADOW_PKG_ID_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BIN_ID_OFFSET 0x230 +#define GC_FUSE_WRITE_SHADOW_BIN_ID_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC48_CC_TRIM_OFFSET 0x234 +#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC48_CC_EN_OFFSET 0x238 +#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC48_CC_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC60_CC_TRIM_OFFSET 0x23c +#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC60_CC_EN_OFFSET 0x240 +#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC60_CC_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_CC_TRIM_OFFSET 0x244 +#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_CC_EN_OFFSET 0x248 +#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_CC_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_FC_TRIM_OFFSET 0x24c +#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_FC_EN_OFFSET 0x250 +#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_FC_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_RTC_OSC32K_CC_TRIM_OFFSET 0x254 +#define GC_FUSE_WRITE_SHADOW_RC_RTC_OSC32K_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RC_RTC_OSC32K_CC_EN_OFFSET 0x258 +#define GC_FUSE_WRITE_SHADOW_RC_RTC_OSC32K_CC_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_SEL_VREG_REG_EN_OFFSET 0x25c +#define GC_FUSE_WRITE_SHADOW_SEL_VREG_REG_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_SEL_VREF_REG_OFFSET 0x260 +#define GC_FUSE_WRITE_SHADOW_SEL_VREF_REG_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_SEL_VREF_BATMON_EN_OFFSET 0x264 +#define GC_FUSE_WRITE_SHADOW_SEL_VREF_BATMON_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_SEL_VREF_BATMON_OFFSET 0x268 +#define GC_FUSE_WRITE_SHADOW_SEL_VREF_BATMON_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_X_OSC_LDO_CTRL_EN_OFFSET 0x26c +#define GC_FUSE_WRITE_SHADOW_X_OSC_LDO_CTRL_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_X_OSC_LDO_CTRL_OFFSET 0x270 +#define GC_FUSE_WRITE_SHADOW_X_OSC_LDO_CTRL_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_EXT_XTAL_PDB_OFFSET 0x274 +#define GC_FUSE_WRITE_SHADOW_EXT_XTAL_PDB_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_DIS_EXT_XTAL_CLK_TREE_OFFSET 0x278 +#define GC_FUSE_WRITE_SHADOW_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_OBS0_OFFSET 0x27c +#define GC_FUSE_WRITE_SHADOW_OBS0_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_OBS1_OFFSET 0x280 +#define GC_FUSE_WRITE_SHADOW_OBS1_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_OBS2_OFFSET 0x284 +#define GC_FUSE_WRITE_SHADOW_OBS2_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_OBS3_OFFSET 0x288 +#define GC_FUSE_WRITE_SHADOW_OBS3_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_OBS4_OFFSET 0x28c +#define GC_FUSE_WRITE_SHADOW_OBS4_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_OBS5_OFFSET 0x290 +#define GC_FUSE_WRITE_SHADOW_OBS5_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_OBS6_OFFSET 0x294 +#define GC_FUSE_WRITE_SHADOW_OBS6_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_OBS7_OFFSET 0x298 +#define GC_FUSE_WRITE_SHADOW_OBS7_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_HIK_CREATE_LOCK_OFFSET 0x29c +#define GC_FUSE_WRITE_SHADOW_HIK_CREATE_LOCK_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BNK1_INTG_N_WR_LOCK_OFFSET 0x2a0 +#define GC_FUSE_WRITE_SHADOW_BNK1_INTG_N_WR_LOCK_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BNK1_INTG_CHKSUM_OFFSET 0x2a4 +#define GC_FUSE_WRITE_SHADOW_BNK1_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_TESTMODE_OTPW_DIS_OFFSET 0x2a8 +#define GC_FUSE_WRITE_SHADOW_TESTMODE_OTPW_DIS_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_HKEY_WDOG_TIMER_EN_OFFSET 0x2ac +#define GC_FUSE_WRITE_SHADOW_HKEY_WDOG_TIMER_EN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_FLASH_BASED_FUSE_LOCK_OFFSET 0x2b0 +#define GC_FUSE_WRITE_SHADOW_FLASH_BASED_FUSE_LOCK_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_ALERT_RSP_CFG_OFFSET 0x2b4 +#define GC_FUSE_WRITE_SHADOW_ALERT_RSP_CFG_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BNK2_INTG_LOCK_OFFSET 0x2b8 +#define GC_FUSE_WRITE_SHADOW_BNK2_INTG_LOCK_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BNK2_INTG_CHKSUM_OFFSET 0x2bc +#define GC_FUSE_WRITE_SHADOW_BNK2_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK0_OFFSET 0x2c0 +#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK0_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK1_OFFSET 0x2c4 +#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK1_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK2_OFFSET 0x2c8 +#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK2_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BNK3_INTG_LOCK_OFFSET 0x2cc +#define GC_FUSE_WRITE_SHADOW_BNK3_INTG_LOCK_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_BNK3_INTG_CHKSUM_OFFSET 0x2d0 +#define GC_FUSE_WRITE_SHADOW_BNK3_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_CLK10HZ_COUNT_OFFSET 0x2d4 +#define GC_FUSE_WRITE_SHADOW_RBOX_CLK10HZ_COUNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_DELAY5MS_COUNT_OFFSET 0x2d8 +#define GC_FUSE_WRITE_SHADOW_RBOX_DELAY5MS_COUNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_DELAY5SEC_COUNT_OFFSET 0x2dc +#define GC_FUSE_WRITE_SHADOW_RBOX_DELAY5SEC_COUNT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_DEBOUNCE_OFFSET 0x2e0 +#define GC_FUSE_WRITE_SHADOW_RBOX_DEBOUNCE_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO0_VAL_OFFSET 0x2e4 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO0_VAL_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO1_VAL_OFFSET 0x2e8 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO1_VAL_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO2_VAL_OFFSET 0x2ec +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO2_VAL_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO0_HOLD_OFFSET 0x2f0 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO1_HOLD_OFFSET 0x2f4 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO2_HOLD_OFFSET 0x2f8 +#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_BLOCK_KEY0_OFFSET 0x2fc +#define GC_FUSE_WRITE_SHADOW_RBOX_BLOCK_KEY0_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_BLOCK_KEY1_OFFSET 0x300 +#define GC_FUSE_WRITE_SHADOW_RBOX_BLOCK_KEY1_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_AC_PRESENT_OFFSET 0x304 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_AC_PRESENT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_PWRB_IN_OFFSET 0x308 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_PWRB_IN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_PWRB_OUT_OFFSET 0x30c +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_PWRB_OUT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY0_IN_OFFSET 0x310 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY0_IN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY0_OUT_OFFSET 0x314 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY0_OUT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY1_IN_OFFSET 0x318 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY1_IN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY1_OUT_OFFSET 0x31c +#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY1_OUT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_AC_PRESENT_OFFSET 0x320 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_AC_PRESENT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_PWRB_IN_OFFSET 0x324 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_PWRB_IN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_PWRB_OUT_OFFSET 0x328 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_PWRB_OUT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY0_IN_OFFSET 0x32c +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY0_IN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY0_OUT_OFFSET 0x330 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY0_OUT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY1_IN_OFFSET 0x334 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY1_IN_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY1_OUT_OFFSET 0x338 +#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY1_OUT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_PWRB_OUT_OFFSET 0x33c +#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_KEY0_OUT_OFFSET 0x340 +#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x0 +#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_KEY1_OUT_OFFSET 0x344 +#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_OFFSET 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_DEFAULT 0x2fff +#define GC_GLOBALSEC_SRAM0_REGION0_OFFSET 0x4 +#define GC_GLOBALSEC_SRAM0_REGION0_DEFAULT 0x2fff +#define GC_GLOBALSEC_SRAM0_REGION1_OFFSET 0x8 +#define GC_GLOBALSEC_SRAM0_REGION1_DEFAULT 0x2fff +#define GC_GLOBALSEC_SRAM1_REGION0_OFFSET 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_DEFAULT 0x2fff +#define GC_GLOBALSEC_SRAM1_REGION1_OFFSET 0x10 +#define GC_GLOBALSEC_SRAM1_REGION1_DEFAULT 0x2fff +#define GC_GLOBALSEC_FLASH0_REGION0_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION0_DEFAULT 0xbfff +#define GC_GLOBALSEC_FLASH0_REGION1_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION1_DEFAULT 0xbfff +#define GC_GLOBALSEC_FLASH0_REGION2_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION2_DEFAULT 0xbfff +#define GC_GLOBALSEC_FLASH0_REGION3_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH0_REGION3_DEFAULT 0xbfff +#define GC_GLOBALSEC_FLASH1_REGION0_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION0_DEFAULT 0xbfff +#define GC_GLOBALSEC_FLASH1_REGION1_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION1_DEFAULT 0xbfff +#define GC_GLOBALSEC_FLASH1_REGION2_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION2_DEFAULT 0xbfff +#define GC_GLOBALSEC_FLASH1_REGION3_OFFSET 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_DEFAULT 0xbfff +#define GC_GLOBALSEC_ROM0_REGION0_BASE_ADDR_OFFSET 0x34 +#define GC_GLOBALSEC_ROM0_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_SIZE_OFFSET 0x38 +#define GC_GLOBALSEC_ROM0_REGION0_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_SRAM0_REGION0_BASE_ADDR_OFFSET 0x3c +#define GC_GLOBALSEC_SRAM0_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_SRAM0_REGION0_SIZE_OFFSET 0x40 +#define GC_GLOBALSEC_SRAM0_REGION0_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_SRAM0_REGION1_BASE_ADDR_OFFSET 0x44 +#define GC_GLOBALSEC_SRAM0_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_SRAM0_REGION1_SIZE_OFFSET 0x48 +#define GC_GLOBALSEC_SRAM0_REGION1_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_SRAM1_REGION0_BASE_ADDR_OFFSET 0x4c +#define GC_GLOBALSEC_SRAM1_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_SRAM1_REGION0_SIZE_OFFSET 0x50 +#define GC_GLOBALSEC_SRAM1_REGION0_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_SRAM1_REGION1_BASE_ADDR_OFFSET 0x54 +#define GC_GLOBALSEC_SRAM1_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_SRAM1_REGION1_SIZE_OFFSET 0x58 +#define GC_GLOBALSEC_SRAM1_REGION1_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_FLASH0_REGION0_BASE_ADDR_OFFSET 0x5c +#define GC_GLOBALSEC_FLASH0_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION0_SIZE_OFFSET 0x60 +#define GC_GLOBALSEC_FLASH0_REGION0_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_FLASH0_REGION1_BASE_ADDR_OFFSET 0x64 +#define GC_GLOBALSEC_FLASH0_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION1_SIZE_OFFSET 0x68 +#define GC_GLOBALSEC_FLASH0_REGION1_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_FLASH0_REGION2_BASE_ADDR_OFFSET 0x6c +#define GC_GLOBALSEC_FLASH0_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION2_SIZE_OFFSET 0x70 +#define GC_GLOBALSEC_FLASH0_REGION2_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_FLASH0_REGION3_BASE_ADDR_OFFSET 0x74 +#define GC_GLOBALSEC_FLASH0_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION3_SIZE_OFFSET 0x78 +#define GC_GLOBALSEC_FLASH0_REGION3_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_FLASH1_REGION0_BASE_ADDR_OFFSET 0x7c +#define GC_GLOBALSEC_FLASH1_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION0_SIZE_OFFSET 0x80 +#define GC_GLOBALSEC_FLASH1_REGION0_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_FLASH1_REGION1_BASE_ADDR_OFFSET 0x84 +#define GC_GLOBALSEC_FLASH1_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION1_SIZE_OFFSET 0x88 +#define GC_GLOBALSEC_FLASH1_REGION1_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_FLASH1_REGION2_BASE_ADDR_OFFSET 0x8c +#define GC_GLOBALSEC_FLASH1_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION2_SIZE_OFFSET 0x90 +#define GC_GLOBALSEC_FLASH1_REGION2_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_FLASH1_REGION3_BASE_ADDR_OFFSET 0x94 +#define GC_GLOBALSEC_FLASH1_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION3_SIZE_OFFSET 0x98 +#define GC_GLOBALSEC_FLASH1_REGION3_SIZE_DEFAULT 0xffff +#define GC_GLOBALSEC_CPU0_D_PERMISSION_OFFSET 0x9c +#define GC_GLOBALSEC_CPU0_D_PERMISSION_DEFAULT 0x55 +#define GC_GLOBALSEC_CPU0_D_DAP_PERMISSION_OFFSET 0xa0 +#define GC_GLOBALSEC_CPU0_D_DAP_PERMISSION_DEFAULT 0x55 +#define GC_GLOBALSEC_CPU0_I_PERMISSION_OFFSET 0xa4 +#define GC_GLOBALSEC_CPU0_I_PERMISSION_DEFAULT 0x55 +#define GC_GLOBALSEC_DDMA0_PERMISSION_OFFSET 0xa8 +#define GC_GLOBALSEC_DDMA0_PERMISSION_DEFAULT 0x55 +#define GC_GLOBALSEC_DSPS0_PERMISSION_OFFSET 0xac +#define GC_GLOBALSEC_DSPS0_PERMISSION_DEFAULT 0x55 +#define GC_GLOBALSEC_DUSB0_PERMISSION_OFFSET 0xb0 +#define GC_GLOBALSEC_DUSB0_PERMISSION_DEFAULT 0x55 +#define GC_GLOBALSEC_FSH_CTRL_PERMISSION_OFFSET 0xb4 +#define GC_GLOBALSEC_FSH_CTRL_PERMISSION_DEFAULT 0x55 +#define GC_GLOBALSEC_SB_COMP_STATUS_OFFSET 0x1000 +#define GC_GLOBALSEC_SB_COMP_STATUS_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_COMP_CONTROL_OFFSET 0x1004 +#define GC_GLOBALSEC_SB_COMP_CONTROL_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_BL_SIG0_OFFSET 0x1008 +#define GC_GLOBALSEC_SB_BL_SIG0_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_BL_SIG1_OFFSET 0x100c +#define GC_GLOBALSEC_SB_BL_SIG1_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_BL_SIG2_OFFSET 0x1010 +#define GC_GLOBALSEC_SB_BL_SIG2_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_BL_SIG3_OFFSET 0x1014 +#define GC_GLOBALSEC_SB_BL_SIG3_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_BL_SIG4_OFFSET 0x1018 +#define GC_GLOBALSEC_SB_BL_SIG4_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_BL_SIG5_OFFSET 0x101c +#define GC_GLOBALSEC_SB_BL_SIG5_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_BL_SIG6_OFFSET 0x1020 +#define GC_GLOBALSEC_SB_BL_SIG6_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_BL_SIG7_OFFSET 0x1024 +#define GC_GLOBALSEC_SB_BL_SIG7_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG2_SIG0_OFFSET 0x1028 +#define GC_GLOBALSEC_SB_STG2_SIG0_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG2_SIG1_OFFSET 0x102c +#define GC_GLOBALSEC_SB_STG2_SIG1_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG2_SIG2_OFFSET 0x1030 +#define GC_GLOBALSEC_SB_STG2_SIG2_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG2_SIG3_OFFSET 0x1034 +#define GC_GLOBALSEC_SB_STG2_SIG3_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG2_SIG4_OFFSET 0x1038 +#define GC_GLOBALSEC_SB_STG2_SIG4_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG2_SIG5_OFFSET 0x103c +#define GC_GLOBALSEC_SB_STG2_SIG5_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG2_SIG6_OFFSET 0x1040 +#define GC_GLOBALSEC_SB_STG2_SIG6_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG2_SIG7_OFFSET 0x1044 +#define GC_GLOBALSEC_SB_STG2_SIG7_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG3_SIG0_OFFSET 0x1048 +#define GC_GLOBALSEC_SB_STG3_SIG0_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG3_SIG1_OFFSET 0x104c +#define GC_GLOBALSEC_SB_STG3_SIG1_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG3_SIG2_OFFSET 0x1050 +#define GC_GLOBALSEC_SB_STG3_SIG2_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG3_SIG3_OFFSET 0x1054 +#define GC_GLOBALSEC_SB_STG3_SIG3_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG3_SIG4_OFFSET 0x1058 +#define GC_GLOBALSEC_SB_STG3_SIG4_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG3_SIG5_OFFSET 0x105c +#define GC_GLOBALSEC_SB_STG3_SIG5_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG3_SIG6_OFFSET 0x1060 +#define GC_GLOBALSEC_SB_STG3_SIG6_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_STG3_SIG7_OFFSET 0x1064 +#define GC_GLOBALSEC_SB_STG3_SIG7_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_NONCE0_OFFSET 0x2000 +#define GC_GLOBALSEC_TM_PW_NONCE0_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_NONCE1_OFFSET 0x2004 +#define GC_GLOBALSEC_TM_PW_NONCE1_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_ATTEMPT0_OFFSET 0x2100 +#define GC_GLOBALSEC_TM_PW_ATTEMPT0_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_ATTEMPT1_OFFSET 0x2104 +#define GC_GLOBALSEC_TM_PW_ATTEMPT1_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_ATTEMPT2_OFFSET 0x2108 +#define GC_GLOBALSEC_TM_PW_ATTEMPT2_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_ATTEMPT3_OFFSET 0x210c +#define GC_GLOBALSEC_TM_PW_ATTEMPT3_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_ATTEMPT4_OFFSET 0x2110 +#define GC_GLOBALSEC_TM_PW_ATTEMPT4_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_ATTEMPT5_OFFSET 0x2114 +#define GC_GLOBALSEC_TM_PW_ATTEMPT5_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_ATTEMPT6_OFFSET 0x2118 +#define GC_GLOBALSEC_TM_PW_ATTEMPT6_DEFAULT 0x0 +#define GC_GLOBALSEC_TM_PW_ATTEMPT7_OFFSET 0x211c +#define GC_GLOBALSEC_TM_PW_ATTEMPT7_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_RWR0_OFFSET 0x3000 +#define GC_GLOBALSEC_HKEY_RWR0_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_RWR1_OFFSET 0x3004 +#define GC_GLOBALSEC_HKEY_RWR1_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_RWR2_OFFSET 0x3008 +#define GC_GLOBALSEC_HKEY_RWR2_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_RWR3_OFFSET 0x300c +#define GC_GLOBALSEC_HKEY_RWR3_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_RWR4_OFFSET 0x3010 +#define GC_GLOBALSEC_HKEY_RWR4_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_RWR5_OFFSET 0x3014 +#define GC_GLOBALSEC_HKEY_RWR5_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_RWR6_OFFSET 0x3018 +#define GC_GLOBALSEC_HKEY_RWR6_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_RWR7_OFFSET 0x301c +#define GC_GLOBALSEC_HKEY_RWR7_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FWR0_OFFSET 0x3100 +#define GC_GLOBALSEC_HKEY_FWR0_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FWR1_OFFSET 0x3104 +#define GC_GLOBALSEC_HKEY_FWR1_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FWR2_OFFSET 0x3108 +#define GC_GLOBALSEC_HKEY_FWR2_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FWR3_OFFSET 0x310c +#define GC_GLOBALSEC_HKEY_FWR3_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FWR4_OFFSET 0x3110 +#define GC_GLOBALSEC_HKEY_FWR4_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FWR5_OFFSET 0x3114 +#define GC_GLOBALSEC_HKEY_FWR5_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FWR6_OFFSET 0x3118 +#define GC_GLOBALSEC_HKEY_FWR6_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FWR7_OFFSET 0x311c +#define GC_GLOBALSEC_HKEY_FWR7_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HWR0_OFFSET 0x3200 +#define GC_GLOBALSEC_HKEY_HWR0_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HWR1_OFFSET 0x3204 +#define GC_GLOBALSEC_HKEY_HWR1_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HWR2_OFFSET 0x3208 +#define GC_GLOBALSEC_HKEY_HWR2_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HWR3_OFFSET 0x320c +#define GC_GLOBALSEC_HKEY_HWR3_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HWR4_OFFSET 0x3210 +#define GC_GLOBALSEC_HKEY_HWR4_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HWR5_OFFSET 0x3214 +#define GC_GLOBALSEC_HKEY_HWR5_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HWR6_OFFSET 0x3218 +#define GC_GLOBALSEC_HKEY_HWR6_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HWR7_OFFSET 0x321c +#define GC_GLOBALSEC_HKEY_HWR7_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR0_OFFSET 0x3300 +#define GC_GLOBALSEC_HKEY_FRR0_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR1_OFFSET 0x3304 +#define GC_GLOBALSEC_HKEY_FRR1_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR2_OFFSET 0x3308 +#define GC_GLOBALSEC_HKEY_FRR2_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR3_OFFSET 0x330c +#define GC_GLOBALSEC_HKEY_FRR3_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR4_OFFSET 0x3310 +#define GC_GLOBALSEC_HKEY_FRR4_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR5_OFFSET 0x3314 +#define GC_GLOBALSEC_HKEY_FRR5_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR6_OFFSET 0x3318 +#define GC_GLOBALSEC_HKEY_FRR6_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR7_OFFSET 0x331c +#define GC_GLOBALSEC_HKEY_FRR7_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR_MTD_OFFSET 0x3320 +#define GC_GLOBALSEC_HKEY_FRR_MTD_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FLSH_FW_MTD_OFFSET 0x3324 +#define GC_GLOBALSEC_HKEY_FLSH_FW_MTD_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ROM_FW_MTD_OFFSET 0x3328 +#define GC_GLOBALSEC_HKEY_ROM_FW_MTD_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HKYSQ_MTD_OFFSET 0x332c +#define GC_GLOBALSEC_HKEY_HKYSQ_MTD_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_OFFSET 0x3334 +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_SEQ_COMMAND_OFFSET 0x3800 +#define GC_GLOBALSEC_HKEY_SEQ_COMMAND_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_SEQ_STATUS_OFFSET 0x3804 +#define GC_GLOBALSEC_HKEY_SEQ_STATUS_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_FW_TRIGGER_OFFSET 0x4000 +#define GC_GLOBALSEC_ALERT_FW_TRIGGER_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_CTR_OFFSET 0x4024 +#define GC_GLOBALSEC_ALERT_GROUPA_CTR_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_CTR_OFFSET 0x4028 +#define GC_GLOBALSEC_ALERT_GROUPB_CTR_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_CTR_OFFSET 0x402c +#define GC_GLOBALSEC_ALERT_GROUPC_CTR_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_THRESHOLD_OFFSET 0x4030 +#define GC_GLOBALSEC_ALERT_GROUPA_THRESHOLD_DEFAULT 0x64 +#define GC_GLOBALSEC_ALERT_GROUPB_THRESHOLD_OFFSET 0x4034 +#define GC_GLOBALSEC_ALERT_GROUPB_THRESHOLD_DEFAULT 0x64 +#define GC_GLOBALSEC_ALERT_GROUPC_THRESHOLD_OFFSET 0x4038 +#define GC_GLOBALSEC_ALERT_GROUPC_THRESHOLD_DEFAULT 0x64 +#define GC_GLOBALSEC_ALERT_CONTROL_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_OFFSET 0x4040 +#define GC_GLOBALSEC_ALERT_DLYCTR0_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_OFFSET 0x4044 +#define GC_GLOBALSEC_ALERT_DLYCTR1_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_OFFSET 0x4048 +#define GC_GLOBALSEC_ALERT_DLYCTR2_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_LEN_OFFSET 0x404c +#define GC_GLOBALSEC_ALERT_DLYCTR0_LEN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_LEN_OFFSET 0x4050 +#define GC_GLOBALSEC_ALERT_DLYCTR1_LEN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_LEN_OFFSET 0x4054 +#define GC_GLOBALSEC_ALERT_DLYCTR2_LEN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_SHUTDOWN_EN_OFFSET 0x4058 +#define GC_GLOBALSEC_ALERT_DLYCTR0_SHUTDOWN_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_SHUTDOWN_EN_OFFSET 0x405c +#define GC_GLOBALSEC_ALERT_DLYCTR1_SHUTDOWN_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_SHUTDOWN_EN_OFFSET 0x4060 +#define GC_GLOBALSEC_ALERT_DLYCTR2_SHUTDOWN_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_WDOG_DIS_OFFSET 0x4064 +#define GC_GLOBALSEC_ALERT_DLYCTR0_WDOG_DIS_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_WDOG_DIS_OFFSET 0x4068 +#define GC_GLOBALSEC_ALERT_DLYCTR1_WDOG_DIS_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_WDOG_DIS_OFFSET 0x406c +#define GC_GLOBALSEC_ALERT_DLYCTR2_WDOG_DIS_DEFAULT 0x0 +#define GC_GLOBALSEC_VERSION_OFFSET 0x4070 +#define GC_GLOBALSEC_VERSION_DEFAULT 0x100105e2 #define GC_GPIO_DATAIN_OFFSET 0x0 #define GC_GPIO_DATAIN_DEFAULT 0x0 #define GC_GPIO_DOUT_OFFSET 0x4 @@ -1843,7 +2946,7 @@ #define GC_I2C_ITOP_OFFSET 0xf04 #define GC_I2C_ITOP_DEFAULT 0x0 #define GC_I2CS_VERSION_OFFSET 0x0 -#define GC_I2CS_VERSION_DEFAULT 0x400b99f +#define GC_I2CS_VERSION_DEFAULT 0x600f6a0 #define GC_I2CS_INT_ENABLE_OFFSET 0x4 #define GC_I2CS_INT_ENABLE_DEFAULT 0x0 #define GC_I2CS_INT_STATE_OFFSET 0x8 @@ -1854,77 +2957,83 @@ #define GC_I2CS_CTRL_SDA_VAL_DEFAULT 0x3d #define GC_I2CS_SLAVE_DEVADDRVAL_OFFSET 0x14 #define GC_I2CS_SLAVE_DEVADDRVAL_DEFAULT 0x0 -#define GC_I2CS_READ_PTR_OFFSET 0x18 +#define GC_I2CS_CLOCK_STRETCH_OFFSET 0x18 +#define GC_I2CS_CLOCK_STRETCH_DEFAULT 0x0 +#define GC_I2CS_AUTO_WAIT_AFTER_WRITE_MODE_OFFSET 0x1c +#define GC_I2CS_AUTO_WAIT_AFTER_WRITE_MODE_DEFAULT 0x0 +#define GC_I2CS_CLOCK_STRETCH_MODE_OFFSET 0x20 +#define GC_I2CS_CLOCK_STRETCH_MODE_DEFAULT 0x0 +#define GC_I2CS_READ_PTR_OFFSET 0x24 #define GC_I2CS_READ_PTR_DEFAULT 0x0 -#define GC_I2CS_WRITE_PTR_OFFSET 0x1c +#define GC_I2CS_WRITE_PTR_OFFSET 0x28 #define GC_I2CS_WRITE_PTR_DEFAULT 0x0 -#define GC_I2CS_READVAL_OFFSET 0x20 +#define GC_I2CS_READVAL_OFFSET 0x2c #define GC_I2CS_READVAL_DEFAULT 0x0 -#define GC_I2CS_CTRL_MSR_OFFSET 0x24 +#define GC_I2CS_CTRL_MSR_OFFSET 0x30 #define GC_I2CS_CTRL_MSR_DEFAULT 0xa -#define GC_I2CS_READ_BUFFER0_OFFSET 0x28 +#define GC_I2CS_READ_BUFFER0_OFFSET 0x34 #define GC_I2CS_READ_BUFFER0_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER1_OFFSET 0x2c +#define GC_I2CS_READ_BUFFER1_OFFSET 0x38 #define GC_I2CS_READ_BUFFER1_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER2_OFFSET 0x30 +#define GC_I2CS_READ_BUFFER2_OFFSET 0x3c #define GC_I2CS_READ_BUFFER2_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER3_OFFSET 0x34 +#define GC_I2CS_READ_BUFFER3_OFFSET 0x40 #define GC_I2CS_READ_BUFFER3_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER4_OFFSET 0x38 +#define GC_I2CS_READ_BUFFER4_OFFSET 0x44 #define GC_I2CS_READ_BUFFER4_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER5_OFFSET 0x3c +#define GC_I2CS_READ_BUFFER5_OFFSET 0x48 #define GC_I2CS_READ_BUFFER5_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER6_OFFSET 0x40 +#define GC_I2CS_READ_BUFFER6_OFFSET 0x4c #define GC_I2CS_READ_BUFFER6_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER7_OFFSET 0x44 +#define GC_I2CS_READ_BUFFER7_OFFSET 0x50 #define GC_I2CS_READ_BUFFER7_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER8_OFFSET 0x48 +#define GC_I2CS_READ_BUFFER8_OFFSET 0x54 #define GC_I2CS_READ_BUFFER8_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER9_OFFSET 0x4c +#define GC_I2CS_READ_BUFFER9_OFFSET 0x58 #define GC_I2CS_READ_BUFFER9_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER10_OFFSET 0x50 +#define GC_I2CS_READ_BUFFER10_OFFSET 0x5c #define GC_I2CS_READ_BUFFER10_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER11_OFFSET 0x54 +#define GC_I2CS_READ_BUFFER11_OFFSET 0x60 #define GC_I2CS_READ_BUFFER11_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER12_OFFSET 0x58 +#define GC_I2CS_READ_BUFFER12_OFFSET 0x64 #define GC_I2CS_READ_BUFFER12_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER13_OFFSET 0x5c +#define GC_I2CS_READ_BUFFER13_OFFSET 0x68 #define GC_I2CS_READ_BUFFER13_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER14_OFFSET 0x60 +#define GC_I2CS_READ_BUFFER14_OFFSET 0x6c #define GC_I2CS_READ_BUFFER14_DEFAULT 0x0 -#define GC_I2CS_READ_BUFFER15_OFFSET 0x64 +#define GC_I2CS_READ_BUFFER15_OFFSET 0x70 #define GC_I2CS_READ_BUFFER15_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER0_OFFSET 0x68 +#define GC_I2CS_WRITE_BUFFER0_OFFSET 0x74 #define GC_I2CS_WRITE_BUFFER0_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER1_OFFSET 0x6c +#define GC_I2CS_WRITE_BUFFER1_OFFSET 0x78 #define GC_I2CS_WRITE_BUFFER1_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER2_OFFSET 0x70 +#define GC_I2CS_WRITE_BUFFER2_OFFSET 0x7c #define GC_I2CS_WRITE_BUFFER2_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER3_OFFSET 0x74 +#define GC_I2CS_WRITE_BUFFER3_OFFSET 0x80 #define GC_I2CS_WRITE_BUFFER3_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER4_OFFSET 0x78 +#define GC_I2CS_WRITE_BUFFER4_OFFSET 0x84 #define GC_I2CS_WRITE_BUFFER4_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER5_OFFSET 0x7c +#define GC_I2CS_WRITE_BUFFER5_OFFSET 0x88 #define GC_I2CS_WRITE_BUFFER5_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER6_OFFSET 0x80 +#define GC_I2CS_WRITE_BUFFER6_OFFSET 0x8c #define GC_I2CS_WRITE_BUFFER6_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER7_OFFSET 0x84 +#define GC_I2CS_WRITE_BUFFER7_OFFSET 0x90 #define GC_I2CS_WRITE_BUFFER7_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER8_OFFSET 0x88 +#define GC_I2CS_WRITE_BUFFER8_OFFSET 0x94 #define GC_I2CS_WRITE_BUFFER8_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER9_OFFSET 0x8c +#define GC_I2CS_WRITE_BUFFER9_OFFSET 0x98 #define GC_I2CS_WRITE_BUFFER9_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER10_OFFSET 0x90 +#define GC_I2CS_WRITE_BUFFER10_OFFSET 0x9c #define GC_I2CS_WRITE_BUFFER10_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER11_OFFSET 0x94 +#define GC_I2CS_WRITE_BUFFER11_OFFSET 0xa0 #define GC_I2CS_WRITE_BUFFER11_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER12_OFFSET 0x98 +#define GC_I2CS_WRITE_BUFFER12_OFFSET 0xa4 #define GC_I2CS_WRITE_BUFFER12_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER13_OFFSET 0x9c +#define GC_I2CS_WRITE_BUFFER13_OFFSET 0xa8 #define GC_I2CS_WRITE_BUFFER13_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER14_OFFSET 0xa0 +#define GC_I2CS_WRITE_BUFFER14_OFFSET 0xac #define GC_I2CS_WRITE_BUFFER14_DEFAULT 0x0 -#define GC_I2CS_WRITE_BUFFER15_OFFSET 0xa4 +#define GC_I2CS_WRITE_BUFFER15_OFFSET 0xb0 #define GC_I2CS_WRITE_BUFFER15_DEFAULT 0x0 #define GC_MAU_EN_OFFSET 0x0 #define GC_MAU_EN_DEFAULT 0x3 @@ -1936,14 +3045,6 @@ #define GC_MAU_TRACE_SYSIBUS_DEFAULT 0x0 #define GC_MAU_TRACE_SYSDBUS_OFFSET 0x10 #define GC_MAU_TRACE_SYSDBUS_DEFAULT 0x0 -#define GC_PAU_EN_OFFSET 0x0 -#define GC_PAU_EN_DEFAULT 0x1 -#define GC_PAU_TRACECLR_OFFSET 0x4 -#define GC_PAU_TRACECLR_DEFAULT 0x1 -#define GC_PAU_TRACEIDX_OFFSET 0x8 -#define GC_PAU_TRACEIDX_DEFAULT 0x1 -#define GC_PAU_TRACE_SYSSBUS_OFFSET 0xc -#define GC_PAU_TRACE_SYSSBUS_DEFAULT 0x0 #define GC_PINMUX_DIOM0_SEL_OFFSET 0x0 #define GC_PINMUX_DIOM0_SEL_DEFAULT 0x0 #define GC_PINMUX_DIOM0_CTL_OFFSET 0x4 @@ -2056,274 +3157,212 @@ #define GC_PINMUX_DIOB7_SEL_DEFAULT 0x0 #define GC_PINMUX_DIOB7_CTL_OFFSET 0xdc #define GC_PINMUX_DIOB7_CTL_DEFAULT 0x3 -#define GC_PINMUX_DIOB8_SEL_OFFSET 0xe0 -#define GC_PINMUX_DIOB8_SEL_DEFAULT 0x0 -#define GC_PINMUX_DIOB8_CTL_OFFSET 0xe4 -#define GC_PINMUX_DIOB8_CTL_DEFAULT 0x3 -#define GC_PINMUX_RTCXOP_SEL_OFFSET 0xe8 -#define GC_PINMUX_RTCXOP_SEL_DEFAULT 0x0 -#define GC_PINMUX_RTCXOP_CTL_OFFSET 0xec -#define GC_PINMUX_RTCXOP_CTL_DEFAULT 0x3 -#define GC_PINMUX_SWDPTRACE_SEL_OFFSET 0xf0 +#define GC_PINMUX_SWDPTRACE_SEL_OFFSET 0xe0 #define GC_PINMUX_SWDPTRACE_SEL_DEFAULT 0x0 -#define GC_PINMUX_SWDPTRACE_CTL_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_OFFSET 0xe4 #define GC_PINMUX_SWDPTRACE_CTL_DEFAULT 0x3 -#define GC_PINMUX_SWDPDATA_SEL_OFFSET 0xf8 +#define GC_PINMUX_SWDPDATA_SEL_OFFSET 0xe8 #define GC_PINMUX_SWDPDATA_SEL_DEFAULT 0x0 -#define GC_PINMUX_SWDPDATA_CTL_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_OFFSET 0xec #define GC_PINMUX_SWDPDATA_CTL_DEFAULT 0x7 -#define GC_PINMUX_TESTMODE_SEL_OFFSET 0x100 -#define GC_PINMUX_TESTMODE_SEL_DEFAULT 0x0 -#define GC_PINMUX_TESTMODE_CTL_OFFSET 0x104 -#define GC_PINMUX_TESTMODE_CTL_DEFAULT 0x7 -#define GC_PINMUX_RESETB_SEL_OFFSET 0x108 +#define GC_PINMUX_RESETB_SEL_OFFSET 0xf0 #define GC_PINMUX_RESETB_SEL_DEFAULT 0x0 -#define GC_PINMUX_RESETB_CTL_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_OFFSET 0xf4 #define GC_PINMUX_RESETB_CTL_DEFAULT 0x7 -#define GC_PINMUX_VIO0_SEL_OFFSET 0x110 -#define GC_PINMUX_VIO0_SEL_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_OFFSET 0x114 -#define GC_PINMUX_VIO0_CTL_DEFAULT 0x3 -#define GC_PINMUX_VIO1_SEL_OFFSET 0x118 -#define GC_PINMUX_VIO1_SEL_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_OFFSET 0x11c -#define GC_PINMUX_VIO1_CTL_DEFAULT 0x3 -#define GC_PINMUX_TDI_SEL_OFFSET 0x120 +#define GC_PINMUX_TRSTN_SEL_OFFSET 0xf8 +#define GC_PINMUX_TRSTN_SEL_DEFAULT 0x0 +#define GC_PINMUX_TRSTN_CTL_OFFSET 0xfc +#define GC_PINMUX_TRSTN_CTL_DEFAULT 0x3 +#define GC_PINMUX_TDI_SEL_OFFSET 0x100 #define GC_PINMUX_TDI_SEL_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_OFFSET 0x104 #define GC_PINMUX_TDI_CTL_DEFAULT 0x3 -#define GC_PINMUX_TMS_SEL_OFFSET 0x128 +#define GC_PINMUX_TMS_SEL_OFFSET 0x108 #define GC_PINMUX_TMS_SEL_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_OFFSET 0x10c #define GC_PINMUX_TMS_CTL_DEFAULT 0x3 -#define GC_PINMUX_TCK_SEL_OFFSET 0x130 +#define GC_PINMUX_TCK_SEL_OFFSET 0x110 #define GC_PINMUX_TCK_SEL_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_OFFSET 0x114 #define GC_PINMUX_TCK_CTL_DEFAULT 0x3 -#define GC_PINMUX_TDO_SEL_OFFSET 0x138 +#define GC_PINMUX_TDO_SEL_OFFSET 0x118 #define GC_PINMUX_TDO_SEL_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_OFFSET 0x11c #define GC_PINMUX_TDO_CTL_DEFAULT 0x3 -#define GC_PINMUX_SETHOLD0_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD1_OFFSET 0x144 -#define GC_PINMUX_SETHOLD1_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD1_OFFSET 0x14c -#define GC_PINMUX_CLRHOLD1_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO0_SEL_OFFSET 0x150 +#define GC_PINMUX_VIO0_SEL_OFFSET 0x120 +#define GC_PINMUX_VIO0_SEL_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_DEFAULT 0x3 +#define GC_PINMUX_VIO1_SEL_OFFSET 0x128 +#define GC_PINMUX_VIO1_SEL_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_DEFAULT 0x3 +#define GC_PINMUX_GPIO0_GPIO0_SEL_OFFSET 0x130 #define GC_PINMUX_GPIO0_GPIO0_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO1_SEL_OFFSET 0x154 +#define GC_PINMUX_GPIO0_GPIO1_SEL_OFFSET 0x134 #define GC_PINMUX_GPIO0_GPIO1_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO2_SEL_OFFSET 0x158 +#define GC_PINMUX_GPIO0_GPIO2_SEL_OFFSET 0x138 #define GC_PINMUX_GPIO0_GPIO2_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO3_SEL_OFFSET 0x15c +#define GC_PINMUX_GPIO0_GPIO3_SEL_OFFSET 0x13c #define GC_PINMUX_GPIO0_GPIO3_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO4_SEL_OFFSET 0x160 +#define GC_PINMUX_GPIO0_GPIO4_SEL_OFFSET 0x140 #define GC_PINMUX_GPIO0_GPIO4_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO5_SEL_OFFSET 0x164 +#define GC_PINMUX_GPIO0_GPIO5_SEL_OFFSET 0x144 #define GC_PINMUX_GPIO0_GPIO5_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO6_SEL_OFFSET 0x168 +#define GC_PINMUX_GPIO0_GPIO6_SEL_OFFSET 0x148 #define GC_PINMUX_GPIO0_GPIO6_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO7_SEL_OFFSET 0x16c +#define GC_PINMUX_GPIO0_GPIO7_SEL_OFFSET 0x14c #define GC_PINMUX_GPIO0_GPIO7_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO8_SEL_OFFSET 0x170 +#define GC_PINMUX_GPIO0_GPIO8_SEL_OFFSET 0x150 #define GC_PINMUX_GPIO0_GPIO8_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO9_SEL_OFFSET 0x174 +#define GC_PINMUX_GPIO0_GPIO9_SEL_OFFSET 0x154 #define GC_PINMUX_GPIO0_GPIO9_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO10_SEL_OFFSET 0x178 +#define GC_PINMUX_GPIO0_GPIO10_SEL_OFFSET 0x158 #define GC_PINMUX_GPIO0_GPIO10_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO11_SEL_OFFSET 0x17c +#define GC_PINMUX_GPIO0_GPIO11_SEL_OFFSET 0x15c #define GC_PINMUX_GPIO0_GPIO11_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO12_SEL_OFFSET 0x180 +#define GC_PINMUX_GPIO0_GPIO12_SEL_OFFSET 0x160 #define GC_PINMUX_GPIO0_GPIO12_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO13_SEL_OFFSET 0x184 +#define GC_PINMUX_GPIO0_GPIO13_SEL_OFFSET 0x164 #define GC_PINMUX_GPIO0_GPIO13_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO14_SEL_OFFSET 0x188 +#define GC_PINMUX_GPIO0_GPIO14_SEL_OFFSET 0x168 #define GC_PINMUX_GPIO0_GPIO14_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO15_SEL_OFFSET 0x18c +#define GC_PINMUX_GPIO0_GPIO15_SEL_OFFSET 0x16c #define GC_PINMUX_GPIO0_GPIO15_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO0_SEL_OFFSET 0x190 +#define GC_PINMUX_GPIO1_GPIO0_SEL_OFFSET 0x170 #define GC_PINMUX_GPIO1_GPIO0_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO1_SEL_OFFSET 0x194 +#define GC_PINMUX_GPIO1_GPIO1_SEL_OFFSET 0x174 #define GC_PINMUX_GPIO1_GPIO1_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO2_SEL_OFFSET 0x198 +#define GC_PINMUX_GPIO1_GPIO2_SEL_OFFSET 0x178 #define GC_PINMUX_GPIO1_GPIO2_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO3_SEL_OFFSET 0x19c +#define GC_PINMUX_GPIO1_GPIO3_SEL_OFFSET 0x17c #define GC_PINMUX_GPIO1_GPIO3_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO4_SEL_OFFSET 0x1a0 +#define GC_PINMUX_GPIO1_GPIO4_SEL_OFFSET 0x180 #define GC_PINMUX_GPIO1_GPIO4_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO5_SEL_OFFSET 0x1a4 +#define GC_PINMUX_GPIO1_GPIO5_SEL_OFFSET 0x184 #define GC_PINMUX_GPIO1_GPIO5_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO6_SEL_OFFSET 0x1a8 +#define GC_PINMUX_GPIO1_GPIO6_SEL_OFFSET 0x188 #define GC_PINMUX_GPIO1_GPIO6_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO7_SEL_OFFSET 0x1ac +#define GC_PINMUX_GPIO1_GPIO7_SEL_OFFSET 0x18c #define GC_PINMUX_GPIO1_GPIO7_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO8_SEL_OFFSET 0x1b0 +#define GC_PINMUX_GPIO1_GPIO8_SEL_OFFSET 0x190 #define GC_PINMUX_GPIO1_GPIO8_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO9_SEL_OFFSET 0x1b4 +#define GC_PINMUX_GPIO1_GPIO9_SEL_OFFSET 0x194 #define GC_PINMUX_GPIO1_GPIO9_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO10_SEL_OFFSET 0x1b8 +#define GC_PINMUX_GPIO1_GPIO10_SEL_OFFSET 0x198 #define GC_PINMUX_GPIO1_GPIO10_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO11_SEL_OFFSET 0x1bc +#define GC_PINMUX_GPIO1_GPIO11_SEL_OFFSET 0x19c #define GC_PINMUX_GPIO1_GPIO11_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO12_SEL_OFFSET 0x1c0 +#define GC_PINMUX_GPIO1_GPIO12_SEL_OFFSET 0x1a0 #define GC_PINMUX_GPIO1_GPIO12_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO13_SEL_OFFSET 0x1c4 +#define GC_PINMUX_GPIO1_GPIO13_SEL_OFFSET 0x1a4 #define GC_PINMUX_GPIO1_GPIO13_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO14_SEL_OFFSET 0x1c8 +#define GC_PINMUX_GPIO1_GPIO14_SEL_OFFSET 0x1a8 #define GC_PINMUX_GPIO1_GPIO14_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO15_SEL_OFFSET 0x1cc +#define GC_PINMUX_GPIO1_GPIO15_SEL_OFFSET 0x1ac #define GC_PINMUX_GPIO1_GPIO15_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2CS0_SCL_SEL_OFFSET 0x1d0 +#define GC_PINMUX_I2CS0_SCL_SEL_OFFSET 0x1b0 #define GC_PINMUX_I2CS0_SCL_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2CS0_SDA_SEL_OFFSET 0x1d4 +#define GC_PINMUX_I2CS0_SDA_SEL_OFFSET 0x1b4 #define GC_PINMUX_I2CS0_SDA_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2C0_SCL_SEL_OFFSET 0x1d8 +#define GC_PINMUX_I2C0_SCL_SEL_OFFSET 0x1b8 #define GC_PINMUX_I2C0_SCL_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2C0_SDA_SEL_OFFSET 0x1dc +#define GC_PINMUX_I2C0_SDA_SEL_OFFSET 0x1bc #define GC_PINMUX_I2C0_SDA_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2C1_SCL_SEL_OFFSET 0x1e0 +#define GC_PINMUX_I2C1_SCL_SEL_OFFSET 0x1c0 #define GC_PINMUX_I2C1_SCL_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2C1_SDA_SEL_OFFSET 0x1e4 +#define GC_PINMUX_I2C1_SDA_SEL_OFFSET 0x1c4 #define GC_PINMUX_I2C1_SDA_SEL_DEFAULT 0x0 -#define GC_PINMUX_PMU_TESTBUS0_SEL_OFFSET 0x1e8 -#define GC_PINMUX_PMU_TESTBUS0_SEL_DEFAULT 0x0 -#define GC_PINMUX_PMU_TESTBUS1_SEL_OFFSET 0x1ec -#define GC_PINMUX_PMU_TESTBUS1_SEL_DEFAULT 0x0 -#define GC_PINMUX_PMU_TESTBUS2_SEL_OFFSET 0x1f0 -#define GC_PINMUX_PMU_TESTBUS2_SEL_DEFAULT 0x0 -#define GC_PINMUX_PMU_TESTBUS3_SEL_OFFSET 0x1f4 -#define GC_PINMUX_PMU_TESTBUS3_SEL_DEFAULT 0x0 -#define GC_PINMUX_PMU_TESTBUS4_SEL_OFFSET 0x1f8 -#define GC_PINMUX_PMU_TESTBUS4_SEL_DEFAULT 0x0 -#define GC_PINMUX_PMU_TESTBUS5_SEL_OFFSET 0x1fc -#define GC_PINMUX_PMU_TESTBUS5_SEL_DEFAULT 0x0 -#define GC_PINMUX_PMU_TESTBUS6_SEL_OFFSET 0x200 -#define GC_PINMUX_PMU_TESTBUS6_SEL_DEFAULT 0x0 -#define GC_PINMUX_PMU_TESTBUS7_SEL_OFFSET 0x204 -#define GC_PINMUX_PMU_TESTBUS7_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_AC_PRESENT_SEL_OFFSET 0x208 -#define GC_PINMUX_RBOX0_AC_PRESENT_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_BATT_EN_SEL_OFFSET 0x20c -#define GC_PINMUX_RBOX0_BATT_EN_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_EC_IN_RW_SEL_OFFSET 0x210 -#define GC_PINMUX_RBOX0_EC_IN_RW_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_EC_RST_L_SEL_OFFSET 0x214 -#define GC_PINMUX_RBOX0_EC_RST_L_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_EC_WP_L_SEL_OFFSET 0x218 -#define GC_PINMUX_RBOX0_EC_WP_L_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_ENTERING_RW_SEL_OFFSET 0x21c -#define GC_PINMUX_RBOX0_ENTERING_RW_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_FW_WP_L_SEL_OFFSET 0x220 -#define GC_PINMUX_RBOX0_FW_WP_L_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_KSI_SEL_OFFSET 0x224 -#define GC_PINMUX_RBOX0_KSI_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_KSI_SW_SEL_OFFSET 0x228 -#define GC_PINMUX_RBOX0_KSI_SW_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_KSO_INV_SEL_OFFSET 0x22c -#define GC_PINMUX_RBOX0_KSO_INV_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_KSO_SW_SEL_OFFSET 0x230 -#define GC_PINMUX_RBOX0_KSO_SW_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_PWR_BTN_L_SEL_OFFSET 0x234 -#define GC_PINMUX_RBOX0_PWR_BTN_L_SEL_DEFAULT 0x0 -#define GC_PINMUX_RBOX0_PWR_BTNO_L_SEL_OFFSET 0x238 -#define GC_PINMUX_RBOX0_PWR_BTNO_L_SEL_DEFAULT 0x0 -#define GC_PINMUX_RTC0_X_RTC_CLK_SEL_OFFSET 0x23c -#define GC_PINMUX_RTC0_X_RTC_CLK_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPI0_SPICLK_SEL_OFFSET 0x240 -#define GC_PINMUX_SPI0_SPICLK_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPI0_SPICSB_SEL_OFFSET 0x244 -#define GC_PINMUX_SPI0_SPICSB_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPI0_SPIMISO_SEL_OFFSET 0x248 -#define GC_PINMUX_SPI0_SPIMISO_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPI0_SPIMOSI_SEL_OFFSET 0x24c -#define GC_PINMUX_SPI0_SPIMOSI_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPS0_SPICLK_SEL_OFFSET 0x250 -#define GC_PINMUX_SPS0_SPICLK_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPS0_SPICSB_SEL_OFFSET 0x254 -#define GC_PINMUX_SPS0_SPICSB_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPS0_SPIMISO_SEL_OFFSET 0x258 -#define GC_PINMUX_SPS0_SPIMISO_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPS0_SPIMOSI_SEL_OFFSET 0x25c -#define GC_PINMUX_SPS0_SPIMOSI_SEL_DEFAULT 0x0 -#define GC_PINMUX_SWDP0_TRACE_SEL_OFFSET 0x260 -#define GC_PINMUX_SWDP0_TRACE_SEL_DEFAULT 0x0 -#define GC_PINMUX_SWDP0_TRACE2_SEL_OFFSET 0x264 +#define GC_PINMUX_PMU_BROWNOUT_DET_SEL_OFFSET 0x1c8 +#define GC_PINMUX_PMU_BROWNOUT_DET_SEL_DEFAULT 0x0 +#define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL_OFFSET 0x1cc +#define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPI1_SPICLK_SEL_OFFSET 0x1d0 +#define GC_PINMUX_SPI1_SPICLK_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPI1_SPICSB_SEL_OFFSET 0x1d4 +#define GC_PINMUX_SPI1_SPICSB_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPI1_SPIMISO_SEL_OFFSET 0x1d8 +#define GC_PINMUX_SPI1_SPIMISO_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPI1_SPIMOSI_SEL_OFFSET 0x1dc +#define GC_PINMUX_SPI1_SPIMOSI_SEL_DEFAULT 0x0 +#define GC_PINMUX_SWDP0_TRACE2_SEL_OFFSET 0x1e0 #define GC_PINMUX_SWDP0_TRACE2_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_OFFSET 0x268 +#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_OFFSET 0x1e4 #define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_OFFSET 0x26c +#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_OFFSET 0x1e8 #define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_OFFSET 0x270 +#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_OFFSET 0x1ec #define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_OFFSET 0x274 +#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_OFFSET 0x1f0 #define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_DEFAULT 0x0 -#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_OFFSET 0x278 +#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_OFFSET 0x1f4 #define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_DEFAULT 0x0 -#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_OFFSET 0x27c +#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_OFFSET 0x1f8 #define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_CTS_SEL_OFFSET 0x280 +#define GC_PINMUX_UART0_CTS_SEL_OFFSET 0x1fc #define GC_PINMUX_UART0_CTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_RTS_SEL_OFFSET 0x284 +#define GC_PINMUX_UART0_RTS_SEL_OFFSET 0x200 #define GC_PINMUX_UART0_RTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_RX_SEL_OFFSET 0x288 +#define GC_PINMUX_UART0_RX_SEL_OFFSET 0x204 #define GC_PINMUX_UART0_RX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_TX_SEL_OFFSET 0x28c +#define GC_PINMUX_UART0_TX_SEL_OFFSET 0x208 #define GC_PINMUX_UART0_TX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_CTS_SEL_OFFSET 0x290 +#define GC_PINMUX_UART1_CTS_SEL_OFFSET 0x20c #define GC_PINMUX_UART1_CTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_RTS_SEL_OFFSET 0x294 +#define GC_PINMUX_UART1_RTS_SEL_OFFSET 0x210 #define GC_PINMUX_UART1_RTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_RX_SEL_OFFSET 0x298 +#define GC_PINMUX_UART1_RX_SEL_OFFSET 0x214 #define GC_PINMUX_UART1_RX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_TX_SEL_OFFSET 0x29c +#define GC_PINMUX_UART1_TX_SEL_OFFSET 0x218 #define GC_PINMUX_UART1_TX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_CTS_SEL_OFFSET 0x2a0 +#define GC_PINMUX_UART2_CTS_SEL_OFFSET 0x21c #define GC_PINMUX_UART2_CTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_RTS_SEL_OFFSET 0x2a4 +#define GC_PINMUX_UART2_RTS_SEL_OFFSET 0x220 #define GC_PINMUX_UART2_RTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_RX_SEL_OFFSET 0x2a8 +#define GC_PINMUX_UART2_RX_SEL_OFFSET 0x224 #define GC_PINMUX_UART2_RX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_TX_SEL_OFFSET 0x2ac +#define GC_PINMUX_UART2_TX_SEL_OFFSET 0x228 #define GC_PINMUX_UART2_TX_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x2b0 +#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x22c #define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x2b4 +#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x230 #define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x2b8 +#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x234 #define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x2bc +#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x238 #define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x2c0 +#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x23c #define GC_PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x2c4 +#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x240 #define GC_PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x2c8 +#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x244 #define GC_PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x2cc +#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x248 #define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x2d0 +#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x24c #define GC_PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x2d4 +#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x250 #define GC_PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x2d8 +#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x254 #define GC_PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0 -#define GC_PINMUX_XO0_TESTCLK_SEL_OFFSET 0x2dc -#define GC_PINMUX_XO0_TESTCLK_SEL_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_OFFSET 0x2e0 +#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x258 +#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_DEFAULT 0x0 +#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET 0x25c +#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_OFFSET 0x2e4 +#define GC_PINMUX_EXITEN1_OFFSET 0x264 #define GC_PINMUX_EXITEN1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_OFFSET 0x2ec +#define GC_PINMUX_EXITEDGE1_OFFSET 0x26c #define GC_PINMUX_EXITEDGE1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_OFFSET 0x2f4 +#define GC_PINMUX_EXITINV1_OFFSET 0x274 #define GC_PINMUX_EXITINV1_DEFAULT 0x0 +#define GC_PINMUX_HOLD_OFFSET 0x278 +#define GC_PINMUX_HOLD_DEFAULT 0x0 #define GC_PMU_RESET_OFFSET 0x0 #define GC_PMU_RESET_DEFAULT 0x3 #define GC_PMU_SETRST_OFFSET 0x4 @@ -2335,241 +3374,326 @@ #define GC_PMU_GLOBAL_RESET_OFFSET 0x10 #define GC_PMU_GLOBAL_RESET_DEFAULT 0x0 #define GC_PMU_GLOBAL_RESET_KEY 0x7041776 -#define GC_PMU_SETDIS_OFFSET 0x14 -#define GC_PMU_SETDIS_DEFAULT 0x0 -#define GC_PMU_CLRDIS_OFFSET 0x18 -#define GC_PMU_CLRDIS_DEFAULT 0x0 -#define GC_PMU_STATDIS_OFFSET 0x1c -#define GC_PMU_STATDIS_DEFAULT 0xec000 +#define GC_PMU_LOW_POWER_DIS_OFFSET 0x14 +#define GC_PMU_LOW_POWER_DIS_DEFAULT 0x1e +#define GC_PMU_LOW_POWER_BYPASS_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_OFFSET 0x1c +#define GC_PMU_LOW_POWER_BYPASS_VALUE_DEFAULT 0x0 #define GC_PMU_SETWIC_OFFSET 0x20 #define GC_PMU_SETWIC_DEFAULT 0x0 #define GC_PMU_CLRWIC_OFFSET 0x24 #define GC_PMU_CLRWIC_DEFAULT 0x0 #define GC_PMU_SYSVTOR_OFFSET 0x28 #define GC_PMU_SYSVTOR_DEFAULT 0xffffffff -#define GC_PMU_EXCLUSIVE_OFFSET 0x2c -#define GC_PMU_EXCLUSIVE_DEFAULT 0x0 -#define GC_PMU_DAP_ID0_OFFSET 0x30 -#define GC_PMU_DAP_ID0_DEFAULT 0x0 -#define GC_PMU_DAP_EN_OFFSET 0x34 -#define GC_PMU_DAP_EN_DEFAULT 0x0 -#define GC_PMU_DAP_LOCK_OFFSET 0x38 -#define GC_PMU_DAP_LOCK_DEFAULT 0x1 -#define GC_PMU_DAP_UNLOCK_OFFSET 0x3c -#define GC_PMU_DAP_UNLOCK_DEFAULT 0x0 -#define GC_PMU_DAP_UNLOCK_KEY 0xb4502f2f -#define GC_PMU_NAP_EN_OFFSET 0x40 +#define GC_PMU_NAP_EN_OFFSET 0x2c #define GC_PMU_NAP_EN_DEFAULT 0x0 -#define GC_PMUSETMODEL_FPGA_OFFSET 0x44 -#define GC_PMUSETMODEL_FPGA_DEFAULT 0x0 -#define GC_PMUCLRMODEL_FPGA_OFFSET 0x48 -#define GC_PMUCLRMODEL_FPGA_DEFAULT 0x0 -#define GC_PMUSETRTC_OFFSET 0x4c -#define GC_PMUSETRTC_DEFAULT 0x0 -#define GC_PMUCLRRTC_OFFSET 0x50 -#define GC_PMUCLRRTC_DEFAULT 0x0 -#define GC_PMU_VREF_OFFSET 0x54 -#define GC_PMU_VREF_DEFAULT 0xffff88 -#define GC_PMU_VREFCMP_OFFSET 0x58 -#define GC_PMU_VREFCMP_DEFAULT 0x0 -#define GC_PMU_RBIAS_OFFSET 0x5c -#define GC_PMU_RBIAS_DEFAULT 0x0 -#define GC_PMU_RBIASLO_OFFSET 0x60 -#define GC_PMU_RBIASLO_DEFAULT 0x0 -#define GC_PMU_RBIASHI_OFFSET 0x64 -#define GC_PMU_RBIASHI_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_DEFAULT 0x0 -#define GC_PMU_BAT_LVL_OK_OFFSET 0x70 +#define GC_PMU_MODEL_FPGA_OFFSET 0x30 +#define GC_PMU_MODEL_FPGA_DEFAULT 0x0 +#define GC_PMU_SW_PDB_OFFSET 0x34 +#define GC_PMU_SW_PDB_DEFAULT 0x0 +#define GC_PMU_SW_PDB_SECURE_OFFSET 0x38 +#define GC_PMU_SW_PDB_SECURE_DEFAULT 0x0 +#define GC_PMU_VREF_OFFSET 0x3c +#define GC_PMU_VREF_DEFAULT 0xfb +#define GC_PMU_BAT_LVL_OK_OFFSET 0x40 #define GC_PMU_BAT_LVL_OK_DEFAULT 0x0 -#define GC_PMU_B_REG_DIG_CTRL_OFFSET 0x74 +#define GC_PMU_B_REG_DIG_CTRL_OFFSET 0x44 #define GC_PMU_B_REG_DIG_CTRL_DEFAULT 0x0 -#define GC_PMU_B_REG_DIG_LATCH_CTRL_OFFSET 0x78 -#define GC_PMU_B_REG_DIG_LATCH_CTRL_DEFAULT 0x0 -#define GC_PMU_EXITPD_HOLD_SET_OFFSET 0x7c -#define GC_PMU_EXITPD_HOLD_SET_DEFAULT 0x0 -#define GC_PMU_EXITPD_HOLD_CLR_OFFSET 0x80 -#define GC_PMU_EXITPD_HOLD_CLR_DEFAULT 0x0 -#define GC_PMU_EXITPD_MASK_OFFSET 0x84 -#define GC_PMU_EXITPD_MASK_DEFAULT 0x7 -#define GC_PMU_EXITPD_SRC_OFFSET 0x88 +#define GC_PMU_EXITPD_MASK_OFFSET 0x48 +#define GC_PMU_EXITPD_MASK_DEFAULT 0x0 +#define GC_PMU_EXITPD_SRC_OFFSET 0x4c #define GC_PMU_EXITPD_SRC_DEFAULT 0x0 -#define GC_PMU_EXITPD_MON_OFFSET 0x8c +#define GC_PMU_EXITPD_MON_OFFSET 0x50 #define GC_PMU_EXITPD_MON_DEFAULT 0x0 -#define GC_PMU_OSC_HOLD_SET_OFFSET 0x90 -#define GC_PMU_OSC_HOLD_SET_DEFAULT 0x0 -#define GC_PMU_OSC_HOLD_CLR_OFFSET 0x94 -#define GC_PMU_OSC_HOLD_CLR_DEFAULT 0x0 -#define GC_PMU_OSC_SELECT_OFFSET 0x98 -#define GC_PMU_OSC_SELECT_DEFAULT 0x3 -#define GC_PMU_OSC_SELECT_XTL 0x0 -#define GC_PMU_OSC_SELECT_RC_TRIM 0x2 -#define GC_PMU_OSC_SELECT_RC 0x3 -#define GC_PMU_OSC_SELECT_STAT_OFFSET 0x9c -#define GC_PMU_OSC_SELECT_STAT_DEFAULT 0x3 -#define GC_PMU_OSC_SELECT_STAT_XTL 0x0 -#define GC_PMU_OSC_SELECT_STAT_RC_TRIM 0x2 -#define GC_PMU_OSC_SELECT_STAT_RC 0x3 -#define GC_PMU_OSC_CTRL_OFFSET 0xa0 -#define GC_PMU_OSC_CTRL_DEFAULT 0x3 -#define GC_PMU_MEMCLKSET_OFFSET 0xa4 +#define GC_PMU_OSC_CTRL_OFFSET 0x54 +#define GC_PMU_OSC_CTRL_DEFAULT 0x1 +#define GC_PMU_MEMCLKSET_OFFSET 0x58 #define GC_PMU_MEMCLKSET_DEFAULT 0x7f -#define GC_PMU_MEMCLKCLR_OFFSET 0xa8 +#define GC_PMU_MEMCLKCLR_OFFSET 0x5c #define GC_PMU_MEMCLKCLR_DEFAULT 0x7f -#define GC_PMU_PERICLKSET0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DEFAULT 0x80001e08 -#define GC_PMU_PERICLKCLR0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DEFAULT 0x80001e08 -#define GC_PMU_PERICLKSET1_OFFSET 0xb4 -#define GC_PMU_PERICLKSET1_DEFAULT 0x3 -#define GC_PMU_PERICLKCLR1_OFFSET 0xb8 -#define GC_PMU_PERICLKCLR1_DEFAULT 0x3 -#define GC_PMU_PERIGATEONSLEEPSET0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DEFAULT 0xc0044e00 -#define GC_PMU_PERIGATEONSLEEPCLR0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DEFAULT 0xc0044e00 -#define GC_PMU_PERIGATEONSLEEPSET1_OFFSET 0xc4 -#define GC_PMU_PERIGATEONSLEEPSET1_DEFAULT 0x3 -#define GC_PMU_PERIGATEONSLEEPCLR1_OFFSET 0xc8 -#define GC_PMU_PERIGATEONSLEEPCLR1_DEFAULT 0x3 -#define GC_PMU_CLK0_OFFSET 0xcc +#define GC_PMU_PERICLKSET0_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DEFAULT 0x781f81ee +#define GC_PMU_PERICLKCLR0_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DEFAULT 0x781f81ee +#define GC_PMU_PERICLKSET1_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DEFAULT 0xf0c41 +#define GC_PMU_PERICLKCLR1_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DEFAULT 0xf0c41 +#define GC_PMU_PERIGATEONSLEEPSET0_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DEFAULT 0x0 +#define GC_PMU_CLK0_OFFSET 0x80 #define GC_PMU_CLK0_DEFAULT 0x1f -#define GC_PMU_CLK1_OFFSET 0xd0 -#define GC_PMU_CLK1_DEFAULT 0x1f -#define GC_PMU_RST0_OFFSET 0xd4 +#define GC_PMU_RST0_OFFSET 0x84 #define GC_PMU_RST0_DEFAULT 0x0 -#define GC_PMU_RST1_OFFSET 0xd8 +#define GC_PMU_RST1_OFFSET 0x88 #define GC_PMU_RST1_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH_HOLD_SET_OFFSET 0xdc -#define GC_PMU_PWRDN_SCRATCH_HOLD_SET_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH_HOLD_CLR_OFFSET 0xe0 -#define GC_PMU_PWRDN_SCRATCH_HOLD_CLR_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH0_OFFSET 0xe4 +#define GC_PMU_PWRDN_SCRATCH0_OFFSET 0x8c #define GC_PMU_PWRDN_SCRATCH0_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH1_OFFSET 0xe8 +#define GC_PMU_PWRDN_SCRATCH1_OFFSET 0x90 #define GC_PMU_PWRDN_SCRATCH1_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH2_OFFSET 0xec +#define GC_PMU_PWRDN_SCRATCH2_OFFSET 0x94 #define GC_PMU_PWRDN_SCRATCH2_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH3_OFFSET 0xf0 +#define GC_PMU_PWRDN_SCRATCH3_OFFSET 0x98 #define GC_PMU_PWRDN_SCRATCH3_DEFAULT 0x0 -#define GC_PMU_FUSE_EN_SET_OFFSET 0xf4 -#define GC_PMU_FUSE_EN_SET_DEFAULT 0x0 -#define GC_PMU_FUSE_EN_CLR_OFFSET 0xf8 -#define GC_PMU_FUSE_EN_CLR_DEFAULT 0x0 -#define GC_PMU_FUSE_START_OFFSET 0xfc +#define GC_PMU_PWRDN_SCRATCH4_OFFSET 0x9c +#define GC_PMU_PWRDN_SCRATCH4_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH5_OFFSET 0xa0 +#define GC_PMU_PWRDN_SCRATCH5_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH6_OFFSET 0xa4 +#define GC_PMU_PWRDN_SCRATCH6_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH7_OFFSET 0xa8 +#define GC_PMU_PWRDN_SCRATCH7_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH8_OFFSET 0xac +#define GC_PMU_PWRDN_SCRATCH8_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH9_OFFSET 0xb0 +#define GC_PMU_PWRDN_SCRATCH9_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH10_OFFSET 0xb4 +#define GC_PMU_PWRDN_SCRATCH10_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH11_OFFSET 0xb8 +#define GC_PMU_PWRDN_SCRATCH11_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH12_OFFSET 0xbc +#define GC_PMU_PWRDN_SCRATCH12_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH13_OFFSET 0xc0 +#define GC_PMU_PWRDN_SCRATCH13_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH14_OFFSET 0xc4 +#define GC_PMU_PWRDN_SCRATCH14_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH15_OFFSET 0xc8 +#define GC_PMU_PWRDN_SCRATCH15_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH16_OFFSET 0xcc +#define GC_PMU_PWRDN_SCRATCH16_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH17_OFFSET 0xd0 +#define GC_PMU_PWRDN_SCRATCH17_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH18_OFFSET 0xd4 +#define GC_PMU_PWRDN_SCRATCH18_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH19_OFFSET 0xd8 +#define GC_PMU_PWRDN_SCRATCH19_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH20_OFFSET 0xdc +#define GC_PMU_PWRDN_SCRATCH20_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH21_OFFSET 0xe0 +#define GC_PMU_PWRDN_SCRATCH21_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH22_OFFSET 0xe4 +#define GC_PMU_PWRDN_SCRATCH22_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH23_OFFSET 0xe8 +#define GC_PMU_PWRDN_SCRATCH23_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH24_OFFSET 0xec +#define GC_PMU_PWRDN_SCRATCH24_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH25_OFFSET 0xf0 +#define GC_PMU_PWRDN_SCRATCH25_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH26_OFFSET 0xf4 +#define GC_PMU_PWRDN_SCRATCH26_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH27_OFFSET 0xf8 +#define GC_PMU_PWRDN_SCRATCH27_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH28_OFFSET 0xfc +#define GC_PMU_PWRDN_SCRATCH28_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH29_OFFSET 0x100 +#define GC_PMU_PWRDN_SCRATCH29_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH30_OFFSET 0x104 +#define GC_PMU_PWRDN_SCRATCH30_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH31_OFFSET 0x108 +#define GC_PMU_PWRDN_SCRATCH31_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_OFFSET 0x10c +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH0_OFFSET 0x110 +#define GC_PMU_LONG_LIFE_SCRATCH0_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH1_OFFSET 0x114 +#define GC_PMU_LONG_LIFE_SCRATCH1_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH2_OFFSET 0x118 +#define GC_PMU_LONG_LIFE_SCRATCH2_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH3_OFFSET 0x11c +#define GC_PMU_LONG_LIFE_SCRATCH3_DEFAULT 0x0 +#define GC_PMU_FUSE_EN_OFFSET 0x120 +#define GC_PMU_FUSE_EN_DEFAULT 0x1 +#define GC_PMU_FUSE_START_OFFSET 0x124 #define GC_PMU_FUSE_START_DEFAULT 0x0 #define GC_PMU_FUSE_START_KEY 0x11de784a -#define GC_PMU_FUSE_CTRL_OFFSET 0x100 +#define GC_PMU_FUSE_CTRL_OFFSET 0x128 #define GC_PMU_FUSE_CTRL_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_DEV_UID0_OFFSET 0x104 +#define GC_PMU_FUSE_WR_DEV_UID0_OFFSET 0x12c #define GC_PMU_FUSE_WR_DEV_UID0_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_DEV_UID1_OFFSET 0x108 +#define GC_PMU_FUSE_WR_DEV_UID1_OFFSET 0x130 #define GC_PMU_FUSE_WR_DEV_UID1_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_ID_OFFSET 0x10c +#define GC_PMU_FUSE_WR_ID_OFFSET 0x134 #define GC_PMU_FUSE_WR_ID_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_OFFSET 0x110 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_OFFSET 0x138 #define GC_PMU_FUSE_WR_RC_OSC_26MHZ_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_OFFSET 0x114 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_OFFSET 0x13c #define GC_PMU_FUSE_WR_RC_OSC_32KHZ_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_OFFSET 0x118 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_OFFSET 0x140 #define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_LOCK_OFFSET 0x11c +#define GC_PMU_FUSE_WR_LOCK_OFFSET 0x144 #define GC_PMU_FUSE_WR_LOCK_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RSRV1_OFFSET 0x120 +#define GC_PMU_FUSE_WR_RSRV1_OFFSET 0x148 #define GC_PMU_FUSE_WR_RSRV1_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RSRV2_OFFSET 0x124 +#define GC_PMU_FUSE_WR_RSRV2_OFFSET 0x14c #define GC_PMU_FUSE_WR_RSRV2_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RSRV3_OFFSET 0x128 +#define GC_PMU_FUSE_WR_RSRV3_OFFSET 0x150 #define GC_PMU_FUSE_WR_RSRV3_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RSRV4_OFFSET 0x12c +#define GC_PMU_FUSE_WR_RSRV4_OFFSET 0x154 #define GC_PMU_FUSE_WR_RSRV4_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RSRV5_OFFSET 0x130 +#define GC_PMU_FUSE_WR_RSRV5_OFFSET 0x158 #define GC_PMU_FUSE_WR_RSRV5_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_DEV_UID0_OFFSET 0x134 +#define GC_PMU_FUSE_RD_DEV_UID0_OFFSET 0x15c #define GC_PMU_FUSE_RD_DEV_UID0_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_DEV_UID1_OFFSET 0x138 +#define GC_PMU_FUSE_RD_DEV_UID1_OFFSET 0x160 #define GC_PMU_FUSE_RD_DEV_UID1_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_ID_OFFSET 0x13c +#define GC_PMU_FUSE_RD_ID_OFFSET 0x164 #define GC_PMU_FUSE_RD_ID_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_OFFSET 0x140 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_OFFSET 0x168 #define GC_PMU_FUSE_RD_RC_OSC_26MHZ_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_OFFSET 0x144 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_OFFSET 0x16c #define GC_PMU_FUSE_RD_RC_OSC_32KHZ_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_OFFSET 0x148 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_OFFSET 0x170 #define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_LOCK_OFFSET 0x14c +#define GC_PMU_FUSE_RD_LOCK_OFFSET 0x174 #define GC_PMU_FUSE_RD_LOCK_DEFAULT 0x2 -#define GC_PMU_FUSE_RD_RSRV1_OFFSET 0x150 +#define GC_PMU_FUSE_RD_RSRV1_OFFSET 0x178 #define GC_PMU_FUSE_RD_RSRV1_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RSRV2_OFFSET 0x154 +#define GC_PMU_FUSE_RD_RSRV2_OFFSET 0x17c #define GC_PMU_FUSE_RD_RSRV2_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RSRV3_OFFSET 0x158 +#define GC_PMU_FUSE_RD_RSRV3_OFFSET 0x180 #define GC_PMU_FUSE_RD_RSRV3_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RSRV4_OFFSET 0x15c +#define GC_PMU_FUSE_RD_RSRV4_OFFSET 0x184 #define GC_PMU_FUSE_RD_RSRV4_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RSRV5_OFFSET 0x160 +#define GC_PMU_FUSE_RD_RSRV5_OFFSET 0x188 #define GC_PMU_FUSE_RD_RSRV5_DEFAULT 0x0 -#define GC_PMU_FUSE_TIMING_OFFSET 0x164 +#define GC_PMU_FUSE_TIMING_OFFSET 0x18c #define GC_PMU_FUSE_TIMING_DEFAULT 0x8007d -#define GC_PMU_FUSE_OVRD_EN_OFFSET 0x168 +#define GC_PMU_FUSE_OVRD_EN_OFFSET 0x190 #define GC_PMU_FUSE_OVRD_EN_DEFAULT 0x0 #define GC_PMU_FUSE_OVRD_EN_KEY 0x1084210 -#define GC_PMU_FUSE_OVRD_OFFSET 0x16c +#define GC_PMU_FUSE_OVRD_OFFSET 0x194 #define GC_PMU_FUSE_OVRD_DEFAULT 0x1 -#define GC_PMU_FUSE_DBG_OFFSET 0x170 +#define GC_PMU_FUSE_DBG_OFFSET 0x198 #define GC_PMU_FUSE_DBG_DEFAULT 0x0 -#define GC_PMU_ICTRL_OFFSET 0x174 -#define GC_PMU_ICTRL_DEFAULT 0x0 -#define GC_PMU_ISTAT_OFFSET 0x178 -#define GC_PMU_ISTAT_DEFAULT 0x0 -#define GC_PMU_ITCR_OFFSET 0xf00 -#define GC_PMU_ITCR_DEFAULT 0x0 -#define GC_PMU_ITOP_OFFSET 0xf04 -#define GC_PMU_ITOP_DEFAULT 0x0 +#define GC_PMU_INT_ENABLE_OFFSET 0x19c +#define GC_PMU_INT_ENABLE_DEFAULT 0x0 +#define GC_PMU_INT_STATE_OFFSET 0x1a0 +#define GC_PMU_INT_STATE_DEFAULT 0x0 +#define GC_PMU_INT_TEST_OFFSET 0x1a4 +#define GC_PMU_INT_TEST_DEFAULT 0x0 #define GC_PMU_ANTEST_TOP_CTRL_OFFSET 0x1008 #define GC_PMU_ANTEST_TOP_CTRL_DEFAULT 0x3 #define GC_PMU_ANTEST1_REGDIG_OFFSET 0x1010 #define GC_PMU_ANTEST1_REGDIG_DEFAULT 0x0 #define GC_PMU_ANTEST_FUSE_OFFSET 0x1018 #define GC_PMU_ANTEST_FUSE_DEFAULT 0x0 -#define GC_PMU_HW_CONTROLS_OFFSET 0x101c -#define GC_PMU_HW_CONTROLS_DEFAULT 0x0 -#define GC_PMU_HW_BYPASS_OFFSET 0x1020 -#define GC_PMU_HW_BYPASS_DEFAULT 0x0 -#define GC_PMU_ANTEST_TRNG_OFFSET 0x1024 +#define GC_PMU_ANTEST_TRNG_OFFSET 0x101c #define GC_PMU_ANTEST_TRNG_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_OFFSET 0x1028 +#define GC_PMU_ANTEST_TEMP_OFFSET 0x1020 #define GC_PMU_ANTEST_TEMP_DEFAULT 0x0 #define GC_PMU_TESTBUS_CTRL_OFFSET 0x2000 #define GC_PMU_TESTBUS_CTRL_DEFAULT 0x0 #define GC_PMU_CHIP_ID_OFFSET 0x1fff8 #define GC_PMU_CHIP_ID_DEFAULT 0x1485694d #define GC_PMU_VERSION_OFFSET 0x1fffc -#define GC_PMU_VERSION_DEFAULT 0x1100c244 -#define GC_RBOX_OVERRIDE_OFFSET 0x0 -#define GC_RBOX_OVERRIDE_DEFAULT 0x0 -#define GC_RBOX_OVERRIDE_VALUES_OFFSET 0x4 -#define GC_RBOX_OVERRIDE_VALUES_DEFAULT 0x0 -#define GC_RBOX_INPUT_VALUES_OFFSET 0x8 -#define GC_RBOX_INPUT_VALUES_DEFAULT 0x0 +#define GC_PMU_VERSION_DEFAULT 0x1f010370 +#define GC_RBOX_INT_ENABLE_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_OFFSET 0x4 +#define GC_RBOX_INT_STATE_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_OFFSET 0x8 +#define GC_RBOX_INT_TEST_DEFAULT 0x0 #define GC_RBOX_EC_WP_L_OFFSET 0xc #define GC_RBOX_EC_WP_L_DEFAULT 0x0 -#define GC_RBOX_FW_WP_L_OFFSET 0x10 -#define GC_RBOX_FW_WP_L_DEFAULT 0x0 -#define GC_RBOX_RESET_OFFSET 0x14 -#define GC_RBOX_RESET_DEFAULT 0x0 -#define GC_RBOX_VERSION_OFFSET 0x18 -#define GC_RBOX_VERSION_DEFAULT 0x600c16f +#define GC_RBOX_ASSERT_EC_RST_L_OFFSET 0x10 +#define GC_RBOX_ASSERT_EC_RST_L_DEFAULT 0x0 +#define GC_RBOX_CLK_DIV_LIMIT_OFFSET 0x14 +#define GC_RBOX_CLK_DIV_LIMIT_DEFAULT 0x0 +#define GC_RBOX_OVERRIDE_OUTPUT_OFFSET 0x18 +#define GC_RBOX_OVERRIDE_OUTPUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_IO_OFFSET 0x1c +#define GC_RBOX_CHECK_IO_DEFAULT 0x0 +#define GC_RBOX_STATUS_OFFSET 0x20 +#define GC_RBOX_STATUS_DEFAULT 0x0 +#define GC_RBOX_FUSE_CTRL_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_DEFAULT 0x0 +#define GC_RBOX_DEBUG_DEBOUNCE_OFFSET 0x28 +#define GC_RBOX_DEBUG_DEBOUNCE_DEFAULT 0x100 +#define GC_RBOX_DEBUG_KEY_COMBO0_OFFSET 0x2c +#define GC_RBOX_DEBUG_KEY_COMBO0_DEFAULT 0x63c0 +#define GC_RBOX_DEBUG_KEY_COMBO1_OFFSET 0x30 +#define GC_RBOX_DEBUG_KEY_COMBO1_DEFAULT 0x6300 +#define GC_RBOX_DEBUG_KEY_COMBO2_OFFSET 0x34 +#define GC_RBOX_DEBUG_KEY_COMBO2_DEFAULT 0x6300 +#define GC_RBOX_DEBUG_BLOCK_KEY_OFFSET 0x38 +#define GC_RBOX_DEBUG_BLOCK_KEY_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_DEFAULT 0x40 +#define GC_RBOX_DEBUG_TERM_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_DEFAULT 0x0 +#define GC_RBOX_DEBUG_DRIVE_OFFSET 0x44 +#define GC_RBOX_DEBUG_DRIVE_DEFAULT 0x0 +#define GC_RBOX_DEBUG_CLK10HZ_COUNT_OFFSET 0x48 +#define GC_RBOX_DEBUG_CLK10HZ_COUNT_DEFAULT 0x63ff +#define GC_RBOX_DEBUG_DELAY5MS_COUNT_OFFSET 0x4c +#define GC_RBOX_DEBUG_DELAY5MS_COUNT_DEFAULT 0x4ff +#define GC_RBOX_DEBUG_DELAY5SEC_COUNT_OFFSET 0x50 +#define GC_RBOX_DEBUG_DELAY5SEC_COUNT_DEFAULT 0x31 +#define GC_RBOX_CHECK_STATE_ENABLE_OFFSET 0x54 +#define GC_RBOX_CHECK_STATE_ENABLE_DEFAULT 0x0 +#define GC_RBOX_CHECK_STATE0_OFFSET 0x58 +#define GC_RBOX_CHECK_STATE0_DEFAULT 0x0 +#define GC_RBOX_CHECK_STATE1_OFFSET 0x5c +#define GC_RBOX_CHECK_STATE1_DEFAULT 0x0 +#define GC_RBOX_CHECK_STATE2_OFFSET 0x60 +#define GC_RBOX_CHECK_STATE2_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DEBOUNCE_OFFSET 0x64 +#define GC_RBOX_CONFIG_DEBOUNCE_DEFAULT 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO0_OFFSET 0x68 +#define GC_RBOX_CONFIG_KEY_COMBO0_DEFAULT 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO1_OFFSET 0x6c +#define GC_RBOX_CONFIG_KEY_COMBO1_DEFAULT 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO2_OFFSET 0x70 +#define GC_RBOX_CONFIG_KEY_COMBO2_DEFAULT 0x0 +#define GC_RBOX_CONFIG_BLOCK_KEY_OFFSET 0x74 +#define GC_RBOX_CONFIG_BLOCK_KEY_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_DEFAULT 0x40 +#define GC_RBOX_CONFIG_TERM_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DRIVE_OFFSET 0x80 +#define GC_RBOX_CONFIG_DRIVE_DEFAULT 0x0 +#define GC_RBOX_CONFIG_CLK10HZ_COUNT_OFFSET 0x84 +#define GC_RBOX_CONFIG_CLK10HZ_COUNT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DELAY5MS_COUNT_OFFSET 0x88 +#define GC_RBOX_CONFIG_DELAY5MS_COUNT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DELAY5SEC_COUNT_OFFSET 0x8c +#define GC_RBOX_CONFIG_DELAY5SEC_COUNT_DEFAULT 0x0 +#define GC_RBOX_VERSION_OFFSET 0x90 +#define GC_RBOX_VERSION_DEFAULT 0x23010772 +#define GC_RDD_VERSION_OFFSET 0x0 +#define GC_RDD_VERSION_DEFAULT 0x500f210 +#define GC_RDD_INT_ENABLE_OFFSET 0x4 +#define GC_RDD_INT_ENABLE_DEFAULT 0x0 +#define GC_RDD_INT_STATE_OFFSET 0x8 +#define GC_RDD_INT_STATE_DEFAULT 0x0 +#define GC_RDD_INT_TEST_OFFSET 0xc +#define GC_RDD_INT_TEST_DEFAULT 0x0 +#define GC_RDD_MAX_WAIT_TIME_COUNTER_OFFSET 0x10 +#define GC_RDD_MAX_WAIT_TIME_COUNTER_DEFAULT 0xc80 +#define GC_RDD_CUR_WAIT_TIME_COUNTER_OFFSET 0x14 +#define GC_RDD_CUR_WAIT_TIME_COUNTER_DEFAULT 0x0 +#define GC_RDD_THRESHOLD_COMPARATOR_OFFSET 0x18 +#define GC_RDD_THRESHOLD_COMPARATOR_DEFAULT 0x0 +#define GC_RDD_CUR_STABLE_STATE_OFFSET 0x1c +#define GC_RDD_CUR_STABLE_STATE_DEFAULT 0x4 #define GC_RTC_CTRL_OFFSET 0x0 -#define GC_RTC_CTRL_DEFAULT 0x22f01 +#define GC_RTC_CTRL_DEFAULT 0x0 #define GC_RTC_PINMUX_EN_OFFSET 0x4 #define GC_RTC_PINMUX_EN_DEFAULT 0x0 -#define GC_RTC_SETHOLD_OFFSET 0x8 -#define GC_RTC_SETHOLD_DEFAULT 0x0 -#define GC_RTC_CLRHOLD_OFFSET 0xc -#define GC_RTC_CLRHOLD_DEFAULT 0x0 +#define GC_RTC_PULSE_STRETCH_OFFSET 0x8 +#define GC_RTC_PULSE_STRETCH_DEFAULT 0x0 +#define GC_RTC_SW_TRIM_EN_OFFSET 0xc +#define GC_RTC_SW_TRIM_EN_DEFAULT 0x0 +#define GC_RTC_SW_TRIM_COUNTER_OFFSET 0x10 +#define GC_RTC_SW_TRIM_COUNTER_DEFAULT 0x0 #define GC_SHA_CFG_MSGLEN_LO_OFFSET 0x0 #define GC_SHA_CFG_MSGLEN_LO_DEFAULT 0x0 #define GC_SHA_CFG_MSGLEN_HI_OFFSET 0x4 @@ -2596,54 +3720,30 @@ #define GC_SHA_STS_H6_DEFAULT 0x0 #define GC_SHA_STS_H7_OFFSET 0x30 #define GC_SHA_STS_H7_DEFAULT 0x0 -#define GC_SHA_STS_W0_OFFSET 0x34 -#define GC_SHA_STS_W0_DEFAULT 0x0 -#define GC_SHA_STS_W1_OFFSET 0x38 -#define GC_SHA_STS_W1_DEFAULT 0x0 -#define GC_SHA_STS_W2_OFFSET 0x3c -#define GC_SHA_STS_W2_DEFAULT 0x0 -#define GC_SHA_STS_W3_OFFSET 0x40 -#define GC_SHA_STS_W3_DEFAULT 0x0 -#define GC_SHA_STS_W4_OFFSET 0x44 -#define GC_SHA_STS_W4_DEFAULT 0x0 -#define GC_SHA_STS_W5_OFFSET 0x48 -#define GC_SHA_STS_W5_DEFAULT 0x0 -#define GC_SHA_STS_W6_OFFSET 0x4c -#define GC_SHA_STS_W6_DEFAULT 0x0 -#define GC_SHA_STS_W7_OFFSET 0x50 -#define GC_SHA_STS_W7_DEFAULT 0x0 -#define GC_SHA_STS_W8_OFFSET 0x54 -#define GC_SHA_STS_W8_DEFAULT 0x0 -#define GC_SHA_STS_W9_OFFSET 0x58 -#define GC_SHA_STS_W9_DEFAULT 0x0 -#define GC_SHA_STS_W10_OFFSET 0x5c -#define GC_SHA_STS_W10_DEFAULT 0x0 -#define GC_SHA_STS_W11_OFFSET 0x60 -#define GC_SHA_STS_W11_DEFAULT 0x0 -#define GC_SHA_STS_W12_OFFSET 0x64 -#define GC_SHA_STS_W12_DEFAULT 0x0 -#define GC_SHA_STS_W13_OFFSET 0x68 -#define GC_SHA_STS_W13_DEFAULT 0x0 -#define GC_SHA_STS_W14_OFFSET 0x6c -#define GC_SHA_STS_W14_DEFAULT 0x0 -#define GC_SHA_STS_W15_OFFSET 0x70 -#define GC_SHA_STS_W15_DEFAULT 0x0 -#define GC_SHA_STS_A_OFFSET 0x74 -#define GC_SHA_STS_A_DEFAULT 0x0 -#define GC_SHA_STS_B_OFFSET 0x78 -#define GC_SHA_STS_B_DEFAULT 0x0 -#define GC_SHA_STS_C_OFFSET 0x7c -#define GC_SHA_STS_C_DEFAULT 0x0 -#define GC_SHA_STS_D_OFFSET 0x80 -#define GC_SHA_STS_D_DEFAULT 0x0 -#define GC_SHA_STS_E_OFFSET 0x84 -#define GC_SHA_STS_E_DEFAULT 0x0 -#define GC_SHA_STS_F_OFFSET 0x88 -#define GC_SHA_STS_F_DEFAULT 0x0 -#define GC_SHA_STS_G_OFFSET 0x8c -#define GC_SHA_STS_G_DEFAULT 0x0 -#define GC_SHA_STS_H_OFFSET 0x90 -#define GC_SHA_STS_H_DEFAULT 0x0 +#define GC_SHA_KEY_W0_OFFSET 0x100 +#define GC_SHA_KEY_W0_DEFAULT 0x0 +#define GC_SHA_KEY_W1_OFFSET 0x104 +#define GC_SHA_KEY_W1_DEFAULT 0x0 +#define GC_SHA_KEY_W2_OFFSET 0x108 +#define GC_SHA_KEY_W2_DEFAULT 0x0 +#define GC_SHA_KEY_W3_OFFSET 0x10c +#define GC_SHA_KEY_W3_DEFAULT 0x0 +#define GC_SHA_KEY_W4_OFFSET 0x110 +#define GC_SHA_KEY_W4_DEFAULT 0x0 +#define GC_SHA_KEY_W5_OFFSET 0x114 +#define GC_SHA_KEY_W5_DEFAULT 0x0 +#define GC_SHA_KEY_W6_OFFSET 0x118 +#define GC_SHA_KEY_W6_DEFAULT 0x0 +#define GC_SHA_KEY_W7_OFFSET 0x11c +#define GC_SHA_KEY_W7_DEFAULT 0x0 +#define GC_SHA_HKEY_INDEX_OFFSET 0x120 +#define GC_SHA_HKEY_INDEX_DEFAULT 0x0 +#define GC_SHA_CERT_DIGPTR_OFFSET 0x124 +#define GC_SHA_CERT_DIGPTR_DEFAULT 0x0 +#define GC_SHA_CERT_KEYPTR_OFFSET 0x128 +#define GC_SHA_CERT_KEYPTR_DEFAULT 0x0 +#define GC_SHA_STS_OFFSET 0x130 +#define GC_SHA_STS_DEFAULT 0x1 #define GC_SHA_ITCR_OFFSET 0xf00 #define GC_SHA_ITCR_DEFAULT 0x0 #define GC_SHA_ITOP_OFFSET 0xf04 @@ -2670,7 +3770,7 @@ #define GC_SPI_TX_DATA_OFFSET 0x1000 #define GC_SPI_RX_DATA_OFFSET 0x1080 #define GC_SPS_CTRL_OFFSET 0x0 -#define GC_SPS_CTRL_DEFAULT 0x181 +#define GC_SPS_CTRL_DEFAULT 0x1 #define GC_SPS_DUMMY_WORD_OFFSET 0x4 #define GC_SPS_DUMMY_WORD_DEFAULT 0xff #define GC_SPS_STATUS01_OFFSET 0x8 @@ -2707,76 +3807,207 @@ #define GC_SPS_RXFIFO_WPTR_DEFAULT 0x0 #define GC_SPS_RXFIFO_THRESHOLD_OFFSET 0x48 #define GC_SPS_RXFIFO_THRESHOLD_DEFAULT 0x0 -#define GC_SPS_ROM_REGION0_CTRL_OFFSET 0x4c -#define GC_SPS_ROM_REGION0_CTRL_DEFAULT 0x0 -#define GC_SPS_ROM_REGION0_ROM_BASE_OFFSET 0x50 -#define GC_SPS_ROM_REGION0_ROM_BASE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION0_SP_BASE_OFFSET 0x54 -#define GC_SPS_ROM_REGION0_SP_BASE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION0_SIZE_OFFSET 0x58 -#define GC_SPS_ROM_REGION0_SIZE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION0_INT_LVL_OFFSET 0x5c -#define GC_SPS_ROM_REGION0_INT_LVL_DEFAULT 0x0 -#define GC_SPS_ROM_REGION1_CTRL_OFFSET 0x60 -#define GC_SPS_ROM_REGION1_CTRL_DEFAULT 0x0 -#define GC_SPS_ROM_REGION1_ROM_BASE_OFFSET 0x64 -#define GC_SPS_ROM_REGION1_ROM_BASE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION1_SP_BASE_OFFSET 0x68 -#define GC_SPS_ROM_REGION1_SP_BASE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION1_SIZE_OFFSET 0x6c -#define GC_SPS_ROM_REGION1_SIZE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION1_INT_LVL_OFFSET 0x70 -#define GC_SPS_ROM_REGION1_INT_LVL_DEFAULT 0x0 -#define GC_SPS_ROM_REGION2_CTRL_OFFSET 0x74 -#define GC_SPS_ROM_REGION2_CTRL_DEFAULT 0x0 -#define GC_SPS_ROM_REGION2_ROM_BASE_OFFSET 0x78 -#define GC_SPS_ROM_REGION2_ROM_BASE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION2_SP_BASE_OFFSET 0x7c -#define GC_SPS_ROM_REGION2_SP_BASE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION2_SIZE_OFFSET 0x80 -#define GC_SPS_ROM_REGION2_SIZE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION2_INT_LVL_OFFSET 0x84 -#define GC_SPS_ROM_REGION2_INT_LVL_DEFAULT 0x0 -#define GC_SPS_ROM_REGION3_CTRL_OFFSET 0x88 -#define GC_SPS_ROM_REGION3_CTRL_DEFAULT 0x0 -#define GC_SPS_ROM_REGION3_ROM_BASE_OFFSET 0x8c -#define GC_SPS_ROM_REGION3_ROM_BASE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION3_SP_BASE_OFFSET 0x90 -#define GC_SPS_ROM_REGION3_SP_BASE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION3_SIZE_OFFSET 0x94 -#define GC_SPS_ROM_REGION3_SIZE_DEFAULT 0x0 -#define GC_SPS_ROM_REGION3_INT_LVL_OFFSET 0x98 -#define GC_SPS_ROM_REGION3_INT_LVL_DEFAULT 0x0 -#define GC_SPS_ROM_STATUS_OFFSET 0x9c -#define GC_SPS_ROM_STATUS_DEFAULT 0x0 -#define GC_SPS_ROM_SET_RDY_OFFSET 0xa0 -#define GC_SPS_ROM_SET_RDY_DEFAULT 0x1 -#define GC_SPS_ROM_MEM_CMD_OP_OFFSET 0xa4 -#define GC_SPS_ROM_MEM_CMD_OP_DEFAULT 0x0 -#define GC_SPS_ROM_MEM_CMD_ADDR_OFFSET 0xa8 -#define GC_SPS_ROM_MEM_CMD_ADDR_DEFAULT 0x0 -#define GC_SPS_ROM_MEM_CMD_REGION_OFFSET 0xac -#define GC_SPS_ROM_MEM_CMD_REGION_DEFAULT 0x0 -#define GC_SPS_ROM_MEM_CMD_LEN_OFFSET 0xb0 -#define GC_SPS_ROM_MEM_CMD_LEN_DEFAULT 0x0 -#define GC_SPS_OVRD_OFFSET 0xb4 +#define GC_SPS_OVRD_OFFSET 0x4c #define GC_SPS_OVRD_DEFAULT 0x0 -#define GC_SPS_VAL_OFFSET 0xb8 +#define GC_SPS_VAL_OFFSET 0x50 #define GC_SPS_VAL_DEFAULT 0x0 -#define GC_SPS_ICTRL_OFFSET 0xbc -#define GC_SPS_ICTRL_DEFAULT 0x0 -#define GC_SPS_ISTATE_OFFSET 0xc0 +#define GC_SPS_ISTATE_OFFSET 0x54 #define GC_SPS_ISTATE_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_DEFAULT 0x0 -#define GC_SPS_ITCR_OFFSET 0xf00 +#define GC_SPS_ITCR_OFFSET 0x5c #define GC_SPS_ITCR_DEFAULT 0x0 -#define GC_SPS_ITOP_OFFSET 0xf04 +#define GC_SPS_ITOP_OFFSET 0x60 #define GC_SPS_ITOP_DEFAULT 0x0 +#define GC_SPS_ICTRL_OFFSET 0x64 +#define GC_SPS_ICTRL_DEFAULT 0x0 +#define GC_SPS_EEPROM_CTRL_OFFSET 0x400 +#define GC_SPS_EEPROM_CTRL_DEFAULT 0x80 +#define GC_SPS_MAILBOX_RD_OPCODE_OFFSET 0x404 +#define GC_SPS_MAILBOX_RD_OPCODE_DEFAULT 0x0 +#define GC_SPS_FAST_DUAL_RD_OPCODE_OFFSET 0x408 +#define GC_SPS_FAST_DUAL_RD_OPCODE_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE0_OFFSET 0x40c +#define GC_SPS_BUSY_OPCODE0_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE1_OFFSET 0x410 +#define GC_SPS_BUSY_OPCODE1_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE2_OFFSET 0x414 +#define GC_SPS_BUSY_OPCODE2_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE3_OFFSET 0x418 +#define GC_SPS_BUSY_OPCODE3_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE4_OFFSET 0x41c +#define GC_SPS_BUSY_OPCODE4_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE5_OFFSET 0x420 +#define GC_SPS_BUSY_OPCODE5_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE6_OFFSET 0x424 +#define GC_SPS_BUSY_OPCODE6_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE7_OFFSET 0x428 +#define GC_SPS_BUSY_OPCODE7_DEFAULT 0x0 +#define GC_SPS_EEPROM_STATUS_OFFSET 0x42c +#define GC_SPS_EEPROM_STATUS_DEFAULT 0x0 +#define GC_SPS_EEPROM_BUSY_STATUS_OFFSET 0x430 +#define GC_SPS_EEPROM_BUSY_STATUS_DEFAULT 0x0 +#define GC_SPS_EEPROM_BUSY_BIT_VECTOR_OFFSET 0x434 +#define GC_SPS_EEPROM_BUSY_BIT_VECTOR_DEFAULT 0x0 +#define GC_SPS_EEPROM_WEL_STATUS_OFFSET 0x438 +#define GC_SPS_EEPROM_WEL_STATUS_DEFAULT 0x0 +#define GC_SPS_JEDEC_ID0_OFFSET 0x43c +#define GC_SPS_JEDEC_ID0_DEFAULT 0x0 +#define GC_SPS_JEDEC_ID1_OFFSET 0x440 +#define GC_SPS_JEDEC_ID1_DEFAULT 0x0 +#define GC_SPS_JEDEC_ID2_OFFSET 0x444 +#define GC_SPS_JEDEC_ID2_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM0_OFFSET 0x448 +#define GC_SPS_SELF_DISCV_PARAM0_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM1_OFFSET 0x44c +#define GC_SPS_SELF_DISCV_PARAM1_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM2_OFFSET 0x450 +#define GC_SPS_SELF_DISCV_PARAM2_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM3_OFFSET 0x454 +#define GC_SPS_SELF_DISCV_PARAM3_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM4_OFFSET 0x458 +#define GC_SPS_SELF_DISCV_PARAM4_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM5_OFFSET 0x45c +#define GC_SPS_SELF_DISCV_PARAM5_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM6_OFFSET 0x460 +#define GC_SPS_SELF_DISCV_PARAM6_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM7_OFFSET 0x464 +#define GC_SPS_SELF_DISCV_PARAM7_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM8_OFFSET 0x468 +#define GC_SPS_SELF_DISCV_PARAM8_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM9_OFFSET 0x46c +#define GC_SPS_SELF_DISCV_PARAM9_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM10_OFFSET 0x470 +#define GC_SPS_SELF_DISCV_PARAM10_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM11_OFFSET 0x474 +#define GC_SPS_SELF_DISCV_PARAM11_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM12_OFFSET 0x478 +#define GC_SPS_SELF_DISCV_PARAM12_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM13_OFFSET 0x47c +#define GC_SPS_SELF_DISCV_PARAM13_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM14_OFFSET 0x480 +#define GC_SPS_SELF_DISCV_PARAM14_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM15_OFFSET 0x484 +#define GC_SPS_SELF_DISCV_PARAM15_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM16_OFFSET 0x488 +#define GC_SPS_SELF_DISCV_PARAM16_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM17_OFFSET 0x48c +#define GC_SPS_SELF_DISCV_PARAM17_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM18_OFFSET 0x490 +#define GC_SPS_SELF_DISCV_PARAM18_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM19_OFFSET 0x494 +#define GC_SPS_SELF_DISCV_PARAM19_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM20_OFFSET 0x498 +#define GC_SPS_SELF_DISCV_PARAM20_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM21_OFFSET 0x49c +#define GC_SPS_SELF_DISCV_PARAM21_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM22_OFFSET 0x4a0 +#define GC_SPS_SELF_DISCV_PARAM22_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM23_OFFSET 0x4a4 +#define GC_SPS_SELF_DISCV_PARAM23_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM24_OFFSET 0x4a8 +#define GC_SPS_SELF_DISCV_PARAM24_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM25_OFFSET 0x4ac +#define GC_SPS_SELF_DISCV_PARAM25_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM26_OFFSET 0x4b0 +#define GC_SPS_SELF_DISCV_PARAM26_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM27_OFFSET 0x4b4 +#define GC_SPS_SELF_DISCV_PARAM27_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM28_OFFSET 0x4b8 +#define GC_SPS_SELF_DISCV_PARAM28_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM29_OFFSET 0x4bc +#define GC_SPS_SELF_DISCV_PARAM29_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM30_OFFSET 0x4c0 +#define GC_SPS_SELF_DISCV_PARAM30_DEFAULT 0x0 +#define GC_SPS_SELF_DISCV_PARAM31_OFFSET 0x4c4 +#define GC_SPS_SELF_DISCV_PARAM31_DEFAULT 0x0 +#define GC_SPS_UNMAPPED_RETURN_VAL_OFFSET 0x4c8 +#define GC_SPS_UNMAPPED_RETURN_VAL_DEFAULT 0x0 +#define GC_SPS_RAM_VIRTUAL_PAGE0_OFFSET 0x4cc +#define GC_SPS_RAM_VIRTUAL_PAGE0_DEFAULT 0x0 +#define GC_SPS_RAM_VIRTUAL_PAGE1_OFFSET 0x4d0 +#define GC_SPS_RAM_VIRTUAL_PAGE1_DEFAULT 0x0 +#define GC_SPS_RAM_VIRTUAL_PAGE2_OFFSET 0x4d4 +#define GC_SPS_RAM_VIRTUAL_PAGE2_DEFAULT 0x0 +#define GC_SPS_RAM_VIRTUAL_PAGE3_OFFSET 0x4d8 +#define GC_SPS_RAM_VIRTUAL_PAGE3_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE0_OFFSET 0x4dc +#define GC_SPS_RAM_CTRL_PAGE0_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE1_OFFSET 0x4e0 +#define GC_SPS_RAM_CTRL_PAGE1_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE2_OFFSET 0x4e4 +#define GC_SPS_RAM_CTRL_PAGE2_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE3_OFFSET 0x4e8 +#define GC_SPS_RAM_CTRL_PAGE3_DEFAULT 0x0 +#define GC_SPS_INT_FLASH_BASE_PAGE_OFFSET 0x4ec +#define GC_SPS_INT_FLASH_BASE_PAGE_DEFAULT 0x0 +#define GC_SPS_INT_FLASH_LIMIT_PAGE_OFFSET 0x4f0 +#define GC_SPS_INT_FLASH_LIMIT_PAGE_DEFAULT 0x0 +#define GC_SPS_EXT_FLASH_BASE_PAGE_OFFSET 0x4f4 +#define GC_SPS_EXT_FLASH_BASE_PAGE_DEFAULT 0x0 +#define GC_SPS_EXT_FLASH_LIMIT_PAGE_OFFSET 0x4f8 +#define GC_SPS_EXT_FLASH_LIMIT_PAGE_DEFAULT 0x0 +#define GC_SPS_INT_FLASH_TRANS_BIT_VECTOR_OFFSET 0x4fc +#define GC_SPS_INT_FLASH_TRANS_BIT_VECTOR_DEFAULT 0x0 +#define GC_SPS_INT_FLASH_TRANS_ADDR_OFFSET 0x500 +#define GC_SPS_INT_FLASH_TRANS_ADDR_DEFAULT 0x0 +#define GC_SPS_EXT_FLASH_TRANS_BIT_VECTOR_OFFSET 0x504 +#define GC_SPS_EXT_FLASH_TRANS_BIT_VECTOR_DEFAULT 0x0 +#define GC_SPS_EXT_FLASH_TRANS_ADDR_OFFSET 0x508 +#define GC_SPS_EXT_FLASH_TRANS_ADDR_DEFAULT 0x0 +#define GC_SPS_CMD_MEM_RPTR_OFFSET 0x50c +#define GC_SPS_CMD_MEM_RPTR_DEFAULT 0x0 +#define GC_SPS_CMD_ADDR_FIFO_OFFSET 0x510 +#define GC_SPS_CMD_ADDR_FIFO_DEFAULT 0x0 +#define GC_SPS_CMD_ADDR_FIFO_EMPTY_OFFSET 0x514 +#define GC_SPS_CMD_ADDR_FIFO_EMPTY_DEFAULT 0x0 +#define GC_SPS_FDA_MSB_ROTATE_BASE_ADDR_OFFSET 0x518 +#define GC_SPS_FDA_MSB_ROTATE_BASE_ADDR_DEFAULT 0x0 +#define GC_SPS_FDA_MSB_LEVEL2_ROTATE_BASE_ADDR_OFFSET 0x51c +#define GC_SPS_FDA_MSB_LEVEL2_ROTATE_BASE_ADDR_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE0_OFFSET 0x520 +#define GC_SPS_PASSTHRU_FILTER_RULE0_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE1_OFFSET 0x524 +#define GC_SPS_PASSTHRU_FILTER_RULE1_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE2_OFFSET 0x528 +#define GC_SPS_PASSTHRU_FILTER_RULE2_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE3_OFFSET 0x52c +#define GC_SPS_PASSTHRU_FILTER_RULE3_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE4_OFFSET 0x530 +#define GC_SPS_PASSTHRU_FILTER_RULE4_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE5_OFFSET 0x534 +#define GC_SPS_PASSTHRU_FILTER_RULE5_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE6_OFFSET 0x538 +#define GC_SPS_PASSTHRU_FILTER_RULE6_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE7_OFFSET 0x53c +#define GC_SPS_PASSTHRU_FILTER_RULE7_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE8_OFFSET 0x540 +#define GC_SPS_PASSTHRU_FILTER_RULE8_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE9_OFFSET 0x544 +#define GC_SPS_PASSTHRU_FILTER_RULE9_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE10_OFFSET 0x548 +#define GC_SPS_PASSTHRU_FILTER_RULE10_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE11_OFFSET 0x54c +#define GC_SPS_PASSTHRU_FILTER_RULE11_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE12_OFFSET 0x550 +#define GC_SPS_PASSTHRU_FILTER_RULE12_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE13_OFFSET 0x554 +#define GC_SPS_PASSTHRU_FILTER_RULE13_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE14_OFFSET 0x558 +#define GC_SPS_PASSTHRU_FILTER_RULE14_DEFAULT 0x0 +#define GC_SPS_PASSTHRU_FILTER_RULE15_OFFSET 0x55c +#define GC_SPS_PASSTHRU_FILTER_RULE15_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_ENABLE_OFFSET 0x560 +#define GC_SPS_EEPROM_INT_ENABLE_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_STATE_OFFSET 0x564 +#define GC_SPS_EEPROM_INT_STATE_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_TEST_OFFSET 0x568 +#define GC_SPS_EEPROM_INT_TEST_DEFAULT 0x0 #define GC_SPS_DATA_OFFSET 0x1000 #define GC_SPS_TX_DATA_OFFSET 0x1000 #define GC_SPS_RX_DATA_OFFSET 0x1400 #define GC_SPS_ROM_SP_OFFSET 0x1000 +#define GC_SPS_ROM_CMD_OFFSET 0x2000 #define GC_SWDP_TRICKBOX_HALT_OFFSET 0x0 #define GC_SWDP_TRICKBOX_HALT_DEFAULT 0x0 #define GC_SWDP_TRICKBOX_UART_OFFSET 0x4 @@ -2800,17 +4031,17 @@ #define GC_SWDP_HEADER_MD5SUM_OFFSET 0x28 #define GC_SWDP_HEADER_MD5SUM_DEFAULT 0x0 #define GC_SWDP_P4_LAST_SYNC_OFFSET 0x2c -#define GC_SWDP_P4_LAST_SYNC_DEFAULT 0xc583 +#define GC_SWDP_P4_LAST_SYNC_DEFAULT 0x10777 #define GC_SWDP_BUILD_DATE_OFFSET 0x30 -#define GC_SWDP_BUILD_DATE_DEFAULT 0x1335498 +#define GC_SWDP_BUILD_DATE_DEFAULT 0x13379c9 #define GC_SWDP_BUILD_TIME_OFFSET 0x34 -#define GC_SWDP_BUILD_TIME_DEFAULT 0x1e800 +#define GC_SWDP_BUILD_TIME_DEFAULT 0x390f7 #define GC_SWDP_A1_DIO8_OFFSET 0x38 #define GC_SWDP_A1_DIO8_DEFAULT 0x0 #define GC_SWDP_A1_CHANNEL_SEL_OFFSET 0x3c #define GC_SWDP_A1_CHANNEL_SEL_DEFAULT 0x0 #define GC_TEMP_VERSION_OFFSET 0x0 -#define GC_TEMP_VERSION_DEFAULT 0xd00c178 +#define GC_TEMP_VERSION_DEFAULT 0x400ed82 #define GC_TEMP_ADC_INT_ENABLE_OFFSET 0x4 #define GC_TEMP_ADC_INT_ENABLE_DEFAULT 0x0 #define GC_TEMP_ADC_INT_STATE_OFFSET 0x8 @@ -2939,10 +4170,8 @@ #define GC_TIMELS_TIMER0_IPR_DEFAULT 0x0 #define GC_TIMELS_TIMER0_IAR_OFFSET 0x24 #define GC_TIMELS_TIMER0_IAR_DEFAULT 0x0 -#define GC_TIMELS_TIMER0_SETHOLD_OFFSET 0x28 -#define GC_TIMELS_TIMER0_SETHOLD_DEFAULT 0x0 -#define GC_TIMELS_TIMER0_CLRHOLD_OFFSET 0x2c -#define GC_TIMELS_TIMER0_CLRHOLD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_WAKEUP_ACK_OFFSET 0x28 +#define GC_TIMELS_TIMER0_WAKEUP_ACK_DEFAULT 0x0 #define GC_TIMELS_TIMER1_CONTROL_OFFSET 0x40 #define GC_TIMELS_TIMER1_CONTROL_DEFAULT 0x0 #define GC_TIMELS_TIMER1_STATUS_OFFSET 0x44 @@ -2963,201 +4192,139 @@ #define GC_TIMELS_TIMER1_IPR_DEFAULT 0x0 #define GC_TIMELS_TIMER1_IAR_OFFSET 0x64 #define GC_TIMELS_TIMER1_IAR_DEFAULT 0x0 -#define GC_TIMELS_TIMER1_SETHOLD_OFFSET 0x68 -#define GC_TIMELS_TIMER1_SETHOLD_DEFAULT 0x0 -#define GC_TIMELS_TIMER1_CLRHOLD_OFFSET 0x6c -#define GC_TIMELS_TIMER1_CLRHOLD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_WAKEUP_ACK_OFFSET 0x68 +#define GC_TIMELS_TIMER1_WAKEUP_ACK_DEFAULT 0x0 #define GC_TIMELS_ITCR_OFFSET 0xf00 #define GC_TIMELS_ITCR_DEFAULT 0x0 #define GC_TIMELS_ITOP_OFFSET 0xf04 #define GC_TIMELS_ITOP_DEFAULT 0x0 +#define GC_TIMEUS_VERSION_OFFSET 0x0 +#define GC_TIMEUS_VERSION_DEFAULT 0x800ea91 +#define GC_TIMEUS_INT_ENABLE_OFFSET 0x4 +#define GC_TIMEUS_INT_ENABLE_DEFAULT 0x0 +#define GC_TIMEUS_INT_STATE_OFFSET 0x8 +#define GC_TIMEUS_INT_STATE_DEFAULT 0x0 +#define GC_TIMEUS_INT_TEST_OFFSET 0xc +#define GC_TIMEUS_INT_TEST_DEFAULT 0x0 +#define GC_TIMEUS_ENABLE_CNTR0_OFFSET 0x100 +#define GC_TIMEUS_ENABLE_CNTR0_DEFAULT 0x0 +#define GC_TIMEUS_ONESHOT_MODE_CNTR0_OFFSET 0x104 +#define GC_TIMEUS_ONESHOT_MODE_CNTR0_DEFAULT 0x0 +#define GC_TIMEUS_MAXVAL_CNTR0_OFFSET 0x108 +#define GC_TIMEUS_MAXVAL_CNTR0_DEFAULT 0x2710 +#define GC_TIMEUS_PROGVAL_CNTR0_OFFSET 0x10c +#define GC_TIMEUS_PROGVAL_CNTR0_DEFAULT 0x3e8 +#define GC_TIMEUS_DIVIDER_CNTR0_OFFSET 0x110 +#define GC_TIMEUS_DIVIDER_CNTR0_DEFAULT 0x1 +#define GC_TIMEUS_CUR_MAJOR_CNTR0_OFFSET 0x114 +#define GC_TIMEUS_CUR_MAJOR_CNTR0_DEFAULT 0x0 +#define GC_TIMEUS_CUR_MINOR_CNTR0_OFFSET 0x118 +#define GC_TIMEUS_CUR_MINOR_CNTR0_DEFAULT 0x0 +#define GC_TIMEUS_ENABLE_CNTR1_OFFSET 0x200 +#define GC_TIMEUS_ENABLE_CNTR1_DEFAULT 0x0 +#define GC_TIMEUS_ONESHOT_MODE_CNTR1_OFFSET 0x204 +#define GC_TIMEUS_ONESHOT_MODE_CNTR1_DEFAULT 0x0 +#define GC_TIMEUS_MAXVAL_CNTR1_OFFSET 0x208 +#define GC_TIMEUS_MAXVAL_CNTR1_DEFAULT 0x2710 +#define GC_TIMEUS_PROGVAL_CNTR1_OFFSET 0x20c +#define GC_TIMEUS_PROGVAL_CNTR1_DEFAULT 0x3e8 +#define GC_TIMEUS_DIVIDER_CNTR1_OFFSET 0x210 +#define GC_TIMEUS_DIVIDER_CNTR1_DEFAULT 0x1 +#define GC_TIMEUS_CUR_MAJOR_CNTR1_OFFSET 0x214 +#define GC_TIMEUS_CUR_MAJOR_CNTR1_DEFAULT 0x0 +#define GC_TIMEUS_CUR_MINOR_CNTR1_OFFSET 0x218 +#define GC_TIMEUS_CUR_MINOR_CNTR1_DEFAULT 0x0 +#define GC_TIMEUS_ENABLE_CNTR2_OFFSET 0x300 +#define GC_TIMEUS_ENABLE_CNTR2_DEFAULT 0x0 +#define GC_TIMEUS_ONESHOT_MODE_CNTR2_OFFSET 0x304 +#define GC_TIMEUS_ONESHOT_MODE_CNTR2_DEFAULT 0x0 +#define GC_TIMEUS_MAXVAL_CNTR2_OFFSET 0x308 +#define GC_TIMEUS_MAXVAL_CNTR2_DEFAULT 0x2710 +#define GC_TIMEUS_PROGVAL_CNTR2_OFFSET 0x30c +#define GC_TIMEUS_PROGVAL_CNTR2_DEFAULT 0x3e8 +#define GC_TIMEUS_DIVIDER_CNTR2_OFFSET 0x310 +#define GC_TIMEUS_DIVIDER_CNTR2_DEFAULT 0x1 +#define GC_TIMEUS_CUR_MAJOR_CNTR2_OFFSET 0x314 +#define GC_TIMEUS_CUR_MAJOR_CNTR2_DEFAULT 0x0 +#define GC_TIMEUS_CUR_MINOR_CNTR2_OFFSET 0x318 +#define GC_TIMEUS_CUR_MINOR_CNTR2_DEFAULT 0x0 +#define GC_TIMEUS_ENABLE_CNTR3_OFFSET 0x400 +#define GC_TIMEUS_ENABLE_CNTR3_DEFAULT 0x0 +#define GC_TIMEUS_ONESHOT_MODE_CNTR3_OFFSET 0x404 +#define GC_TIMEUS_ONESHOT_MODE_CNTR3_DEFAULT 0x0 +#define GC_TIMEUS_MAXVAL_CNTR3_OFFSET 0x408 +#define GC_TIMEUS_MAXVAL_CNTR3_DEFAULT 0x2710 +#define GC_TIMEUS_PROGVAL_CNTR3_OFFSET 0x40c +#define GC_TIMEUS_PROGVAL_CNTR3_DEFAULT 0x3e8 +#define GC_TIMEUS_DIVIDER_CNTR3_OFFSET 0x410 +#define GC_TIMEUS_DIVIDER_CNTR3_DEFAULT 0x1 +#define GC_TIMEUS_CUR_MAJOR_CNTR3_OFFSET 0x414 +#define GC_TIMEUS_CUR_MAJOR_CNTR3_DEFAULT 0x0 +#define GC_TIMEUS_CUR_MINOR_CNTR3_OFFSET 0x418 +#define GC_TIMEUS_CUR_MINOR_CNTR3_DEFAULT 0x0 #define GC_TRNG_VERSION_OFFSET 0x0 -#define GC_TRNG_VERSION_DEFAULT 0x700c241 +#define GC_TRNG_VERSION_DEFAULT 0x14010564 #define GC_TRNG_INT_ENABLE_OFFSET 0x4 #define GC_TRNG_INT_ENABLE_DEFAULT 0x0 #define GC_TRNG_INT_STATE_OFFSET 0x8 #define GC_TRNG_INT_STATE_DEFAULT 0x0 #define GC_TRNG_INT_TEST_OFFSET 0xc #define GC_TRNG_INT_TEST_DEFAULT 0x0 -#define GC_TRNG_GO_EVENT_OFFSET 0x10 +#define GC_TRNG_POST_PROCESSING_CTRL_OFFSET 0x10 +#define GC_TRNG_POST_PROCESSING_CTRL_DEFAULT 0x3f +#define GC_TRNG_GO_EVENT_OFFSET 0x14 #define GC_TRNG_GO_EVENT_DEFAULT 0x0 -#define GC_TRNG_TIMEOUT_COUNTER_OFFSET 0x14 -#define GC_TRNG_TIMEOUT_COUNTER_DEFAULT 0x2710 -#define GC_TRNG_TIMEOUT_MAX_TRY_NUM_OFFSET 0x18 +#define GC_TRNG_RO_CALIBRATION_MODE_OFFSET 0x18 +#define GC_TRNG_RO_CALIBRATION_MODE_DEFAULT 0x0 +#define GC_TRNG_TIMEOUT_COUNTER_OFFSET 0x1c +#define GC_TRNG_TIMEOUT_COUNTER_DEFAULT 0x7d0 +#define GC_TRNG_TIMEOUT_MAX_TRY_NUM_OFFSET 0x20 #define GC_TRNG_TIMEOUT_MAX_TRY_NUM_DEFAULT 0x4 -#define GC_TRNG_CAPTURE_FOR_CALIBRATION_NUM_ENTRIES_OFFSET 0x1c -#define GC_TRNG_CAPTURE_FOR_CALIBRATION_NUM_ENTRIES_DEFAULT 0x7 -#define GC_TRNG_STOP_WORK_OFFSET 0x20 +#define GC_TRNG_OUTPUT_TIME_COUNTER_OFFSET 0x24 +#define GC_TRNG_OUTPUT_TIME_COUNTER_DEFAULT 0x10000 +#define GC_TRNG_STOP_WORK_OFFSET 0x28 #define GC_TRNG_STOP_WORK_DEFAULT 0x0 -#define GC_TRNG_TAIL_POINTER_OFFSET 0x24 -#define GC_TRNG_TAIL_POINTER_DEFAULT 0x0 -#define GC_TRNG_SLICE_MAX_LIMIT_OFFSET 0x28 -#define GC_TRNG_SLICE_MAX_LIMIT_DEFAULT 0xf0 -#define GC_TRNG_HEAD_POINTER_OFFSET 0x2c -#define GC_TRNG_HEAD_POINTER_DEFAULT 0x0 -#define GC_TRNG_SYNC_ANALOG_OFFSET 0x30 -#define GC_TRNG_SYNC_ANALOG_DEFAULT 0x0 -#define GC_TRNG_MODE_OPERATION_OFFSET 0x34 -#define GC_TRNG_MODE_OPERATION_DEFAULT 0x0 -#define GC_TRNG_FSM_STATE_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_OFFSET 0x2c #define GC_TRNG_FSM_STATE_DEFAULT 0x1 -#define GC_TRNG_TIMER_COUNTER_OFFSET 0x3c +#define GC_TRNG_ALLOWED_VALUES_OFFSET 0x30 +#define GC_TRNG_ALLOWED_VALUES_DEFAULT 0x0 +#define GC_TRNG_TIMER_COUNTER_OFFSET 0x34 #define GC_TRNG_TIMER_COUNTER_DEFAULT 0x0 -#define GC_TRNG_SLICE_RANGE_OFFSET 0x40 -#define GC_TRNG_SLICE_RANGE_DEFAULT 0xf0 -#define GC_TRNG_AVERAGE_OFFSET 0x44 -#define GC_TRNG_AVERAGE_DEFAULT 0x0 -#define GC_TRNG_STD_DEV_OFFSET 0x48 -#define GC_TRNG_STD_DEV_DEFAULT 0x0 -#define GC_TRNG_INLINE_STATS_OFFSET 0x4c -#define GC_TRNG_INLINE_STATS_DEFAULT 0x0 -#define GC_TRNG_LDO_CTRL_OFFSET 0x50 +#define GC_TRNG_SLICE_MAX_UPPER_LIMIT_OFFSET 0x38 +#define GC_TRNG_SLICE_MAX_UPPER_LIMIT_DEFAULT 0xf +#define GC_TRNG_SLICE_MIN_LOWER_LIMIT_OFFSET 0x3c +#define GC_TRNG_SLICE_MIN_LOWER_LIMIT_DEFAULT 0x0 +#define GC_TRNG_MAX_VALUE_OFFSET 0x40 +#define GC_TRNG_MAX_VALUE_DEFAULT 0x0 +#define GC_TRNG_MIN_VALUE_OFFSET 0x44 +#define GC_TRNG_MIN_VALUE_DEFAULT 0x0 +#define GC_TRNG_LDO_CTRL_OFFSET 0x48 #define GC_TRNG_LDO_CTRL_DEFAULT 0xb -#define GC_TRNG_DIV_EN_OFFSET 0x54 +#define GC_TRNG_DIV_EN_OFFSET 0x4c #define GC_TRNG_DIV_EN_DEFAULT 0x0 -#define GC_TRNG_ONE_SHOT_MODE_OFFSET 0x58 +#define GC_TRNG_ONE_SHOT_MODE_OFFSET 0x50 #define GC_TRNG_ONE_SHOT_MODE_DEFAULT 0x0 -#define GC_TRNG_ONE_SHOT_REG_OFFSET 0x5c +#define GC_TRNG_ONE_SHOT_REG_OFFSET 0x54 #define GC_TRNG_ONE_SHOT_REG_DEFAULT 0x0 -#define GC_TRNG_REG_BITS0_OFFSET 0x100 -#define GC_TRNG_REG_BITS0_DEFAULT 0x0 -#define GC_TRNG_REG_BITS1_OFFSET 0x104 -#define GC_TRNG_REG_BITS1_DEFAULT 0x0 -#define GC_TRNG_REG_BITS2_OFFSET 0x108 -#define GC_TRNG_REG_BITS2_DEFAULT 0x0 -#define GC_TRNG_REG_BITS3_OFFSET 0x10c -#define GC_TRNG_REG_BITS3_DEFAULT 0x0 -#define GC_TRNG_REG_BITS4_OFFSET 0x110 -#define GC_TRNG_REG_BITS4_DEFAULT 0x0 -#define GC_TRNG_REG_BITS5_OFFSET 0x114 -#define GC_TRNG_REG_BITS5_DEFAULT 0x0 -#define GC_TRNG_REG_BITS6_OFFSET 0x118 -#define GC_TRNG_REG_BITS6_DEFAULT 0x0 -#define GC_TRNG_REG_BITS7_OFFSET 0x11c -#define GC_TRNG_REG_BITS7_DEFAULT 0x0 -#define GC_TRNG_REG_BITS8_OFFSET 0x120 -#define GC_TRNG_REG_BITS8_DEFAULT 0x0 -#define GC_TRNG_REG_BITS9_OFFSET 0x124 -#define GC_TRNG_REG_BITS9_DEFAULT 0x0 -#define GC_TRNG_REG_BITS10_OFFSET 0x128 -#define GC_TRNG_REG_BITS10_DEFAULT 0x0 -#define GC_TRNG_REG_BITS11_OFFSET 0x12c -#define GC_TRNG_REG_BITS11_DEFAULT 0x0 -#define GC_TRNG_REG_BITS12_OFFSET 0x130 -#define GC_TRNG_REG_BITS12_DEFAULT 0x0 -#define GC_TRNG_REG_BITS13_OFFSET 0x134 -#define GC_TRNG_REG_BITS13_DEFAULT 0x0 -#define GC_TRNG_REG_BITS14_OFFSET 0x138 -#define GC_TRNG_REG_BITS14_DEFAULT 0x0 -#define GC_TRNG_REG_BITS15_OFFSET 0x13c -#define GC_TRNG_REG_BITS15_DEFAULT 0x0 -#define GC_TRNG_REG_BITS16_OFFSET 0x140 -#define GC_TRNG_REG_BITS16_DEFAULT 0x0 -#define GC_TRNG_REG_BITS17_OFFSET 0x144 -#define GC_TRNG_REG_BITS17_DEFAULT 0x0 -#define GC_TRNG_REG_BITS18_OFFSET 0x148 -#define GC_TRNG_REG_BITS18_DEFAULT 0x0 -#define GC_TRNG_REG_BITS19_OFFSET 0x14c -#define GC_TRNG_REG_BITS19_DEFAULT 0x0 -#define GC_TRNG_REG_BITS20_OFFSET 0x150 -#define GC_TRNG_REG_BITS20_DEFAULT 0x0 -#define GC_TRNG_REG_BITS21_OFFSET 0x154 -#define GC_TRNG_REG_BITS21_DEFAULT 0x0 -#define GC_TRNG_REG_BITS22_OFFSET 0x158 -#define GC_TRNG_REG_BITS22_DEFAULT 0x0 -#define GC_TRNG_REG_BITS23_OFFSET 0x15c -#define GC_TRNG_REG_BITS23_DEFAULT 0x0 -#define GC_TRNG_REG_BITS24_OFFSET 0x160 -#define GC_TRNG_REG_BITS24_DEFAULT 0x0 -#define GC_TRNG_REG_BITS25_OFFSET 0x164 -#define GC_TRNG_REG_BITS25_DEFAULT 0x0 -#define GC_TRNG_REG_BITS26_OFFSET 0x168 -#define GC_TRNG_REG_BITS26_DEFAULT 0x0 -#define GC_TRNG_REG_BITS27_OFFSET 0x16c -#define GC_TRNG_REG_BITS27_DEFAULT 0x0 -#define GC_TRNG_REG_BITS28_OFFSET 0x170 -#define GC_TRNG_REG_BITS28_DEFAULT 0x0 -#define GC_TRNG_REG_BITS29_OFFSET 0x174 -#define GC_TRNG_REG_BITS29_DEFAULT 0x0 -#define GC_TRNG_REG_BITS30_OFFSET 0x178 -#define GC_TRNG_REG_BITS30_DEFAULT 0x0 -#define GC_TRNG_REG_BITS31_OFFSET 0x17c -#define GC_TRNG_REG_BITS31_DEFAULT 0x0 -#define GC_TRNG_REG_BITS32_OFFSET 0x180 -#define GC_TRNG_REG_BITS32_DEFAULT 0x0 -#define GC_TRNG_REG_BITS33_OFFSET 0x184 -#define GC_TRNG_REG_BITS33_DEFAULT 0x0 -#define GC_TRNG_REG_BITS34_OFFSET 0x188 -#define GC_TRNG_REG_BITS34_DEFAULT 0x0 -#define GC_TRNG_REG_BITS35_OFFSET 0x18c -#define GC_TRNG_REG_BITS35_DEFAULT 0x0 -#define GC_TRNG_REG_BITS36_OFFSET 0x190 -#define GC_TRNG_REG_BITS36_DEFAULT 0x0 -#define GC_TRNG_REG_BITS37_OFFSET 0x194 -#define GC_TRNG_REG_BITS37_DEFAULT 0x0 -#define GC_TRNG_REG_BITS38_OFFSET 0x198 -#define GC_TRNG_REG_BITS38_DEFAULT 0x0 -#define GC_TRNG_REG_BITS39_OFFSET 0x19c -#define GC_TRNG_REG_BITS39_DEFAULT 0x0 -#define GC_TRNG_REG_BITS40_OFFSET 0x1a0 -#define GC_TRNG_REG_BITS40_DEFAULT 0x0 -#define GC_TRNG_REG_BITS41_OFFSET 0x1a4 -#define GC_TRNG_REG_BITS41_DEFAULT 0x0 -#define GC_TRNG_REG_BITS42_OFFSET 0x1a8 -#define GC_TRNG_REG_BITS42_DEFAULT 0x0 -#define GC_TRNG_REG_BITS43_OFFSET 0x1ac -#define GC_TRNG_REG_BITS43_DEFAULT 0x0 -#define GC_TRNG_REG_BITS44_OFFSET 0x1b0 -#define GC_TRNG_REG_BITS44_DEFAULT 0x0 -#define GC_TRNG_REG_BITS45_OFFSET 0x1b4 -#define GC_TRNG_REG_BITS45_DEFAULT 0x0 -#define GC_TRNG_REG_BITS46_OFFSET 0x1b8 -#define GC_TRNG_REG_BITS46_DEFAULT 0x0 -#define GC_TRNG_REG_BITS47_OFFSET 0x1bc -#define GC_TRNG_REG_BITS47_DEFAULT 0x0 -#define GC_TRNG_REG_BITS48_OFFSET 0x1c0 -#define GC_TRNG_REG_BITS48_DEFAULT 0x0 -#define GC_TRNG_REG_BITS49_OFFSET 0x1c4 -#define GC_TRNG_REG_BITS49_DEFAULT 0x0 -#define GC_TRNG_REG_BITS50_OFFSET 0x1c8 -#define GC_TRNG_REG_BITS50_DEFAULT 0x0 -#define GC_TRNG_REG_BITS51_OFFSET 0x1cc -#define GC_TRNG_REG_BITS51_DEFAULT 0x0 -#define GC_TRNG_REG_BITS52_OFFSET 0x1d0 -#define GC_TRNG_REG_BITS52_DEFAULT 0x0 -#define GC_TRNG_REG_BITS53_OFFSET 0x1d4 -#define GC_TRNG_REG_BITS53_DEFAULT 0x0 -#define GC_TRNG_REG_BITS54_OFFSET 0x1d8 -#define GC_TRNG_REG_BITS54_DEFAULT 0x0 -#define GC_TRNG_REG_BITS55_OFFSET 0x1dc -#define GC_TRNG_REG_BITS55_DEFAULT 0x0 -#define GC_TRNG_REG_BITS56_OFFSET 0x1e0 -#define GC_TRNG_REG_BITS56_DEFAULT 0x0 -#define GC_TRNG_REG_BITS57_OFFSET 0x1e4 -#define GC_TRNG_REG_BITS57_DEFAULT 0x0 -#define GC_TRNG_REG_BITS58_OFFSET 0x1e8 -#define GC_TRNG_REG_BITS58_DEFAULT 0x0 -#define GC_TRNG_REG_BITS59_OFFSET 0x1ec -#define GC_TRNG_REG_BITS59_DEFAULT 0x0 -#define GC_TRNG_REG_BITS60_OFFSET 0x1f0 -#define GC_TRNG_REG_BITS60_DEFAULT 0x0 -#define GC_TRNG_REG_BITS61_OFFSET 0x1f4 -#define GC_TRNG_REG_BITS61_DEFAULT 0x0 -#define GC_TRNG_REG_BITS62_OFFSET 0x1f8 -#define GC_TRNG_REG_BITS62_DEFAULT 0x0 -#define GC_TRNG_REG_BITS63_OFFSET 0x1fc -#define GC_TRNG_REG_BITS63_DEFAULT 0x0 -#define GC_TRNG_FPGA_MODEL_MEAN_OFFSET 0x200 +#define GC_TRNG_READ_DATA_OFFSET 0x58 +#define GC_TRNG_READ_DATA_DEFAULT 0x0 +#define GC_TRNG_FREQUENCY_CALLS_OFFSET 0x5c +#define GC_TRNG_FREQUENCY_CALLS_DEFAULT 0x0 +#define GC_TRNG_CUR_NUM_ONES_OFFSET 0x60 +#define GC_TRNG_CUR_NUM_ONES_DEFAULT 0x0 +#define GC_TRNG_EMPTY_OFFSET 0x64 +#define GC_TRNG_EMPTY_DEFAULT 0x0 +#define GC_TRNG_FPGA_MODEL_MEAN_OFFSET 0x68 #define GC_TRNG_FPGA_MODEL_MEAN_DEFAULT 0x400 -#define GC_TRNG_FPGA_MODEL_DIST_MASK_OFFSET 0x204 +#define GC_TRNG_FPGA_MODEL_DIST_MASK_OFFSET 0x6c #define GC_TRNG_FPGA_MODEL_DIST_MASK_DEFAULT 0x3ff -#define GC_TRNG_FPGA_MODEL_PPM_TIMEOUT_OFFSET 0x208 +#define GC_TRNG_FPGA_MODEL_PPM_TIMEOUT_OFFSET 0x70 #define GC_TRNG_FPGA_MODEL_PPM_TIMEOUT_DEFAULT 0x0 -#define GC_TRNG_FPGA_MODEL_STAT_CALLS_OFFSET 0x20c +#define GC_TRNG_FPGA_MODEL_STAT_CALLS_OFFSET 0x74 #define GC_TRNG_FPGA_MODEL_STAT_CALLS_DEFAULT 0x0 -#define GC_TRNG_FPGA_MODEL_STAT_TIMEOUTS_OFFSET 0x210 +#define GC_TRNG_FPGA_MODEL_STAT_TIMEOUTS_OFFSET 0x78 #define GC_TRNG_FPGA_MODEL_STAT_TIMEOUTS_DEFAULT 0x0 -#define GC_TRNG_FPGA_MODEL_STAT_ABORTS_OFFSET 0x214 +#define GC_TRNG_FPGA_MODEL_STAT_ABORTS_OFFSET 0x7c #define GC_TRNG_FPGA_MODEL_STAT_ABORTS_DEFAULT 0x0 #define GC_UART_RDATA_OFFSET 0x0 #define GC_UART_RDATA_DEFAULT 0x0 @@ -3633,23 +4800,15 @@ #define GC_USB_DOEPDMA15_DEFAULT 0x0 #define GC_USB_DOEPDMAB15_OFFSET 0xcfc #define GC_USB_DOEPDMAB15_DEFAULT 0x0 -#define GC_USB_DFIFO_PP0_OFFSET 0x1000 -#define GC_USB_DFIFO_PP1_OFFSET 0x2000 -#define GC_USB_DFIFO_PP2_OFFSET 0x3000 -#define GC_USB_DFIFO_PP3_OFFSET 0x4000 -#define GC_USB_DFIFO_PP4_OFFSET 0x5000 -#define GC_USB_DFIFO_PP5_OFFSET 0x6000 -#define GC_USB_DFIFO_PP6_OFFSET 0x7000 -#define GC_USB_DFIFO_PP7_OFFSET 0x8000 -#define GC_USB_DFIFO_PP8_OFFSET 0x9000 -#define GC_USB_DFIFO_PP9_OFFSET 0xa000 -#define GC_USB_DFIFO_PP10_OFFSET 0xb000 -#define GC_USB_DFIFO_PP11_OFFSET 0xc000 -#define GC_USB_DFIFO_PP12_OFFSET 0xd000 -#define GC_USB_DFIFO_PP13_OFFSET 0xe000 -#define GC_USB_DFIFO_PP14_OFFSET 0xf000 -#define GC_USB_DFIFO_PP15_OFFSET 0x10000 #define GC_USB_DFIFO_OFFSET 0x20000 +#define GC_VOLT_VERSION_OFFSET 0x0 +#define GC_VOLT_VERSION_DEFAULT 0x1010218 +#define GC_VOLT_ANALOG_CONTROL_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_DEFAULT 0x0 +#define GC_VOLT_CONFIG_OFFSET 0x8 +#define GC_VOLT_CONFIG_DEFAULT 0x0 +#define GC_VOLT_ERRS_CTR_STATE_OFFSET 0xc +#define GC_VOLT_ERRS_CTR_STATE_DEFAULT 0x0 #define GC_WATCHDOG_WDOGLOAD_OFFSET 0x0 #define GC_WATCHDOG_WDOGLOAD_DEFAULT 0xffffffff #define GC_WATCHDOG_WDOGVALUE_OFFSET 0x4 @@ -3692,57 +4851,273 @@ #define GC_WATCHDOG_WDOGPCELLID2_DEFAULT 0x5 #define GC_WATCHDOG_WDOGPCELLID3_OFFSET 0xffc #define GC_WATCHDOG_WDOGPCELLID3_DEFAULT 0xb1 -#define GC_XO_OSC_CLKOUT_OFFSET 0x0 -#define GC_XO_OSC_CLKOUT_DEFAULT 0x0 -#define GC_XO_OSC_ADC_CAL_FREQ2X_OFFSET 0x4 -#define GC_XO_OSC_ADC_CAL_FREQ2X_DEFAULT 0x6 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_OFFSET 0x8 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_DEFAULT 0x6 -#define GC_XO_OSC_24_48B_SEL_OFFSET 0xc -#define GC_XO_OSC_24_48B_SEL_DEFAULT 0x0 -#define GC_XO_OSC_TEST_OFFSET 0x10 -#define GC_XO_OSC_TEST_DEFAULT 0x0 -#define GC_XO_OSC_RC_CAL_RSTB_OFFSET 0x14 -#define GC_XO_OSC_RC_CAL_RSTB_DEFAULT 0x1 -#define GC_XO_OSC_RC_CAL_LOAD_OFFSET 0x18 -#define GC_XO_OSC_RC_CAL_LOAD_DEFAULT 0x800 -#define GC_XO_OSC_RC_CAL_START_OFFSET 0x1c -#define GC_XO_OSC_RC_CAL_START_DEFAULT 0x0 -#define GC_XO_OSC_RC_CAL_DONE_OFFSET 0x20 -#define GC_XO_OSC_RC_CAL_DONE_DEFAULT 0x0 -#define GC_XO_OSC_RC_CAL_COUNT_OFFSET 0x24 -#define GC_XO_OSC_RC_CAL_COUNT_DEFAULT 0x0 -#define GC_XO_OSC_RC_OFFSET 0x28 -#define GC_XO_OSC_RC_DEFAULT 0x4444444 -#define GC_XO_OSC_RC_STATUS_OFFSET 0x2c -#define GC_XO_OSC_RC_STATUS_DEFAULT 0x4444444 -#define GC_XO_OSC_XTL_TRIMD_OFFSET 0x30 +#define GC_XO_VERSION_OFFSET 0x0 +#define GC_XO_VERSION_DEFAULT 0x14010370 +#define GC_XO_CLK_JTR_CTRL_OFFSET 0x4 +#define GC_XO_CLK_JTR_CTRL_DEFAULT 0x3 +#define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_OFFSET 0x8 +#define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_OFFSET 0xc +#define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CURRENT_OFFSET 0x10 +#define GC_XO_CLK_JTR_CURRENT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SYNC_CONTENTS_OFFSET 0x14 +#define GC_XO_CLK_JTR_SYNC_CONTENTS_DEFAULT 0x0 +#define GC_XO_CLK_JTR_TRIM_CTRL_OFFSET 0x18 +#define GC_XO_CLK_JTR_TRIM_CTRL_DEFAULT 0x1e +#define GC_XO_CLK_JTR_JITTERY_TRIM_EN_OFFSET 0x1c +#define GC_XO_CLK_JTR_JITTERY_TRIM_EN_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_OFFSET 0x20 +#define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_OFFSET 0x24 +#define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_DEFAULT 0xff +#define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_OFFSET 0x28 +#define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_OFFSET 0x2c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_OFFSET 0x30 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_OFFSET 0x34 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_OFFSET 0x38 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_OFFSET 0x3c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_OFFSET 0x40 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_OFFSET 0x44 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_OFFSET 0x48 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_OFFSET 0x4c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_OFFSET 0x50 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_OFFSET 0x54 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_OFFSET 0x58 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_OFFSET 0x5c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_OFFSET 0x60 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_OFFSET 0x64 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_DEFAULT 0x0 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_OFFSET 0x68 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CALIB_NOP_SEEN_OFFSET 0x70 +#define GC_XO_CLK_JTR_CALIB_NOP_SEEN_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_OFFSET 0x74 +#define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_OFFSET 0x78 +#define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB0_OFFSET 0x7c +#define GC_XO_CLK_JTR_FAST_CALIB0_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB1_OFFSET 0x80 +#define GC_XO_CLK_JTR_FAST_CALIB1_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB2_OFFSET 0x84 +#define GC_XO_CLK_JTR_FAST_CALIB2_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB3_OFFSET 0x88 +#define GC_XO_CLK_JTR_FAST_CALIB3_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB4_OFFSET 0x8c +#define GC_XO_CLK_JTR_FAST_CALIB4_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB5_OFFSET 0x90 +#define GC_XO_CLK_JTR_FAST_CALIB5_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB6_OFFSET 0x94 +#define GC_XO_CLK_JTR_FAST_CALIB6_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB7_OFFSET 0x98 +#define GC_XO_CLK_JTR_FAST_CALIB7_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OFFSET 0x9c +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OFFSET 0xa0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OFFSET 0xa4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OFFSET 0xa8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OFFSET 0xac +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OFFSET 0xb0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OFFSET 0xb4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OFFSET 0xb8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OFFSET 0xbc +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB0_OFFSET 0xc0 +#define GC_XO_CLK_JTR_SLOW_CALIB0_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB1_OFFSET 0xc4 +#define GC_XO_CLK_JTR_SLOW_CALIB1_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB2_OFFSET 0xc8 +#define GC_XO_CLK_JTR_SLOW_CALIB2_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB3_OFFSET 0xcc +#define GC_XO_CLK_JTR_SLOW_CALIB3_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB4_OFFSET 0xd0 +#define GC_XO_CLK_JTR_SLOW_CALIB4_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB5_OFFSET 0xd4 +#define GC_XO_CLK_JTR_SLOW_CALIB5_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB6_OFFSET 0xd8 +#define GC_XO_CLK_JTR_SLOW_CALIB6_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB7_OFFSET 0xdc +#define GC_XO_CLK_JTR_SLOW_CALIB7_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OFFSET 0xe0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OFFSET 0xe4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OFFSET 0xe8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OFFSET 0xec +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OFFSET 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OFFSET 0xf4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OFFSET 0xf8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OFFSET 0xfc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OFFSET 0x100 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_DEFAULT 0x0 +#define GC_XO_CLK_JTR_ENABLE_SW_TRIM_OFFSET 0x104 +#define GC_XO_CLK_JTR_ENABLE_SW_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_OFFSET 0x108 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CTRL_OFFSET 0x10c +#define GC_XO_CLK_TIMER_CTRL_DEFAULT 0x3 +#define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_OFFSET 0x110 +#define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_OFFSET 0x114 +#define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CURRENT_OFFSET 0x118 +#define GC_XO_CLK_TIMER_CURRENT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SYNC_CONTENTS_OFFSET 0x11c +#define GC_XO_CLK_TIMER_SYNC_CONTENTS_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_TRIM_CTRL_OFFSET 0x120 +#define GC_XO_CLK_TIMER_TRIM_CTRL_DEFAULT 0x1e +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_OFFSET 0x128 +#define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_OFFSET 0x12c +#define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_OFFSET 0x130 +#define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB0_OFFSET 0x134 +#define GC_XO_CLK_TIMER_FAST_CALIB0_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB1_OFFSET 0x138 +#define GC_XO_CLK_TIMER_FAST_CALIB1_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB2_OFFSET 0x13c +#define GC_XO_CLK_TIMER_FAST_CALIB2_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB3_OFFSET 0x140 +#define GC_XO_CLK_TIMER_FAST_CALIB3_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB4_OFFSET 0x144 +#define GC_XO_CLK_TIMER_FAST_CALIB4_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB5_OFFSET 0x148 +#define GC_XO_CLK_TIMER_FAST_CALIB5_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB6_OFFSET 0x14c +#define GC_XO_CLK_TIMER_FAST_CALIB6_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB7_OFFSET 0x150 +#define GC_XO_CLK_TIMER_FAST_CALIB7_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OFFSET 0x154 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OFFSET 0x158 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OFFSET 0x15c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OFFSET 0x160 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OFFSET 0x164 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OFFSET 0x168 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OFFSET 0x16c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OFFSET 0x170 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OFFSET 0x174 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB0_OFFSET 0x178 +#define GC_XO_CLK_TIMER_SLOW_CALIB0_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB1_OFFSET 0x17c +#define GC_XO_CLK_TIMER_SLOW_CALIB1_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB2_OFFSET 0x180 +#define GC_XO_CLK_TIMER_SLOW_CALIB2_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_OFFSET 0x184 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB4_OFFSET 0x188 +#define GC_XO_CLK_TIMER_SLOW_CALIB4_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB5_OFFSET 0x18c +#define GC_XO_CLK_TIMER_SLOW_CALIB5_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB6_OFFSET 0x190 +#define GC_XO_CLK_TIMER_SLOW_CALIB6_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_OFFSET 0x194 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OFFSET 0x198 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OFFSET 0x19c +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OFFSET 0x1a0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OFFSET 0x1a4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OFFSET 0x1a8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OFFSET 0x1ac +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OFFSET 0x1b0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OFFSET 0x1b4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OFFSET 0x1b8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_OFFSET 0x1bc +#define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_OFFSET 0x1c0 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FREQ2X_OFFSET 0x1c4 +#define GC_XO_OSC_XTL_FREQ2X_DEFAULT 0x6 +#define GC_XO_OSC_XTL_FREQ2X_STAT_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_STAT_DEFAULT 0x6 +#define GC_XO_OSC_XTL_TRIMD_OFFSET 0x1cc #define GC_XO_OSC_XTL_TRIMD_DEFAULT 0x40 -#define GC_XO_OSC_XTL_TRIMG_OFFSET 0x34 +#define GC_XO_OSC_XTL_TRIMG_OFFSET 0x1d0 #define GC_XO_OSC_XTL_TRIMG_DEFAULT 0x40 -#define GC_XO_OSC_XTL_CTRL_OFFSET 0x38 +#define GC_XO_OSC_XTL_CTRL_OFFSET 0x1d4 #define GC_XO_OSC_XTL_CTRL_DEFAULT 0x0 -#define GC_XO_OSC_XTL_RC_FLTR_OFFSET 0x3c +#define GC_XO_OSC_XTL_RC_FLTR_OFFSET 0x1d8 #define GC_XO_OSC_XTL_RC_FLTR_DEFAULT 0x15 -#define GC_XO_OSC_XTL_OVRD_OFFSET 0x40 +#define GC_XO_OSC_XTL_OVRD_OFFSET 0x1dc #define GC_XO_OSC_XTL_OVRD_DEFAULT 0x17 -#define GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET 0x44 +#define GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET 0x1e0 #define GC_XO_OSC_XTL_OVRD_HOLDB_DEFAULT 0x1 -#define GC_XO_OSC_XTL_TRIM_OFFSET 0x48 +#define GC_XO_OSC_XTL_TRIM_OFFSET 0x1e4 #define GC_XO_OSC_XTL_TRIM_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_STAT_OFFSET 0x4c +#define GC_XO_OSC_XTL_TRIM_STAT_OFFSET 0x1e8 #define GC_XO_OSC_XTL_TRIM_STAT_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_EN_OFFSET 0x50 +#define GC_XO_OSC_XTL_FSM_EN_OFFSET 0x1ec #define GC_XO_OSC_XTL_FSM_EN_DEFAULT 0x0 #define GC_XO_OSC_XTL_FSM_EN_KEY 0x60221413 -#define GC_XO_OSC_XTL_FSM_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_RESETB_OFFSET 0x1f0 +#define GC_XO_OSC_XTL_FSM_RESETB_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_OFFSET 0x1f4 #define GC_XO_OSC_XTL_FSM_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_CFG_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_CFG_DEFAULT 0xd7488 -#define GC_XO_OSC_SETHOLD_OFFSET 0x5c +#define GC_XO_OSC_SETHOLD_OFFSET 0x1fc #define GC_XO_OSC_SETHOLD_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_OFFSET 0x60 +#define GC_XO_OSC_CLRHOLD_OFFSET 0x200 #define GC_XO_OSC_CLRHOLD_DEFAULT 0x0 +#define GC_XO_OSC_TEST_OFFSET 0x204 +#define GC_XO_OSC_TEST_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_DEFAULT 0x0 +#define GC_XO_DXO_INT_STATE_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_DEFAULT 0x0 +#define GC_XO_DXO_INT_TEST_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_DEFAULT 0x0 #define GC_M3_ITM_STIM0_OFFSET 0x0 #define GC_M3_ITM_STIM0_DEFAULT 0x0 #define GC_M3_ITM_STIM1_OFFSET 0x4 @@ -3884,7 +5259,7 @@ #define GC_M3_FP_COMP7_OFFSET 0x2024 #define GC_M3_FP_COMP7_DEFAULT 0x0 #define GC_M3_ICTR_OFFSET 0xe004 -#define GC_M3_ICTR_DEFAULT 0x4 +#define GC_M3_ICTR_DEFAULT 0x7 #define GC_M3_SYST_CSR_OFFSET 0xe010 #define GC_M3_SYST_CSR_DEFAULT 0x4 #define GC_M3_SYST_RVR_OFFSET 0xe014 @@ -4409,76 +5784,1386 @@ #define GC_M3_CLAIMCLR_ADDR 0xe0040fa4 #define GC_M3_DEVID_ADDR 0xe0040fc8 #define GC_M3_DEVTYPE_ADDR 0xe0040fcc -#define GC_AES_CTRL_KEYSIZE_LSB 0x0 -#define GC_AES_CTRL_KEYSIZE_MASK 0x3 -#define GC_AES_CTRL_KEYSIZE_SIZE 0x2 -#define GC_AES_CTRL_KEYSIZE_DEFAULT 0x0 -#define GC_AES_CTRL_KEYSIZE_OFFSET 0x0 -#define GC_AES_CTRL_CTR_MODE_LSB 0x2 -#define GC_AES_CTRL_CTR_MODE_MASK 0x4 -#define GC_AES_CTRL_CTR_MODE_SIZE 0x1 -#define GC_AES_CTRL_CTR_MODE_DEFAULT 0x0 -#define GC_AES_CTRL_CTR_MODE_OFFSET 0x0 -#define GC_AES_CTRL_ENC_MODE_LSB 0x3 -#define GC_AES_CTRL_ENC_MODE_MASK 0x8 -#define GC_AES_CTRL_ENC_MODE_SIZE 0x1 -#define GC_AES_CTRL_ENC_MODE_DEFAULT 0x0 -#define GC_AES_CTRL_ENC_MODE_OFFSET 0x0 -#define GC_AES_CTRL_CTR_ENDIAN_LSB 0x4 -#define GC_AES_CTRL_CTR_ENDIAN_MASK 0x10 -#define GC_AES_CTRL_CTR_ENDIAN_SIZE 0x1 -#define GC_AES_CTRL_CTR_ENDIAN_DEFAULT 0x0 -#define GC_AES_CTRL_CTR_ENDIAN_OFFSET 0x0 -#define GC_AES_LFSR_CTL_STALL_EN_LSB 0x0 -#define GC_AES_LFSR_CTL_STALL_EN_MASK 0x1 -#define GC_AES_LFSR_CTL_STALL_EN_SIZE 0x1 -#define GC_AES_LFSR_CTL_STALL_EN_DEFAULT 0x1 -#define GC_AES_LFSR_CTL_STALL_EN_OFFSET 0x60 -#define GC_AES_LFSR_CTL_WIDTH_LSB 0x1 -#define GC_AES_LFSR_CTL_WIDTH_MASK 0x6 -#define GC_AES_LFSR_CTL_WIDTH_SIZE 0x2 -#define GC_AES_LFSR_CTL_WIDTH_DEFAULT 0x3 -#define GC_AES_LFSR_CTL_WIDTH_OFFSET 0x60 -#define GC_AES_LFSR_CTL_FREQ_LSB 0x3 -#define GC_AES_LFSR_CTL_FREQ_MASK 0x18 -#define GC_AES_LFSR_CTL_FREQ_SIZE 0x2 -#define GC_AES_LFSR_CTL_FREQ_DEFAULT 0x3 -#define GC_AES_LFSR_CTL_FREQ_OFFSET 0x60 #define GC_AES_VERSION_CHANGE_LSB 0x0 #define GC_AES_VERSION_CHANGE_MASK 0xffffff #define GC_AES_VERSION_CHANGE_SIZE 0x18 -#define GC_AES_VERSION_CHANGE_DEFAULT 0xbe5c -#define GC_AES_VERSION_CHANGE_OFFSET 0x64 +#define GC_AES_VERSION_CHANGE_DEFAULT 0x1052c +#define GC_AES_VERSION_CHANGE_OFFSET 0x0 #define GC_AES_VERSION_REVISION_LSB 0x18 #define GC_AES_VERSION_REVISION_MASK 0xff000000 #define GC_AES_VERSION_REVISION_SIZE 0x8 -#define GC_AES_VERSION_REVISION_DEFAULT 0x8 -#define GC_AES_VERSION_REVISION_OFFSET 0x64 -#define GC_CAMO_INT_ENABLE_BREACH_LSB 0x0 -#define GC_CAMO_INT_ENABLE_BREACH_MASK 0x1 -#define GC_CAMO_INT_ENABLE_BREACH_SIZE 0x1 -#define GC_CAMO_INT_ENABLE_BREACH_DEFAULT 0x0 -#define GC_CAMO_INT_ENABLE_BREACH_OFFSET 0x8 -#define GC_CAMO_INT_STATE_BREACH_LSB 0x0 -#define GC_CAMO_INT_STATE_BREACH_MASK 0x1 -#define GC_CAMO_INT_STATE_BREACH_SIZE 0x1 -#define GC_CAMO_INT_STATE_BREACH_DEFAULT 0x0 -#define GC_CAMO_INT_STATE_BREACH_OFFSET 0xc -#define GC_CAMO_INT_TEST_BREACH_LSB 0x0 -#define GC_CAMO_INT_TEST_BREACH_MASK 0x1 -#define GC_CAMO_INT_TEST_BREACH_SIZE 0x1 -#define GC_CAMO_INT_TEST_BREACH_DEFAULT 0x0 -#define GC_CAMO_INT_TEST_BREACH_OFFSET 0x10 +#define GC_AES_VERSION_REVISION_DEFAULT 0x4 +#define GC_AES_VERSION_REVISION_OFFSET 0x0 +#define GC_AES_CTRL_RESET_LSB 0x0 +#define GC_AES_CTRL_RESET_MASK 0x1 +#define GC_AES_CTRL_RESET_SIZE 0x1 +#define GC_AES_CTRL_RESET_DEFAULT 0x0 +#define GC_AES_CTRL_RESET_OFFSET 0x4 +#define GC_AES_CTRL_KEYSIZE_LSB 0x1 +#define GC_AES_CTRL_KEYSIZE_MASK 0x6 +#define GC_AES_CTRL_KEYSIZE_SIZE 0x2 +#define GC_AES_CTRL_KEYSIZE_DEFAULT 0x0 +#define GC_AES_CTRL_KEYSIZE_OFFSET 0x4 +#define GC_AES_CTRL_CIPHER_MODE_LSB 0x3 +#define GC_AES_CTRL_CIPHER_MODE_MASK 0x18 +#define GC_AES_CTRL_CIPHER_MODE_SIZE 0x2 +#define GC_AES_CTRL_CIPHER_MODE_DEFAULT 0x0 +#define GC_AES_CTRL_CIPHER_MODE_OFFSET 0x4 +#define GC_AES_CTRL_ENC_MODE_LSB 0x5 +#define GC_AES_CTRL_ENC_MODE_MASK 0x20 +#define GC_AES_CTRL_ENC_MODE_SIZE 0x1 +#define GC_AES_CTRL_ENC_MODE_DEFAULT 0x0 +#define GC_AES_CTRL_ENC_MODE_OFFSET 0x4 +#define GC_AES_CTRL_CTR_ENDIAN_LSB 0x6 +#define GC_AES_CTRL_CTR_ENDIAN_MASK 0x40 +#define GC_AES_CTRL_CTR_ENDIAN_SIZE 0x1 +#define GC_AES_CTRL_CTR_ENDIAN_DEFAULT 0x0 +#define GC_AES_CTRL_CTR_ENDIAN_OFFSET 0x4 +#define GC_AES_CTRL_ENABLE_LSB 0x7 +#define GC_AES_CTRL_ENABLE_MASK 0x80 +#define GC_AES_CTRL_ENABLE_SIZE 0x1 +#define GC_AES_CTRL_ENABLE_DEFAULT 0x0 +#define GC_AES_CTRL_ENABLE_OFFSET 0x4 +#define GC_AES_HKEY_INDEX_LSB 0x0 +#define GC_AES_HKEY_INDEX_MASK 0x3ff +#define GC_AES_HKEY_INDEX_SIZE 0xa +#define GC_AES_HKEY_INDEX_DEFAULT 0x0 +#define GC_AES_HKEY_INDEX_OFFSET 0x18 +#define GC_AES_HKEY_READ_EN_LSB 0x0 +#define GC_AES_HKEY_READ_EN_MASK 0x1 +#define GC_AES_HKEY_READ_EN_SIZE 0x1 +#define GC_AES_HKEY_READ_EN_DEFAULT 0x0 +#define GC_AES_HKEY_READ_EN_OFFSET 0x1c +#define GC_AES_RAND_STALL_CTL_STALL_EN_LSB 0x0 +#define GC_AES_RAND_STALL_CTL_STALL_EN_MASK 0x1 +#define GC_AES_RAND_STALL_CTL_STALL_EN_SIZE 0x1 +#define GC_AES_RAND_STALL_CTL_STALL_EN_DEFAULT 0x1 +#define GC_AES_RAND_STALL_CTL_STALL_EN_OFFSET 0x60 +#define GC_AES_RAND_STALL_CTL_FREQ_LSB 0x1 +#define GC_AES_RAND_STALL_CTL_FREQ_MASK 0x6 +#define GC_AES_RAND_STALL_CTL_FREQ_SIZE 0x2 +#define GC_AES_RAND_STALL_CTL_FREQ_DEFAULT 0x3 +#define GC_AES_RAND_STALL_CTL_FREQ_OFFSET 0x60 +#define GC_AES_EXECUTE_COUNT_STD_MAX_VAL_LSB 0x0 +#define GC_AES_EXECUTE_COUNT_STD_MAX_VAL_MASK 0xffffffff +#define GC_AES_EXECUTE_COUNT_STD_MAX_VAL_SIZE 0x20 +#define GC_AES_EXECUTE_COUNT_STD_MAX_VAL_DEFAULT 0x0 +#define GC_AES_EXECUTE_COUNT_STD_MAX_VAL_OFFSET 0x7c +#define GC_AES_EXECUTE_COUNT_HKEY_MAX_VAL_LSB 0x0 +#define GC_AES_EXECUTE_COUNT_HKEY_MAX_VAL_MASK 0xffffffff +#define GC_AES_EXECUTE_COUNT_HKEY_MAX_VAL_SIZE 0x20 +#define GC_AES_EXECUTE_COUNT_HKEY_MAX_VAL_DEFAULT 0x0 +#define GC_AES_EXECUTE_COUNT_HKEY_MAX_VAL_OFFSET 0x80 +#define GC_AES_DAES_INT_ENABLE_WFIFO_OVERFLOW_LSB 0x0 +#define GC_AES_DAES_INT_ENABLE_WFIFO_OVERFLOW_MASK 0x1 +#define GC_AES_DAES_INT_ENABLE_WFIFO_OVERFLOW_SIZE 0x1 +#define GC_AES_DAES_INT_ENABLE_WFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_AES_DAES_INT_ENABLE_WFIFO_OVERFLOW_OFFSET 0xd0 +#define GC_AES_DAES_INT_ENABLE_RFIFO_OVERFLOW_LSB 0x1 +#define GC_AES_DAES_INT_ENABLE_RFIFO_OVERFLOW_MASK 0x2 +#define GC_AES_DAES_INT_ENABLE_RFIFO_OVERFLOW_SIZE 0x1 +#define GC_AES_DAES_INT_ENABLE_RFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_AES_DAES_INT_ENABLE_RFIFO_OVERFLOW_OFFSET 0xd0 +#define GC_AES_DAES_INT_ENABLE_RFIFO_UNDERFLOW_LSB 0x2 +#define GC_AES_DAES_INT_ENABLE_RFIFO_UNDERFLOW_MASK 0x4 +#define GC_AES_DAES_INT_ENABLE_RFIFO_UNDERFLOW_SIZE 0x1 +#define GC_AES_DAES_INT_ENABLE_RFIFO_UNDERFLOW_DEFAULT 0x0 +#define GC_AES_DAES_INT_ENABLE_RFIFO_UNDERFLOW_OFFSET 0xd0 +#define GC_AES_DAES_INT_ENABLE_DONE_CIPHER_LSB 0x3 +#define GC_AES_DAES_INT_ENABLE_DONE_CIPHER_MASK 0x8 +#define GC_AES_DAES_INT_ENABLE_DONE_CIPHER_SIZE 0x1 +#define GC_AES_DAES_INT_ENABLE_DONE_CIPHER_DEFAULT 0x0 +#define GC_AES_DAES_INT_ENABLE_DONE_CIPHER_OFFSET 0xd0 +#define GC_AES_DAES_INT_ENABLE_DONE_KEYEXPANSION_LSB 0x4 +#define GC_AES_DAES_INT_ENABLE_DONE_KEYEXPANSION_MASK 0x10 +#define GC_AES_DAES_INT_ENABLE_DONE_KEYEXPANSION_SIZE 0x1 +#define GC_AES_DAES_INT_ENABLE_DONE_KEYEXPANSION_DEFAULT 0x0 +#define GC_AES_DAES_INT_ENABLE_DONE_KEYEXPANSION_OFFSET 0xd0 +#define GC_AES_DAES_INT_ENABLE_DONE_WIPE_SECRETS_LSB 0x5 +#define GC_AES_DAES_INT_ENABLE_DONE_WIPE_SECRETS_MASK 0x20 +#define GC_AES_DAES_INT_ENABLE_DONE_WIPE_SECRETS_SIZE 0x1 +#define GC_AES_DAES_INT_ENABLE_DONE_WIPE_SECRETS_DEFAULT 0x0 +#define GC_AES_DAES_INT_ENABLE_DONE_WIPE_SECRETS_OFFSET 0xd0 +#define GC_AES_DAES_INT_STATE_WFIFO_OVERFLOW_LSB 0x0 +#define GC_AES_DAES_INT_STATE_WFIFO_OVERFLOW_MASK 0x1 +#define GC_AES_DAES_INT_STATE_WFIFO_OVERFLOW_SIZE 0x1 +#define GC_AES_DAES_INT_STATE_WFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_AES_DAES_INT_STATE_WFIFO_OVERFLOW_OFFSET 0xd4 +#define GC_AES_DAES_INT_STATE_RFIFO_OVERFLOW_LSB 0x1 +#define GC_AES_DAES_INT_STATE_RFIFO_OVERFLOW_MASK 0x2 +#define GC_AES_DAES_INT_STATE_RFIFO_OVERFLOW_SIZE 0x1 +#define GC_AES_DAES_INT_STATE_RFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_AES_DAES_INT_STATE_RFIFO_OVERFLOW_OFFSET 0xd4 +#define GC_AES_DAES_INT_STATE_RFIFO_UNDERFLOW_LSB 0x2 +#define GC_AES_DAES_INT_STATE_RFIFO_UNDERFLOW_MASK 0x4 +#define GC_AES_DAES_INT_STATE_RFIFO_UNDERFLOW_SIZE 0x1 +#define GC_AES_DAES_INT_STATE_RFIFO_UNDERFLOW_DEFAULT 0x0 +#define GC_AES_DAES_INT_STATE_RFIFO_UNDERFLOW_OFFSET 0xd4 +#define GC_AES_DAES_INT_STATE_DONE_CIPHER_LSB 0x3 +#define GC_AES_DAES_INT_STATE_DONE_CIPHER_MASK 0x8 +#define GC_AES_DAES_INT_STATE_DONE_CIPHER_SIZE 0x1 +#define GC_AES_DAES_INT_STATE_DONE_CIPHER_DEFAULT 0x0 +#define GC_AES_DAES_INT_STATE_DONE_CIPHER_OFFSET 0xd4 +#define GC_AES_DAES_INT_STATE_DONE_KEYEXPANSION_LSB 0x4 +#define GC_AES_DAES_INT_STATE_DONE_KEYEXPANSION_MASK 0x10 +#define GC_AES_DAES_INT_STATE_DONE_KEYEXPANSION_SIZE 0x1 +#define GC_AES_DAES_INT_STATE_DONE_KEYEXPANSION_DEFAULT 0x0 +#define GC_AES_DAES_INT_STATE_DONE_KEYEXPANSION_OFFSET 0xd4 +#define GC_AES_DAES_INT_STATE_DONE_WIPE_SECRETS_LSB 0x5 +#define GC_AES_DAES_INT_STATE_DONE_WIPE_SECRETS_MASK 0x20 +#define GC_AES_DAES_INT_STATE_DONE_WIPE_SECRETS_SIZE 0x1 +#define GC_AES_DAES_INT_STATE_DONE_WIPE_SECRETS_DEFAULT 0x0 +#define GC_AES_DAES_INT_STATE_DONE_WIPE_SECRETS_OFFSET 0xd4 +#define GC_AES_DAES_INT_TEST_WFIFO_OVERFLOW_LSB 0x0 +#define GC_AES_DAES_INT_TEST_WFIFO_OVERFLOW_MASK 0x1 +#define GC_AES_DAES_INT_TEST_WFIFO_OVERFLOW_SIZE 0x1 +#define GC_AES_DAES_INT_TEST_WFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_AES_DAES_INT_TEST_WFIFO_OVERFLOW_OFFSET 0xd8 +#define GC_AES_DAES_INT_TEST_RFIFO_OVERFLOW_LSB 0x1 +#define GC_AES_DAES_INT_TEST_RFIFO_OVERFLOW_MASK 0x2 +#define GC_AES_DAES_INT_TEST_RFIFO_OVERFLOW_SIZE 0x1 +#define GC_AES_DAES_INT_TEST_RFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_AES_DAES_INT_TEST_RFIFO_OVERFLOW_OFFSET 0xd8 +#define GC_AES_DAES_INT_TEST_RFIFO_UNDERFLOW_LSB 0x2 +#define GC_AES_DAES_INT_TEST_RFIFO_UNDERFLOW_MASK 0x4 +#define GC_AES_DAES_INT_TEST_RFIFO_UNDERFLOW_SIZE 0x1 +#define GC_AES_DAES_INT_TEST_RFIFO_UNDERFLOW_DEFAULT 0x0 +#define GC_AES_DAES_INT_TEST_RFIFO_UNDERFLOW_OFFSET 0xd8 +#define GC_AES_DAES_INT_TEST_DONE_CIPHER_LSB 0x3 +#define GC_AES_DAES_INT_TEST_DONE_CIPHER_MASK 0x8 +#define GC_AES_DAES_INT_TEST_DONE_CIPHER_SIZE 0x1 +#define GC_AES_DAES_INT_TEST_DONE_CIPHER_DEFAULT 0x0 +#define GC_AES_DAES_INT_TEST_DONE_CIPHER_OFFSET 0xd8 +#define GC_AES_DAES_INT_TEST_DONE_KEYEXPANSION_LSB 0x4 +#define GC_AES_DAES_INT_TEST_DONE_KEYEXPANSION_MASK 0x10 +#define GC_AES_DAES_INT_TEST_DONE_KEYEXPANSION_SIZE 0x1 +#define GC_AES_DAES_INT_TEST_DONE_KEYEXPANSION_DEFAULT 0x0 +#define GC_AES_DAES_INT_TEST_DONE_KEYEXPANSION_OFFSET 0xd8 +#define GC_AES_DAES_INT_TEST_DONE_WIPE_SECRETS_LSB 0x5 +#define GC_AES_DAES_INT_TEST_DONE_WIPE_SECRETS_MASK 0x20 +#define GC_AES_DAES_INT_TEST_DONE_WIPE_SECRETS_SIZE 0x1 +#define GC_AES_DAES_INT_TEST_DONE_WIPE_SECRETS_DEFAULT 0x0 +#define GC_AES_DAES_INT_TEST_DONE_WIPE_SECRETS_OFFSET 0xd8 #define GC_CAMO_VERSION_CHANGE_LSB 0x0 #define GC_CAMO_VERSION_CHANGE_MASK 0xffffff #define GC_CAMO_VERSION_CHANGE_SIZE 0x18 -#define GC_CAMO_VERSION_CHANGE_DEFAULT 0xba73 -#define GC_CAMO_VERSION_CHANGE_OFFSET 0x28 +#define GC_CAMO_VERSION_CHANGE_DEFAULT 0xe1a1 +#define GC_CAMO_VERSION_CHANGE_OFFSET 0x10 #define GC_CAMO_VERSION_REVISION_LSB 0x18 #define GC_CAMO_VERSION_REVISION_MASK 0xff000000 #define GC_CAMO_VERSION_REVISION_SIZE 0x8 -#define GC_CAMO_VERSION_REVISION_DEFAULT 0x5 -#define GC_CAMO_VERSION_REVISION_OFFSET 0x28 +#define GC_CAMO_VERSION_REVISION_DEFAULT 0x2 +#define GC_CAMO_VERSION_REVISION_OFFSET 0x10 +#define GC_CRYPTO_VERSION_CHANGE_LSB 0x0 +#define GC_CRYPTO_VERSION_CHANGE_MASK 0xffffff +#define GC_CRYPTO_VERSION_CHANGE_SIZE 0x18 +#define GC_CRYPTO_VERSION_CHANGE_DEFAULT 0x105b6 +#define GC_CRYPTO_VERSION_CHANGE_OFFSET 0x0 +#define GC_CRYPTO_VERSION_REVISION_LSB 0x18 +#define GC_CRYPTO_VERSION_REVISION_MASK 0xff000000 +#define GC_CRYPTO_VERSION_REVISION_SIZE 0x8 +#define GC_CRYPTO_VERSION_REVISION_DEFAULT 0x23 +#define GC_CRYPTO_VERSION_REVISION_OFFSET 0x0 +#define GC_CRYPTO_CONTROL_RESET_LSB 0x0 +#define GC_CRYPTO_CONTROL_RESET_MASK 0x1 +#define GC_CRYPTO_CONTROL_RESET_SIZE 0x1 +#define GC_CRYPTO_CONTROL_RESET_DEFAULT 0x0 +#define GC_CRYPTO_CONTROL_RESET_OFFSET 0x4 +#define GC_CRYPTO_CONTROL_BREAK_LSB 0x1 +#define GC_CRYPTO_CONTROL_BREAK_MASK 0x2 +#define GC_CRYPTO_CONTROL_BREAK_SIZE 0x1 +#define GC_CRYPTO_CONTROL_BREAK_DEFAULT 0x0 +#define GC_CRYPTO_CONTROL_BREAK_OFFSET 0x4 +#define GC_CRYPTO_CONTROL_RESUME_LSB 0x2 +#define GC_CRYPTO_CONTROL_RESUME_MASK 0x4 +#define GC_CRYPTO_CONTROL_RESUME_SIZE 0x1 +#define GC_CRYPTO_CONTROL_RESUME_DEFAULT 0x0 +#define GC_CRYPTO_CONTROL_RESUME_OFFSET 0x4 +#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_LSB 0x0 +#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_MASK 0x1 +#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_SIZE 0x1 +#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_DEFAULT 0x0 +#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_OFFSET 0x8 +#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_LSB 0x1 +#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_MASK 0x2 +#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_SIZE 0x1 +#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_DEFAULT 0x0 +#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_OFFSET 0x8 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_LSB 0x2 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_MASK 0x4 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_SIZE 0x1 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_DEFAULT 0x0 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_OFFSET 0x8 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_LSB 0x3 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_MASK 0x8 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_SIZE 0x1 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_DEFAULT 0x0 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_OFFSET 0x8 +#define GC_CRYPTO_CONFIG_SCRUB_FREQ_LSB 0x4 +#define GC_CRYPTO_CONFIG_SCRUB_FREQ_MASK 0x30 +#define GC_CRYPTO_CONFIG_SCRUB_FREQ_SIZE 0x2 +#define GC_CRYPTO_CONFIG_SCRUB_FREQ_DEFAULT 0x1 +#define GC_CRYPTO_CONFIG_SCRUB_FREQ_OFFSET 0x8 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_LSB 0x6 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_MASK 0x40 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_SIZE 0x1 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_DEFAULT 0x0 +#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_OFFSET 0x8 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_LSB 0x7 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_MASK 0x80 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_SIZE 0x1 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_DEFAULT 0x0 +#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_OFFSET 0x8 +#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_LSB 0x8 +#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_MASK 0x100 +#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_SIZE 0x1 +#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_DEFAULT 0x0 +#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_OFFSET 0x8 +#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_LSB 0x0 +#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_MASK 0x3ff +#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_SIZE 0xa +#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_DEFAULT 0x3ff +#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_OFFSET 0xc +#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_LSB 0xa +#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_MASK 0xffc00 +#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_SIZE 0xa +#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_DEFAULT 0x0 +#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_OFFSET 0xc +#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_LSB 0x0 +#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_MASK 0x7f +#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_SIZE 0x7 +#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_DEFAULT 0x7f +#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_OFFSET 0x10 +#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_LSB 0x7 +#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_MASK 0x3f80 +#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_SIZE 0x7 +#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_DEFAULT 0x0 +#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_OFFSET 0x10 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_LSB 0x0 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_MASK 0x1 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_LSB 0x1 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_MASK 0x2 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_LSB 0x2 +#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_MASK 0x4 +#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_LSB 0x3 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_MASK 0x8 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_LSB 0x4 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_MASK 0x10 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_LSB 0x5 +#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_MASK 0x20 +#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_LSB 0x6 +#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_MASK 0x40 +#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_BREAK_LSB 0x7 +#define GC_CRYPTO_INT_ENABLE_BREAK_MASK 0x80 +#define GC_CRYPTO_INT_ENABLE_BREAK_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_BREAK_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_BREAK_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_TRAP_LSB 0x8 +#define GC_CRYPTO_INT_ENABLE_TRAP_MASK 0x100 +#define GC_CRYPTO_INT_ENABLE_TRAP_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_TRAP_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_TRAP_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_LSB 0x9 +#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_MASK 0x200 +#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_OFFSET 0x14 +#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_LSB 0x0 +#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_MASK 0x1 +#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_LSB 0x1 +#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_MASK 0x2 +#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_LSB 0x2 +#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_MASK 0x4 +#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_LSB 0x3 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_MASK 0x8 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_LSB 0x4 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_MASK 0x10 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_LSB 0x5 +#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_MASK 0x20 +#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_LSB 0x6 +#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_MASK 0x40 +#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_BREAK_LSB 0x7 +#define GC_CRYPTO_INT_STATE_BREAK_MASK 0x80 +#define GC_CRYPTO_INT_STATE_BREAK_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_BREAK_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_BREAK_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_TRAP_LSB 0x8 +#define GC_CRYPTO_INT_STATE_TRAP_MASK 0x100 +#define GC_CRYPTO_INT_STATE_TRAP_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_TRAP_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_TRAP_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_LSB 0x9 +#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_MASK 0x200 +#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_OFFSET 0x18 +#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_LSB 0x0 +#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_MASK 0x1 +#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_LSB 0x1 +#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_MASK 0x2 +#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_LSB 0x2 +#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_MASK 0x4 +#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_LSB 0x3 +#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_MASK 0x8 +#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_LSB 0x4 +#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_MASK 0x10 +#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_LSB 0x5 +#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_MASK 0x20 +#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_LSB 0x6 +#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_MASK 0x40 +#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_BREAK_LSB 0x7 +#define GC_CRYPTO_INT_TEST_BREAK_MASK 0x80 +#define GC_CRYPTO_INT_TEST_BREAK_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_BREAK_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_BREAK_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_TRAP_LSB 0x8 +#define GC_CRYPTO_INT_TEST_TRAP_MASK 0x100 +#define GC_CRYPTO_INT_TEST_TRAP_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_TRAP_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_TRAP_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_LSB 0x9 +#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_MASK 0x200 +#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_OFFSET 0x1c +#define GC_CRYPTO_HOST_CMD_INSTR_LSB 0x0 +#define GC_CRYPTO_HOST_CMD_INSTR_MASK 0xffffffff +#define GC_CRYPTO_HOST_CMD_INSTR_SIZE 0x20 +#define GC_CRYPTO_HOST_CMD_INSTR_DEFAULT 0xffffffff +#define GC_CRYPTO_HOST_CMD_INSTR_OFFSET 0x20 +#define GC_CRYPTO_INSTR_PC_LSB 0x0 +#define GC_CRYPTO_INSTR_PC_MASK 0x3ff +#define GC_CRYPTO_INSTR_PC_SIZE 0xa +#define GC_CRYPTO_INSTR_PC_DEFAULT 0x0 +#define GC_CRYPTO_INSTR_PC_OFFSET 0x24 +#define GC_CRYPTO_STATUS_STATE_LSB 0x0 +#define GC_CRYPTO_STATUS_STATE_MASK 0x3 +#define GC_CRYPTO_STATUS_STATE_SIZE 0x2 +#define GC_CRYPTO_STATUS_STATE_DEFAULT 0x0 +#define GC_CRYPTO_STATUS_STATE_OFFSET 0x28 +#define GC_CRYPTO_STATUS_L_LSB 0x2 +#define GC_CRYPTO_STATUS_L_MASK 0x4 +#define GC_CRYPTO_STATUS_L_SIZE 0x1 +#define GC_CRYPTO_STATUS_L_DEFAULT 0x0 +#define GC_CRYPTO_STATUS_L_OFFSET 0x28 +#define GC_CRYPTO_STATUS_M_LSB 0x3 +#define GC_CRYPTO_STATUS_M_MASK 0x8 +#define GC_CRYPTO_STATUS_M_SIZE 0x1 +#define GC_CRYPTO_STATUS_M_DEFAULT 0x0 +#define GC_CRYPTO_STATUS_M_OFFSET 0x28 +#define GC_CRYPTO_STATUS_Z_LSB 0x4 +#define GC_CRYPTO_STATUS_Z_MASK 0x10 +#define GC_CRYPTO_STATUS_Z_SIZE 0x1 +#define GC_CRYPTO_STATUS_Z_DEFAULT 0x0 +#define GC_CRYPTO_STATUS_Z_OFFSET 0x28 +#define GC_CRYPTO_STATUS_C_LSB 0x5 +#define GC_CRYPTO_STATUS_C_MASK 0x20 +#define GC_CRYPTO_STATUS_C_SIZE 0x1 +#define GC_CRYPTO_STATUS_C_DEFAULT 0x0 +#define GC_CRYPTO_STATUS_C_OFFSET 0x28 +#define GC_CRYPTO_AUX_CC_L_LSB 0x0 +#define GC_CRYPTO_AUX_CC_L_MASK 0x1 +#define GC_CRYPTO_AUX_CC_L_SIZE 0x1 +#define GC_CRYPTO_AUX_CC_L_DEFAULT 0x0 +#define GC_CRYPTO_AUX_CC_L_OFFSET 0x2c +#define GC_CRYPTO_AUX_CC_M_LSB 0x1 +#define GC_CRYPTO_AUX_CC_M_MASK 0x2 +#define GC_CRYPTO_AUX_CC_M_SIZE 0x1 +#define GC_CRYPTO_AUX_CC_M_DEFAULT 0x0 +#define GC_CRYPTO_AUX_CC_M_OFFSET 0x2c +#define GC_CRYPTO_AUX_CC_Z_LSB 0x2 +#define GC_CRYPTO_AUX_CC_Z_MASK 0x4 +#define GC_CRYPTO_AUX_CC_Z_SIZE 0x1 +#define GC_CRYPTO_AUX_CC_Z_DEFAULT 0x0 +#define GC_CRYPTO_AUX_CC_Z_OFFSET 0x2c +#define GC_CRYPTO_AUX_CC_C_LSB 0x3 +#define GC_CRYPTO_AUX_CC_C_MASK 0x8 +#define GC_CRYPTO_AUX_CC_C_SIZE 0x1 +#define GC_CRYPTO_AUX_CC_C_DEFAULT 0x0 +#define GC_CRYPTO_AUX_CC_C_OFFSET 0x2c +#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_LSB 0x0 +#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_MASK 0x1 +#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_SIZE 0x1 +#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_DEFAULT 0x1 +#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_OFFSET 0x30 +#define GC_CRYPTO_RAND_STALL_CTL_FREQ_LSB 0x1 +#define GC_CRYPTO_RAND_STALL_CTL_FREQ_MASK 0x6 +#define GC_CRYPTO_RAND_STALL_CTL_FREQ_SIZE 0x2 +#define GC_CRYPTO_RAND_STALL_CTL_FREQ_DEFAULT 0x2 +#define GC_CRYPTO_RAND_STALL_CTL_FREQ_OFFSET 0x30 +#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_LSB 0x0 +#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_MASK 0xffff +#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_SIZE 0x10 +#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_DEFAULT 0x0 +#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_OFFSET 0x40 +#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_LSB 0x0 +#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_MASK 0xffff +#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_SIZE 0x10 +#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_DEFAULT 0x0 +#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_OFFSET 0x44 +#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_LSB 0x0 +#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_MASK 0xffff +#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_SIZE 0x10 +#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_DEFAULT 0x0 +#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_OFFSET 0x48 +#define GC_CRYPTO_PGM_LFSR_SIG_LSB 0x0 +#define GC_CRYPTO_PGM_LFSR_SIG_MASK 0xffffff +#define GC_CRYPTO_PGM_LFSR_SIG_SIZE 0x18 +#define GC_CRYPTO_PGM_LFSR_SIG_DEFAULT 0x0 +#define GC_CRYPTO_PGM_LFSR_SIG_OFFSET 0x4c +#define GC_CRYPTO_DEBUG_BRKPT0_PC_LSB 0x0 +#define GC_CRYPTO_DEBUG_BRKPT0_PC_MASK 0x3ff +#define GC_CRYPTO_DEBUG_BRKPT0_PC_SIZE 0xa +#define GC_CRYPTO_DEBUG_BRKPT0_PC_DEFAULT 0x0 +#define GC_CRYPTO_DEBUG_BRKPT0_PC_OFFSET 0x50 +#define GC_CRYPTO_DEBUG_BRKPT0_EN_LSB 0x1f +#define GC_CRYPTO_DEBUG_BRKPT0_EN_MASK 0x80000000 +#define GC_CRYPTO_DEBUG_BRKPT0_EN_SIZE 0x1 +#define GC_CRYPTO_DEBUG_BRKPT0_EN_DEFAULT 0x0 +#define GC_CRYPTO_DEBUG_BRKPT0_EN_OFFSET 0x50 +#define GC_CRYPTO_DEBUG_BRKPT1_PC_LSB 0x0 +#define GC_CRYPTO_DEBUG_BRKPT1_PC_MASK 0x3ff +#define GC_CRYPTO_DEBUG_BRKPT1_PC_SIZE 0xa +#define GC_CRYPTO_DEBUG_BRKPT1_PC_DEFAULT 0x0 +#define GC_CRYPTO_DEBUG_BRKPT1_PC_OFFSET 0x54 +#define GC_CRYPTO_DEBUG_BRKPT1_EN_LSB 0x1f +#define GC_CRYPTO_DEBUG_BRKPT1_EN_MASK 0x80000000 +#define GC_CRYPTO_DEBUG_BRKPT1_EN_SIZE 0x1 +#define GC_CRYPTO_DEBUG_BRKPT1_EN_DEFAULT 0x0 +#define GC_CRYPTO_DEBUG_BRKPT1_EN_OFFSET 0x54 +#define GC_DMA_VERSION_CHANGE_LSB 0x0 +#define GC_DMA_VERSION_CHANGE_MASK 0xffffff +#define GC_DMA_VERSION_CHANGE_SIZE 0x18 +#define GC_DMA_VERSION_CHANGE_DEFAULT 0x10532 +#define GC_DMA_VERSION_CHANGE_OFFSET 0x0 +#define GC_DMA_VERSION_REVISION_LSB 0x18 +#define GC_DMA_VERSION_REVISION_MASK 0xff000000 +#define GC_DMA_VERSION_REVISION_SIZE 0x8 +#define GC_DMA_VERSION_REVISION_DEFAULT 0xf +#define GC_DMA_VERSION_REVISION_OFFSET 0x0 +#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_LSB 0x0 +#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_MASK 0xff +#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_SIZE 0x8 +#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_OFFSET 0x4 +#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_LSB 0x8 +#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_MASK 0xff00 +#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_SIZE 0x8 +#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_OFFSET 0x4 +#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_LSB 0x10 +#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_MASK 0xff0000 +#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_SIZE 0x8 +#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_OFFSET 0x4 +#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_LSB 0x18 +#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_MASK 0xff000000 +#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_SIZE 0x8 +#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_OFFSET 0x4 +#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_LSB 0x0 +#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_MASK 0xff +#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_SIZE 0x8 +#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_OFFSET 0x8 +#define GC_DMA_INT_STATE_INTR_PROG_CHAN_LSB 0x8 +#define GC_DMA_INT_STATE_INTR_PROG_CHAN_MASK 0xff00 +#define GC_DMA_INT_STATE_INTR_PROG_CHAN_SIZE 0x8 +#define GC_DMA_INT_STATE_INTR_PROG_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_STATE_INTR_PROG_CHAN_OFFSET 0x8 +#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_LSB 0x10 +#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_MASK 0xff0000 +#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_SIZE 0x8 +#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_OFFSET 0x8 +#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_LSB 0x18 +#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_MASK 0xff000000 +#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_SIZE 0x8 +#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_OFFSET 0x8 +#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_LSB 0x0 +#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_MASK 0xff +#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_SIZE 0x8 +#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_OFFSET 0xc +#define GC_DMA_INT_TEST_INTR_PROG_CHAN_LSB 0x8 +#define GC_DMA_INT_TEST_INTR_PROG_CHAN_MASK 0xff00 +#define GC_DMA_INT_TEST_INTR_PROG_CHAN_SIZE 0x8 +#define GC_DMA_INT_TEST_INTR_PROG_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_TEST_INTR_PROG_CHAN_OFFSET 0xc +#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_LSB 0x10 +#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_MASK 0xff0000 +#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_SIZE 0x8 +#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_OFFSET 0xc +#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_LSB 0x18 +#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_MASK 0xff000000 +#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_SIZE 0x8 +#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_DEFAULT 0x0 +#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_OFFSET 0xc +#define GC_DMA_CTRL_CHAN0_ENABLE_LSB 0x0 +#define GC_DMA_CTRL_CHAN0_ENABLE_MASK 0x1 +#define GC_DMA_CTRL_CHAN0_ENABLE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN0_ENABLE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_ENABLE_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_STOP_LSB 0x1 +#define GC_DMA_CTRL_CHAN0_STOP_MASK 0x2 +#define GC_DMA_CTRL_CHAN0_STOP_SIZE 0x1 +#define GC_DMA_CTRL_CHAN0_STOP_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_STOP_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_CLR_ERROR_LSB 0x2 +#define GC_DMA_CTRL_CHAN0_CLR_ERROR_MASK 0x4 +#define GC_DMA_CTRL_CHAN0_CLR_ERROR_SIZE 0x1 +#define GC_DMA_CTRL_CHAN0_CLR_ERROR_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_CLR_ERROR_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_WRAP_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN0_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN0_WRAP_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN0_WRAP_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_WRAP_MODE_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_LSB 0x5 +#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_LSB 0x6 +#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_LSB 0x7 +#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_SIZE 0x1 +#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_NCHK_FULL_LSB 0x8 +#define GC_DMA_CTRL_CHAN0_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN0_NCHK_FULL_SIZE 0x1 +#define GC_DMA_CTRL_CHAN0_NCHK_FULL_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_NCHK_FULL_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_LSB 0x9 +#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_LSB 0xc +#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_OFFSET 0x100 +#define GC_DMA_FSM_STATE_CHAN0_IDLE_LSB 0x0 +#define GC_DMA_FSM_STATE_CHAN0_IDLE_MASK 0x1 +#define GC_DMA_FSM_STATE_CHAN0_IDLE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_IDLE_DEFAULT 0x1 +#define GC_DMA_FSM_STATE_CHAN0_IDLE_OFFSET 0x120 +#define GC_DMA_FSM_STATE_CHAN0_WAIT_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN0_WAIT_MASK 0x2 +#define GC_DMA_FSM_STATE_CHAN0_WAIT_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_WAIT_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_WAIT_OFFSET 0x120 +#define GC_DMA_FSM_STATE_CHAN0_BID_READ_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN0_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN0_BID_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_BID_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_BID_READ_OFFSET 0x120 +#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_OFFSET 0x120 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_OFFSET 0x120 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_OFFSET 0x120 +#define GC_DMA_FSM_STATE_CHAN0_READ_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN0_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN0_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_READ_OFFSET 0x120 +#define GC_DMA_FSM_STATE_CHAN0_WRITE_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN0_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN0_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_WRITE_OFFSET 0x120 +#define GC_DMA_FSM_STATE_CHAN0_ERROR_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN0_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN0_ERROR_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_ERROR_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_ERROR_OFFSET 0x120 +#define GC_DMA_CTRL_CHAN1_ENABLE_LSB 0x0 +#define GC_DMA_CTRL_CHAN1_ENABLE_MASK 0x1 +#define GC_DMA_CTRL_CHAN1_ENABLE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN1_ENABLE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_ENABLE_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_STOP_LSB 0x1 +#define GC_DMA_CTRL_CHAN1_STOP_MASK 0x2 +#define GC_DMA_CTRL_CHAN1_STOP_SIZE 0x1 +#define GC_DMA_CTRL_CHAN1_STOP_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_STOP_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_CLR_ERROR_LSB 0x2 +#define GC_DMA_CTRL_CHAN1_CLR_ERROR_MASK 0x4 +#define GC_DMA_CTRL_CHAN1_CLR_ERROR_SIZE 0x1 +#define GC_DMA_CTRL_CHAN1_CLR_ERROR_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_CLR_ERROR_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_WRAP_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN1_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN1_WRAP_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN1_WRAP_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_WRAP_MODE_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_LSB 0x5 +#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_LSB 0x6 +#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_LSB 0x7 +#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_SIZE 0x1 +#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_NCHK_FULL_LSB 0x8 +#define GC_DMA_CTRL_CHAN1_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN1_NCHK_FULL_SIZE 0x1 +#define GC_DMA_CTRL_CHAN1_NCHK_FULL_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_NCHK_FULL_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_LSB 0x9 +#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_LSB 0xc +#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_OFFSET 0x200 +#define GC_DMA_FSM_STATE_CHAN1_IDLE_LSB 0x0 +#define GC_DMA_FSM_STATE_CHAN1_IDLE_MASK 0x1 +#define GC_DMA_FSM_STATE_CHAN1_IDLE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_IDLE_DEFAULT 0x1 +#define GC_DMA_FSM_STATE_CHAN1_IDLE_OFFSET 0x220 +#define GC_DMA_FSM_STATE_CHAN1_WAIT_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN1_WAIT_MASK 0x2 +#define GC_DMA_FSM_STATE_CHAN1_WAIT_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_WAIT_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_WAIT_OFFSET 0x220 +#define GC_DMA_FSM_STATE_CHAN1_BID_READ_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN1_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN1_BID_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_BID_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_BID_READ_OFFSET 0x220 +#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_OFFSET 0x220 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_OFFSET 0x220 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_OFFSET 0x220 +#define GC_DMA_FSM_STATE_CHAN1_READ_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN1_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN1_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_READ_OFFSET 0x220 +#define GC_DMA_FSM_STATE_CHAN1_WRITE_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN1_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN1_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_WRITE_OFFSET 0x220 +#define GC_DMA_FSM_STATE_CHAN1_ERROR_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN1_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN1_ERROR_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_ERROR_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_ERROR_OFFSET 0x220 +#define GC_DMA_CTRL_CHAN2_ENABLE_LSB 0x0 +#define GC_DMA_CTRL_CHAN2_ENABLE_MASK 0x1 +#define GC_DMA_CTRL_CHAN2_ENABLE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN2_ENABLE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_ENABLE_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_STOP_LSB 0x1 +#define GC_DMA_CTRL_CHAN2_STOP_MASK 0x2 +#define GC_DMA_CTRL_CHAN2_STOP_SIZE 0x1 +#define GC_DMA_CTRL_CHAN2_STOP_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_STOP_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_CLR_ERROR_LSB 0x2 +#define GC_DMA_CTRL_CHAN2_CLR_ERROR_MASK 0x4 +#define GC_DMA_CTRL_CHAN2_CLR_ERROR_SIZE 0x1 +#define GC_DMA_CTRL_CHAN2_CLR_ERROR_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_CLR_ERROR_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_WRAP_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN2_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN2_WRAP_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN2_WRAP_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_WRAP_MODE_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_LSB 0x5 +#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_LSB 0x6 +#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_LSB 0x7 +#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_SIZE 0x1 +#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_NCHK_FULL_LSB 0x8 +#define GC_DMA_CTRL_CHAN2_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN2_NCHK_FULL_SIZE 0x1 +#define GC_DMA_CTRL_CHAN2_NCHK_FULL_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_NCHK_FULL_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_LSB 0x9 +#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_LSB 0xc +#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_OFFSET 0x300 +#define GC_DMA_FSM_STATE_CHAN2_IDLE_LSB 0x0 +#define GC_DMA_FSM_STATE_CHAN2_IDLE_MASK 0x1 +#define GC_DMA_FSM_STATE_CHAN2_IDLE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_IDLE_DEFAULT 0x1 +#define GC_DMA_FSM_STATE_CHAN2_IDLE_OFFSET 0x320 +#define GC_DMA_FSM_STATE_CHAN2_WAIT_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN2_WAIT_MASK 0x2 +#define GC_DMA_FSM_STATE_CHAN2_WAIT_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_WAIT_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_WAIT_OFFSET 0x320 +#define GC_DMA_FSM_STATE_CHAN2_BID_READ_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN2_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN2_BID_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_BID_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_BID_READ_OFFSET 0x320 +#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_OFFSET 0x320 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_OFFSET 0x320 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_OFFSET 0x320 +#define GC_DMA_FSM_STATE_CHAN2_READ_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN2_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN2_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_READ_OFFSET 0x320 +#define GC_DMA_FSM_STATE_CHAN2_WRITE_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN2_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN2_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_WRITE_OFFSET 0x320 +#define GC_DMA_FSM_STATE_CHAN2_ERROR_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN2_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN2_ERROR_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_ERROR_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_ERROR_OFFSET 0x320 +#define GC_DMA_CTRL_CHAN3_ENABLE_LSB 0x0 +#define GC_DMA_CTRL_CHAN3_ENABLE_MASK 0x1 +#define GC_DMA_CTRL_CHAN3_ENABLE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN3_ENABLE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_ENABLE_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_STOP_LSB 0x1 +#define GC_DMA_CTRL_CHAN3_STOP_MASK 0x2 +#define GC_DMA_CTRL_CHAN3_STOP_SIZE 0x1 +#define GC_DMA_CTRL_CHAN3_STOP_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_STOP_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_CLR_ERROR_LSB 0x2 +#define GC_DMA_CTRL_CHAN3_CLR_ERROR_MASK 0x4 +#define GC_DMA_CTRL_CHAN3_CLR_ERROR_SIZE 0x1 +#define GC_DMA_CTRL_CHAN3_CLR_ERROR_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_CLR_ERROR_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_WRAP_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN3_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN3_WRAP_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN3_WRAP_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_WRAP_MODE_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_LSB 0x5 +#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_LSB 0x6 +#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_LSB 0x7 +#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_SIZE 0x1 +#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_NCHK_FULL_LSB 0x8 +#define GC_DMA_CTRL_CHAN3_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN3_NCHK_FULL_SIZE 0x1 +#define GC_DMA_CTRL_CHAN3_NCHK_FULL_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_NCHK_FULL_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_LSB 0x9 +#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_LSB 0xc +#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_OFFSET 0x400 +#define GC_DMA_FSM_STATE_CHAN3_IDLE_LSB 0x0 +#define GC_DMA_FSM_STATE_CHAN3_IDLE_MASK 0x1 +#define GC_DMA_FSM_STATE_CHAN3_IDLE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_IDLE_DEFAULT 0x1 +#define GC_DMA_FSM_STATE_CHAN3_IDLE_OFFSET 0x420 +#define GC_DMA_FSM_STATE_CHAN3_WAIT_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN3_WAIT_MASK 0x2 +#define GC_DMA_FSM_STATE_CHAN3_WAIT_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_WAIT_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_WAIT_OFFSET 0x420 +#define GC_DMA_FSM_STATE_CHAN3_BID_READ_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN3_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN3_BID_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_BID_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_BID_READ_OFFSET 0x420 +#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_OFFSET 0x420 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_OFFSET 0x420 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_OFFSET 0x420 +#define GC_DMA_FSM_STATE_CHAN3_READ_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN3_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN3_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_READ_OFFSET 0x420 +#define GC_DMA_FSM_STATE_CHAN3_WRITE_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN3_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN3_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_WRITE_OFFSET 0x420 +#define GC_DMA_FSM_STATE_CHAN3_ERROR_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN3_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN3_ERROR_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_ERROR_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_ERROR_OFFSET 0x420 +#define GC_DMA_CTRL_CHAN4_ENABLE_LSB 0x0 +#define GC_DMA_CTRL_CHAN4_ENABLE_MASK 0x1 +#define GC_DMA_CTRL_CHAN4_ENABLE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN4_ENABLE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_ENABLE_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_STOP_LSB 0x1 +#define GC_DMA_CTRL_CHAN4_STOP_MASK 0x2 +#define GC_DMA_CTRL_CHAN4_STOP_SIZE 0x1 +#define GC_DMA_CTRL_CHAN4_STOP_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_STOP_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_CLR_ERROR_LSB 0x2 +#define GC_DMA_CTRL_CHAN4_CLR_ERROR_MASK 0x4 +#define GC_DMA_CTRL_CHAN4_CLR_ERROR_SIZE 0x1 +#define GC_DMA_CTRL_CHAN4_CLR_ERROR_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_CLR_ERROR_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_WRAP_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN4_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN4_WRAP_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN4_WRAP_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_WRAP_MODE_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_LSB 0x5 +#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_LSB 0x6 +#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_LSB 0x7 +#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_SIZE 0x1 +#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_NCHK_FULL_LSB 0x8 +#define GC_DMA_CTRL_CHAN4_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN4_NCHK_FULL_SIZE 0x1 +#define GC_DMA_CTRL_CHAN4_NCHK_FULL_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_NCHK_FULL_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_LSB 0x9 +#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_LSB 0xc +#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_OFFSET 0x500 +#define GC_DMA_FSM_STATE_CHAN4_IDLE_LSB 0x0 +#define GC_DMA_FSM_STATE_CHAN4_IDLE_MASK 0x1 +#define GC_DMA_FSM_STATE_CHAN4_IDLE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_IDLE_DEFAULT 0x1 +#define GC_DMA_FSM_STATE_CHAN4_IDLE_OFFSET 0x520 +#define GC_DMA_FSM_STATE_CHAN4_WAIT_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN4_WAIT_MASK 0x2 +#define GC_DMA_FSM_STATE_CHAN4_WAIT_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_WAIT_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_WAIT_OFFSET 0x520 +#define GC_DMA_FSM_STATE_CHAN4_BID_READ_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN4_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN4_BID_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_BID_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_BID_READ_OFFSET 0x520 +#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_OFFSET 0x520 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_OFFSET 0x520 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_OFFSET 0x520 +#define GC_DMA_FSM_STATE_CHAN4_READ_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN4_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN4_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_READ_OFFSET 0x520 +#define GC_DMA_FSM_STATE_CHAN4_WRITE_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN4_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN4_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_WRITE_OFFSET 0x520 +#define GC_DMA_FSM_STATE_CHAN4_ERROR_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN4_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN4_ERROR_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_ERROR_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_ERROR_OFFSET 0x520 +#define GC_DMA_CTRL_CHAN5_ENABLE_LSB 0x0 +#define GC_DMA_CTRL_CHAN5_ENABLE_MASK 0x1 +#define GC_DMA_CTRL_CHAN5_ENABLE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN5_ENABLE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_ENABLE_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_STOP_LSB 0x1 +#define GC_DMA_CTRL_CHAN5_STOP_MASK 0x2 +#define GC_DMA_CTRL_CHAN5_STOP_SIZE 0x1 +#define GC_DMA_CTRL_CHAN5_STOP_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_STOP_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_CLR_ERROR_LSB 0x2 +#define GC_DMA_CTRL_CHAN5_CLR_ERROR_MASK 0x4 +#define GC_DMA_CTRL_CHAN5_CLR_ERROR_SIZE 0x1 +#define GC_DMA_CTRL_CHAN5_CLR_ERROR_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_CLR_ERROR_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_WRAP_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN5_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN5_WRAP_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN5_WRAP_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_WRAP_MODE_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_LSB 0x5 +#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_LSB 0x6 +#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_LSB 0x7 +#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_SIZE 0x1 +#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_NCHK_FULL_LSB 0x8 +#define GC_DMA_CTRL_CHAN5_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN5_NCHK_FULL_SIZE 0x1 +#define GC_DMA_CTRL_CHAN5_NCHK_FULL_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_NCHK_FULL_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_LSB 0x9 +#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_LSB 0xc +#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_OFFSET 0x600 +#define GC_DMA_FSM_STATE_CHAN5_IDLE_LSB 0x0 +#define GC_DMA_FSM_STATE_CHAN5_IDLE_MASK 0x1 +#define GC_DMA_FSM_STATE_CHAN5_IDLE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_IDLE_DEFAULT 0x1 +#define GC_DMA_FSM_STATE_CHAN5_IDLE_OFFSET 0x620 +#define GC_DMA_FSM_STATE_CHAN5_WAIT_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN5_WAIT_MASK 0x2 +#define GC_DMA_FSM_STATE_CHAN5_WAIT_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_WAIT_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_WAIT_OFFSET 0x620 +#define GC_DMA_FSM_STATE_CHAN5_BID_READ_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN5_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN5_BID_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_BID_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_BID_READ_OFFSET 0x620 +#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_OFFSET 0x620 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_OFFSET 0x620 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_OFFSET 0x620 +#define GC_DMA_FSM_STATE_CHAN5_READ_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN5_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN5_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_READ_OFFSET 0x620 +#define GC_DMA_FSM_STATE_CHAN5_WRITE_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN5_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN5_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_WRITE_OFFSET 0x620 +#define GC_DMA_FSM_STATE_CHAN5_ERROR_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN5_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN5_ERROR_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_ERROR_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_ERROR_OFFSET 0x620 +#define GC_DMA_CTRL_CHAN6_ENABLE_LSB 0x0 +#define GC_DMA_CTRL_CHAN6_ENABLE_MASK 0x1 +#define GC_DMA_CTRL_CHAN6_ENABLE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN6_ENABLE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_ENABLE_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_STOP_LSB 0x1 +#define GC_DMA_CTRL_CHAN6_STOP_MASK 0x2 +#define GC_DMA_CTRL_CHAN6_STOP_SIZE 0x1 +#define GC_DMA_CTRL_CHAN6_STOP_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_STOP_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_CLR_ERROR_LSB 0x2 +#define GC_DMA_CTRL_CHAN6_CLR_ERROR_MASK 0x4 +#define GC_DMA_CTRL_CHAN6_CLR_ERROR_SIZE 0x1 +#define GC_DMA_CTRL_CHAN6_CLR_ERROR_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_CLR_ERROR_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_WRAP_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN6_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN6_WRAP_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN6_WRAP_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_WRAP_MODE_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_LSB 0x5 +#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_LSB 0x6 +#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_LSB 0x7 +#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_SIZE 0x1 +#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_NCHK_FULL_LSB 0x8 +#define GC_DMA_CTRL_CHAN6_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN6_NCHK_FULL_SIZE 0x1 +#define GC_DMA_CTRL_CHAN6_NCHK_FULL_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_NCHK_FULL_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_LSB 0x9 +#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_LSB 0xc +#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_OFFSET 0x700 +#define GC_DMA_FSM_STATE_CHAN6_IDLE_LSB 0x0 +#define GC_DMA_FSM_STATE_CHAN6_IDLE_MASK 0x1 +#define GC_DMA_FSM_STATE_CHAN6_IDLE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_IDLE_DEFAULT 0x1 +#define GC_DMA_FSM_STATE_CHAN6_IDLE_OFFSET 0x720 +#define GC_DMA_FSM_STATE_CHAN6_WAIT_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN6_WAIT_MASK 0x2 +#define GC_DMA_FSM_STATE_CHAN6_WAIT_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_WAIT_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_WAIT_OFFSET 0x720 +#define GC_DMA_FSM_STATE_CHAN6_BID_READ_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN6_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN6_BID_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_BID_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_BID_READ_OFFSET 0x720 +#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_OFFSET 0x720 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_OFFSET 0x720 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_OFFSET 0x720 +#define GC_DMA_FSM_STATE_CHAN6_READ_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN6_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN6_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_READ_OFFSET 0x720 +#define GC_DMA_FSM_STATE_CHAN6_WRITE_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN6_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN6_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_WRITE_OFFSET 0x720 +#define GC_DMA_FSM_STATE_CHAN6_ERROR_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN6_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN6_ERROR_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_ERROR_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_ERROR_OFFSET 0x720 +#define GC_DMA_CTRL_CHAN7_ENABLE_LSB 0x0 +#define GC_DMA_CTRL_CHAN7_ENABLE_MASK 0x1 +#define GC_DMA_CTRL_CHAN7_ENABLE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN7_ENABLE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_ENABLE_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_STOP_LSB 0x1 +#define GC_DMA_CTRL_CHAN7_STOP_MASK 0x2 +#define GC_DMA_CTRL_CHAN7_STOP_SIZE 0x1 +#define GC_DMA_CTRL_CHAN7_STOP_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_STOP_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_CLR_ERROR_LSB 0x2 +#define GC_DMA_CTRL_CHAN7_CLR_ERROR_MASK 0x4 +#define GC_DMA_CTRL_CHAN7_CLR_ERROR_SIZE 0x1 +#define GC_DMA_CTRL_CHAN7_CLR_ERROR_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_CLR_ERROR_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_WRAP_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN7_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN7_WRAP_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN7_WRAP_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_WRAP_MODE_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_LSB 0x5 +#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_DEFAULT 0x1 +#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_LSB 0x6 +#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_SIZE 0x1 +#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_LSB 0x7 +#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_SIZE 0x1 +#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_NCHK_FULL_LSB 0x8 +#define GC_DMA_CTRL_CHAN7_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN7_NCHK_FULL_SIZE 0x1 +#define GC_DMA_CTRL_CHAN7_NCHK_FULL_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_NCHK_FULL_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_LSB 0x9 +#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_LSB 0xc +#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_SIZE 0x3 +#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_OFFSET 0x800 +#define GC_DMA_FSM_STATE_CHAN7_IDLE_LSB 0x0 +#define GC_DMA_FSM_STATE_CHAN7_IDLE_MASK 0x1 +#define GC_DMA_FSM_STATE_CHAN7_IDLE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_IDLE_DEFAULT 0x1 +#define GC_DMA_FSM_STATE_CHAN7_IDLE_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_WAIT_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN7_WAIT_MASK 0x2 +#define GC_DMA_FSM_STATE_CHAN7_WAIT_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_WAIT_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_WAIT_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_BID_READ_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN7_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN7_BID_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_BID_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_BID_READ_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_READ_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN7_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN7_READ_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_READ_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_READ_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_WRITE_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN7_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN7_WRITE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_WRITE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_WRITE_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_ERROR_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN7_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN7_ERROR_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_ERROR_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_ERROR_OFFSET 0x820 #define GC_FLASH_FSH_TRANS_OFFSET_LSB 0x0 #define GC_FLASH_FSH_TRANS_OFFSET_MASK 0xffff #define GC_FLASH_FSH_TRANS_OFFSET_SIZE 0x10 @@ -4694,6 +7379,2243 @@ #define GC_FLASH_FSH_ITOP_EDONEINT_SIZE 0x1 #define GC_FLASH_FSH_ITOP_EDONEINT_DEFAULT 0x0 #define GC_FLASH_FSH_ITOP_EDONEINT_OFFSET 0xf04 +#define GC_FUSE_STATUS_READ_DONE_LSB 0x0 +#define GC_FUSE_STATUS_READ_DONE_MASK 0x1 +#define GC_FUSE_STATUS_READ_DONE_SIZE 0x1 +#define GC_FUSE_STATUS_READ_DONE_DEFAULT 0x0 +#define GC_FUSE_STATUS_READ_DONE_OFFSET 0x0 +#define GC_FUSE_STATUS_B0_VALID_LSB 0x1 +#define GC_FUSE_STATUS_B0_VALID_MASK 0x2 +#define GC_FUSE_STATUS_B0_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_B0_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_B0_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_B1_VALID_LSB 0x2 +#define GC_FUSE_STATUS_B1_VALID_MASK 0x4 +#define GC_FUSE_STATUS_B1_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_B1_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_B1_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_B2_VALID_LSB 0x3 +#define GC_FUSE_STATUS_B2_VALID_MASK 0x8 +#define GC_FUSE_STATUS_B2_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_B2_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_B2_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_B3_VALID_LSB 0x4 +#define GC_FUSE_STATUS_B3_VALID_MASK 0x10 +#define GC_FUSE_STATUS_B3_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_B3_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_B3_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_LSB 0x5 +#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_MASK 0x20 +#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_LSB 0x6 +#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_MASK 0x40 +#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_LSB 0x7 +#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_MASK 0x80 +#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_LSB 0x8 +#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_MASK 0x100 +#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_WRITE_DONE_LSB 0x10 +#define GC_FUSE_STATUS_WRITE_DONE_MASK 0x10000 +#define GC_FUSE_STATUS_WRITE_DONE_SIZE 0x1 +#define GC_FUSE_STATUS_WRITE_DONE_DEFAULT 0x0 +#define GC_FUSE_STATUS_WRITE_DONE_OFFSET 0x0 +#define GC_FUSE_STATUS_SCRUB_BUSY_LSB 0x1c +#define GC_FUSE_STATUS_SCRUB_BUSY_MASK 0x10000000 +#define GC_FUSE_STATUS_SCRUB_BUSY_SIZE 0x1 +#define GC_FUSE_STATUS_SCRUB_BUSY_DEFAULT 0x0 +#define GC_FUSE_STATUS_SCRUB_BUSY_OFFSET 0x0 +#define GC_FUSE_STATUS_READ_BUSY_LSB 0x1d +#define GC_FUSE_STATUS_READ_BUSY_MASK 0x20000000 +#define GC_FUSE_STATUS_READ_BUSY_SIZE 0x1 +#define GC_FUSE_STATUS_READ_BUSY_DEFAULT 0x0 +#define GC_FUSE_STATUS_READ_BUSY_OFFSET 0x0 +#define GC_FUSE_STATUS_WRITE_BUSY_LSB 0x1e +#define GC_FUSE_STATUS_WRITE_BUSY_MASK 0x40000000 +#define GC_FUSE_STATUS_WRITE_BUSY_SIZE 0x1 +#define GC_FUSE_STATUS_WRITE_BUSY_DEFAULT 0x0 +#define GC_FUSE_STATUS_WRITE_BUSY_OFFSET 0x0 +#define GC_FUSE_STATUS_BUSY_LSB 0x1f +#define GC_FUSE_STATUS_BUSY_MASK 0x80000000 +#define GC_FUSE_STATUS_BUSY_SIZE 0x1 +#define GC_FUSE_STATUS_BUSY_DEFAULT 0x0 +#define GC_FUSE_STATUS_BUSY_OFFSET 0x0 +#define GC_FUSE_STATUS_CLR_CLR_DONE_LSB 0x0 +#define GC_FUSE_STATUS_CLR_CLR_DONE_MASK 0x1 +#define GC_FUSE_STATUS_CLR_CLR_DONE_SIZE 0x1 +#define GC_FUSE_STATUS_CLR_CLR_DONE_DEFAULT 0x0 +#define GC_FUSE_STATUS_CLR_CLR_DONE_OFFSET 0x4 +#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_LSB 0x0 +#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_MASK 0xffffff +#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_SIZE 0x18 +#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_DEFAULT 0xffff +#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_OFFSET 0x14 +#define GC_FUSE_SCRUB_CTRL_DISABLE_LSB 0x1c +#define GC_FUSE_SCRUB_CTRL_DISABLE_MASK 0xf0000000 +#define GC_FUSE_SCRUB_CTRL_DISABLE_SIZE 0x4 +#define GC_FUSE_SCRUB_CTRL_DISABLE_DEFAULT 0x0 +#define GC_FUSE_SCRUB_CTRL_DISABLE_OFFSET 0x14 +#define GC_FUSE_SCRUB_CTRL_DISABLE_ENABLE 0x0 +#define GC_FUSE_SCRUB_CTRL_DISABLE_DISABLE 0x0 +#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_LSB 0x0 +#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_MASK 0x1 +#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_SIZE 0x1 +#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_DEFAULT 0x0 +#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_OFFSET 0x18 +#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_LSB 0x1 +#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_MASK 0x2 +#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_SIZE 0x1 +#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_DEFAULT 0x0 +#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_OFFSET 0x18 +#define GC_FUSE_VERSION_CHANGE_LSB 0x0 +#define GC_FUSE_VERSION_CHANGE_MASK 0xffffff +#define GC_FUSE_VERSION_CHANGE_SIZE 0x18 +#define GC_FUSE_VERSION_CHANGE_DEFAULT 0x10240 +#define GC_FUSE_VERSION_CHANGE_OFFSET 0x20 +#define GC_FUSE_VERSION_REVISION_LSB 0x18 +#define GC_FUSE_VERSION_REVISION_MASK 0xff000000 +#define GC_FUSE_VERSION_REVISION_SIZE 0x8 +#define GC_FUSE_VERSION_REVISION_DEFAULT 0x3 +#define GC_FUSE_VERSION_REVISION_OFFSET 0x20 +#define GC_FUSE_INT_ENABLE_READ_FINISHED_LSB 0x0 +#define GC_FUSE_INT_ENABLE_READ_FINISHED_MASK 0x1 +#define GC_FUSE_INT_ENABLE_READ_FINISHED_SIZE 0x1 +#define GC_FUSE_INT_ENABLE_READ_FINISHED_DEFAULT 0x0 +#define GC_FUSE_INT_ENABLE_READ_FINISHED_OFFSET 0x24 +#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_LSB 0x1 +#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_MASK 0x2 +#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_SIZE 0x1 +#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_DEFAULT 0x0 +#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_OFFSET 0x24 +#define GC_FUSE_INT_STATE_READ_FINISHED_LSB 0x0 +#define GC_FUSE_INT_STATE_READ_FINISHED_MASK 0x1 +#define GC_FUSE_INT_STATE_READ_FINISHED_SIZE 0x1 +#define GC_FUSE_INT_STATE_READ_FINISHED_DEFAULT 0x0 +#define GC_FUSE_INT_STATE_READ_FINISHED_OFFSET 0x28 +#define GC_FUSE_INT_STATE_WRITE_FINISHED_LSB 0x1 +#define GC_FUSE_INT_STATE_WRITE_FINISHED_MASK 0x2 +#define GC_FUSE_INT_STATE_WRITE_FINISHED_SIZE 0x1 +#define GC_FUSE_INT_STATE_WRITE_FINISHED_DEFAULT 0x0 +#define GC_FUSE_INT_STATE_WRITE_FINISHED_OFFSET 0x28 +#define GC_FUSE_INT_TEST_READ_FINISHED_LSB 0x0 +#define GC_FUSE_INT_TEST_READ_FINISHED_MASK 0x1 +#define GC_FUSE_INT_TEST_READ_FINISHED_SIZE 0x1 +#define GC_FUSE_INT_TEST_READ_FINISHED_DEFAULT 0x0 +#define GC_FUSE_INT_TEST_READ_FINISHED_OFFSET 0x2c +#define GC_FUSE_INT_TEST_WRITE_FINISHED_LSB 0x1 +#define GC_FUSE_INT_TEST_WRITE_FINISHED_MASK 0x2 +#define GC_FUSE_INT_TEST_WRITE_FINISHED_SIZE 0x1 +#define GC_FUSE_INT_TEST_WRITE_FINISHED_DEFAULT 0x0 +#define GC_FUSE_INT_TEST_WRITE_FINISHED_OFFSET 0x2c +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_OFFSET 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_OFFSET 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_OFFSET 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_OFFSET 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_OFFSET 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_OFFSET 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_LOCK_LSB 0xc +#define GC_GLOBALSEC_ROM0_REGION0_LOCK_MASK 0x1000 +#define GC_GLOBALSEC_ROM0_REGION0_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_ROM0_REGION0_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_LOCK_OFFSET 0x0 +#define GC_GLOBALSEC_ROM0_REGION0_EN_LSB 0xd +#define GC_GLOBALSEC_ROM0_REGION0_EN_MASK 0x2000 +#define GC_GLOBALSEC_ROM0_REGION0_EN_SIZE 0x1 +#define GC_GLOBALSEC_ROM0_REGION0_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_ROM0_REGION0_EN_OFFSET 0x0 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_OFFSET 0x4 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_OFFSET 0x4 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_OFFSET 0x4 +#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_OFFSET 0x4 +#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_OFFSET 0x4 +#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_OFFSET 0x4 +#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_LSB 0xc +#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_MASK 0x1000 +#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_OFFSET 0x4 +#define GC_GLOBALSEC_SRAM0_REGION0_EN_LSB 0xd +#define GC_GLOBALSEC_SRAM0_REGION0_EN_MASK 0x2000 +#define GC_GLOBALSEC_SRAM0_REGION0_EN_SIZE 0x1 +#define GC_GLOBALSEC_SRAM0_REGION0_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_SRAM0_REGION0_EN_OFFSET 0x4 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_OFFSET 0x8 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_OFFSET 0x8 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_OFFSET 0x8 +#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_OFFSET 0x8 +#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_OFFSET 0x8 +#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_OFFSET 0x8 +#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_LSB 0xc +#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_MASK 0x1000 +#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_OFFSET 0x8 +#define GC_GLOBALSEC_SRAM0_REGION1_EN_LSB 0xd +#define GC_GLOBALSEC_SRAM0_REGION1_EN_MASK 0x2000 +#define GC_GLOBALSEC_SRAM0_REGION1_EN_SIZE 0x1 +#define GC_GLOBALSEC_SRAM0_REGION1_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_SRAM0_REGION1_EN_OFFSET 0x8 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_OFFSET 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_OFFSET 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_OFFSET 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_OFFSET 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_OFFSET 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_OFFSET 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_LSB 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_MASK 0x1000 +#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_OFFSET 0xc +#define GC_GLOBALSEC_SRAM1_REGION0_EN_LSB 0xd +#define GC_GLOBALSEC_SRAM1_REGION0_EN_MASK 0x2000 +#define GC_GLOBALSEC_SRAM1_REGION0_EN_SIZE 0x1 +#define GC_GLOBALSEC_SRAM1_REGION0_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_SRAM1_REGION0_EN_OFFSET 0xc +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_OFFSET 0x10 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_OFFSET 0x10 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_OFFSET 0x10 +#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_OFFSET 0x10 +#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_OFFSET 0x10 +#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_OFFSET 0x10 +#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_LSB 0xc +#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_MASK 0x1000 +#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_OFFSET 0x10 +#define GC_GLOBALSEC_SRAM1_REGION1_EN_LSB 0xd +#define GC_GLOBALSEC_SRAM1_REGION1_EN_MASK 0x2000 +#define GC_GLOBALSEC_SRAM1_REGION1_EN_SIZE 0x1 +#define GC_GLOBALSEC_SRAM1_REGION1_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_SRAM1_REGION1_EN_OFFSET 0x10 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION0_FSH_CTRL_CTRL_LSB 0xc +#define GC_GLOBALSEC_FLASH0_REGION0_FSH_CTRL_CTRL_MASK 0x3000 +#define GC_GLOBALSEC_FLASH0_REGION0_FSH_CTRL_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_FSH_CTRL_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION0_FSH_CTRL_CTRL_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_LSB 0xe +#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_MASK 0x4000 +#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION0_EN_LSB 0xf +#define GC_GLOBALSEC_FLASH0_REGION0_EN_MASK 0x8000 +#define GC_GLOBALSEC_FLASH0_REGION0_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION0_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_FLASH0_REGION0_EN_OFFSET 0x14 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION1_FSH_CTRL_CTRL_LSB 0xc +#define GC_GLOBALSEC_FLASH0_REGION1_FSH_CTRL_CTRL_MASK 0x3000 +#define GC_GLOBALSEC_FLASH0_REGION1_FSH_CTRL_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_FSH_CTRL_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION1_FSH_CTRL_CTRL_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_LSB 0xe +#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_MASK 0x4000 +#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION1_EN_LSB 0xf +#define GC_GLOBALSEC_FLASH0_REGION1_EN_MASK 0x8000 +#define GC_GLOBALSEC_FLASH0_REGION1_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION1_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_FLASH0_REGION1_EN_OFFSET 0x18 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION2_FSH_CTRL_CTRL_LSB 0xc +#define GC_GLOBALSEC_FLASH0_REGION2_FSH_CTRL_CTRL_MASK 0x3000 +#define GC_GLOBALSEC_FLASH0_REGION2_FSH_CTRL_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_FSH_CTRL_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION2_FSH_CTRL_CTRL_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_LSB 0xe +#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_MASK 0x4000 +#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION2_EN_LSB 0xf +#define GC_GLOBALSEC_FLASH0_REGION2_EN_MASK 0x8000 +#define GC_GLOBALSEC_FLASH0_REGION2_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION2_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_FLASH0_REGION2_EN_OFFSET 0x1c +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH0_REGION3_FSH_CTRL_CTRL_LSB 0xc +#define GC_GLOBALSEC_FLASH0_REGION3_FSH_CTRL_CTRL_MASK 0x3000 +#define GC_GLOBALSEC_FLASH0_REGION3_FSH_CTRL_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_FSH_CTRL_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH0_REGION3_FSH_CTRL_CTRL_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_LSB 0xe +#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_MASK 0x4000 +#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH0_REGION3_EN_LSB 0xf +#define GC_GLOBALSEC_FLASH0_REGION3_EN_MASK 0x8000 +#define GC_GLOBALSEC_FLASH0_REGION3_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION3_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_FLASH0_REGION3_EN_OFFSET 0x20 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION0_FSH_CTRL_CTRL_LSB 0xc +#define GC_GLOBALSEC_FLASH1_REGION0_FSH_CTRL_CTRL_MASK 0x3000 +#define GC_GLOBALSEC_FLASH1_REGION0_FSH_CTRL_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_FSH_CTRL_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION0_FSH_CTRL_CTRL_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_LSB 0xe +#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_MASK 0x4000 +#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION0_EN_LSB 0xf +#define GC_GLOBALSEC_FLASH1_REGION0_EN_MASK 0x8000 +#define GC_GLOBALSEC_FLASH1_REGION0_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION0_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_FLASH1_REGION0_EN_OFFSET 0x24 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION1_FSH_CTRL_CTRL_LSB 0xc +#define GC_GLOBALSEC_FLASH1_REGION1_FSH_CTRL_CTRL_MASK 0x3000 +#define GC_GLOBALSEC_FLASH1_REGION1_FSH_CTRL_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_FSH_CTRL_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION1_FSH_CTRL_CTRL_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_LSB 0xe +#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_MASK 0x4000 +#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION1_EN_LSB 0xf +#define GC_GLOBALSEC_FLASH1_REGION1_EN_MASK 0x8000 +#define GC_GLOBALSEC_FLASH1_REGION1_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION1_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_FLASH1_REGION1_EN_OFFSET 0x28 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION2_FSH_CTRL_CTRL_LSB 0xc +#define GC_GLOBALSEC_FLASH1_REGION2_FSH_CTRL_CTRL_MASK 0x3000 +#define GC_GLOBALSEC_FLASH1_REGION2_FSH_CTRL_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_FSH_CTRL_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION2_FSH_CTRL_CTRL_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_LSB 0xe +#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_MASK 0x4000 +#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION2_EN_LSB 0xf +#define GC_GLOBALSEC_FLASH1_REGION2_EN_MASK 0x8000 +#define GC_GLOBALSEC_FLASH1_REGION2_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION2_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_FLASH1_REGION2_EN_OFFSET 0x2c +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_LSB 0x0 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_MASK 0x3 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_OFFSET 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_LSB 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_MASK 0xc +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_OFFSET 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_LSB 0x4 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_MASK 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_OFFSET 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_LSB 0x6 +#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_MASK 0xc0 +#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_OFFSET 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_LSB 0x8 +#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_MASK 0x300 +#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_OFFSET 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_LSB 0xa +#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_MASK 0xc00 +#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_OFFSET 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_FSH_CTRL_CTRL_LSB 0xc +#define GC_GLOBALSEC_FLASH1_REGION3_FSH_CTRL_CTRL_MASK 0x3000 +#define GC_GLOBALSEC_FLASH1_REGION3_FSH_CTRL_CTRL_SIZE 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_FSH_CTRL_CTRL_DEFAULT 0x3 +#define GC_GLOBALSEC_FLASH1_REGION3_FSH_CTRL_CTRL_OFFSET 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_LSB 0xe +#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_MASK 0x4000 +#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_OFFSET 0x30 +#define GC_GLOBALSEC_FLASH1_REGION3_EN_LSB 0xf +#define GC_GLOBALSEC_FLASH1_REGION3_EN_MASK 0x8000 +#define GC_GLOBALSEC_FLASH1_REGION3_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION3_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_FLASH1_REGION3_EN_OFFSET 0x30 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_LSB 0x0 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_MASK 0x1 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_SIZE 0x1 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_OFFSET 0x1000 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG2_FW_SIG_MATCH_LSB 0x1 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG2_FW_SIG_MATCH_MASK 0x2 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG2_FW_SIG_MATCH_SIZE 0x1 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG2_FW_SIG_MATCH_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG2_FW_SIG_MATCH_OFFSET 0x1000 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG3_FW_SIG_MATCH_LSB 0x2 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG3_FW_SIG_MATCH_MASK 0x4 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG3_FW_SIG_MATCH_SIZE 0x1 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG3_FW_SIG_MATCH_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_COMP_STATUS_SB_STG3_FW_SIG_MATCH_OFFSET 0x1000 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_NUM_LSB 0x0 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_NUM_MASK 0x7 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_NUM_SIZE 0x3 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_NUM_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_NUM_OFFSET 0x1004 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_EN_LSB 0x7 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_EN_MASK 0x80 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_EN_SIZE 0x1 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG2_FW_MMU_EN_OFFSET 0x1004 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_NUM_LSB 0x8 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_NUM_MASK 0x700 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_NUM_SIZE 0x3 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_NUM_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_NUM_OFFSET 0x1004 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_EN_LSB 0xf +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_EN_MASK 0x8000 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_EN_SIZE 0x1 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_SB_COMP_CONTROL_SB_STG3_FW_MMU_EN_OFFSET 0x1004 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_GEN_LSB 0x0 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_GEN_MASK 0x3f +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_GEN_SIZE 0x6 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_GEN_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_GEN_OFFSET 0x3320 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_ID_LSB 0x8 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_ID_MASK 0x3f00 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_ID_SIZE 0x6 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_ID_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_ID_OFFSET 0x3320 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_VLD_LSB 0x1e +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_VLD_MASK 0xc0000000 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_VLD_SIZE 0x2 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_VLD_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FRR_MTD_FRR_VLD_OFFSET 0x3320 +#define GC_GLOBALSEC_HKEY_FLSH_FW_MTD_FWR_VLD_LSB 0x0 +#define GC_GLOBALSEC_HKEY_FLSH_FW_MTD_FWR_VLD_MASK 0x3 +#define GC_GLOBALSEC_HKEY_FLSH_FW_MTD_FWR_VLD_SIZE 0x2 +#define GC_GLOBALSEC_HKEY_FLSH_FW_MTD_FWR_VLD_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_FLSH_FW_MTD_FWR_VLD_OFFSET 0x3324 +#define GC_GLOBALSEC_HKEY_ROM_FW_MTD_RWR_VLD_LSB 0x0 +#define GC_GLOBALSEC_HKEY_ROM_FW_MTD_RWR_VLD_MASK 0x3 +#define GC_GLOBALSEC_HKEY_ROM_FW_MTD_RWR_VLD_SIZE 0x2 +#define GC_GLOBALSEC_HKEY_ROM_FW_MTD_RWR_VLD_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ROM_FW_MTD_RWR_VLD_OFFSET 0x3328 +#define GC_GLOBALSEC_HKEY_HKYSQ_MTD_HWR_VLD_LSB 0x0 +#define GC_GLOBALSEC_HKEY_HKYSQ_MTD_HWR_VLD_MASK 0x3 +#define GC_GLOBALSEC_HKEY_HKYSQ_MTD_HWR_VLD_SIZE 0x2 +#define GC_GLOBALSEC_HKEY_HKYSQ_MTD_HWR_VLD_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_HKYSQ_MTD_HWR_VLD_OFFSET 0x332c +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_INVLD_SLOT_LSB 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_INVLD_SLOT_MASK 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_INVLD_SLOT_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_INVLD_SLOT_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_INVLD_SLOT_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_GEN_TO_LOW_LSB 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_GEN_TO_LOW_MASK 0x2 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_GEN_TO_LOW_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_GEN_TO_LOW_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_GEN_TO_LOW_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_WRNG_ID_LSB 0x2 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_WRNG_ID_MASK 0x4 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_WRNG_ID_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_WRNG_ID_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_RD_WRNG_ID_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ADDR_ERR_LSB 0x3 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ADDR_ERR_MASK 0x8 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ADDR_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ADDR_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ADDR_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_AES_ACCESS_ERR_LSB 0x4 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_AES_ACCESS_ERR_MASK 0x10 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_AES_ACCESS_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_AES_ACCESS_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_AES_ACCESS_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_UNLCK_ATMPT_ERR_LSB 0x5 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_UNLCK_ATMPT_ERR_MASK 0x20 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_UNLCK_ATMPT_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_UNLCK_ATMPT_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_UNLCK_ATMPT_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ZEROS_DW_ERR_LSB 0x6 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ZEROS_DW_ERR_MASK 0x40 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ZEROS_DW_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ZEROS_DW_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ZEROS_DW_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ONES_DW_ERR_LSB 0x7 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ONES_DW_ERR_MASK 0x80 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ONES_DW_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ONES_DW_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_PW_ONES_DW_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_STRNG_ERR_LSB 0x8 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_STRNG_ERR_MASK 0x100 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_STRNG_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_STRNG_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_STRNG_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_STRNG_ERR_LSB 0x9 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_STRNG_ERR_MASK 0x200 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_STRNG_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_STRNG_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_STRNG_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_DW_ERR_LSB 0xa +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_DW_ERR_MASK 0x400 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_DW_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_DW_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ZEROS_DW_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_DW_ERR_LSB 0xb +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_DW_ERR_MASK 0x800 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_DW_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_DW_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_SLOT_ONES_DW_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_FAIL_LSB 0x10 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_FAIL_MASK 0x10000 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_FAIL_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_FAIL_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_FAIL_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_ERR_LSB 0x11 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_ERR_MASK 0x20000 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_KEY_REGEN_CMP_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_DEV_ST_DEC_ERR_LSB 0x18 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_DEV_ST_DEC_ERR_MASK 0x1000000 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_DEV_ST_DEC_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_DEV_ST_DEC_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_DEV_ST_DEC_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_RSR_SHDW_ERR_LSB 0x1e +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_RSR_SHDW_ERR_MASK 0x40000000 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_RSR_SHDW_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_RSR_SHDW_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_RSR_SHDW_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_FBS_SHDW_ERR_LSB 0x1f +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_FBS_SHDW_ERR_MASK 0x80000000 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_FBS_SHDW_ERR_SIZE 0x1 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_FBS_SHDW_ERR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_FLAGS_FLASH_FBS_SHDW_ERR_OFFSET 0x3330 +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_BUS_ERR_ADR_LSB 0x0 +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_BUS_ERR_ADR_MASK 0x3ff +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_BUS_ERR_ADR_SIZE 0xa +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_BUS_ERR_ADR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_BUS_ERR_ADR_OFFSET 0x3334 +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_ZEROS_ONES_ERR_ADR_LSB 0x10 +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_ZEROS_ONES_ERR_ADR_MASK 0x3ff0000 +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_ZEROS_ONES_ERR_ADR_SIZE 0xa +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_ZEROS_ONES_ERR_ADR_DEFAULT 0x0 +#define GC_GLOBALSEC_HKEY_ERR_ADDRS_HKEY_ZEROS_ONES_ERR_ADR_OFFSET 0x3334 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_HKEY_CTR_MAX_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_HKEY_CTR_MAX_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_HKEY_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_HKEY_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_HKEY_CTR_MAX_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_STD_CTR_MAX_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_STD_CTR_MAX_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_STD_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_STD_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_AES0_EXEC_STD_CTR_MAX_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x80 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x200 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x800 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xd +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x2000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xf +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x8000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MIN_TEMP_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MIN_TEMP_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_TIMEOUT_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_TIMEOUT_ALERT_MASK 0x20000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_TIMEOUT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_TRNG0_TIMEOUT_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_VOLT0_VOLT_ERR_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_INTR_STS0_VOLT0_VOLT_ERR_ALERT_MASK 0x40000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_INTR_STS0_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x80 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x200 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x800 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xd +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x2000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xf +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x8000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MIN_TEMP_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MIN_TEMP_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_TIMEOUT_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_TIMEOUT_ALERT_MASK 0x20000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_TIMEOUT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_TRNG0_TIMEOUT_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_VOLT0_VOLT_ERR_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_NMI_EN0_VOLT0_VOLT_ERR_ALERT_MASK 0x40000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_NMI_EN0_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_NMI_EN0_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x80 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x200 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x800 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xd +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x2000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xf +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x8000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MIN_TEMP_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MIN_TEMP_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MIN_TEMP_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_TIMEOUT_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_TIMEOUT_ALERT_MASK 0x20000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_TIMEOUT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TRNG0_TIMEOUT_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_VOLT0_VOLT_ERR_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_VOLT0_VOLT_ERR_ALERT_MASK 0x40000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_VOLT0_VOLT_ERR_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x80 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x200 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x800 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xd +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x2000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xf +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x8000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MIN_TEMP_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MIN_TEMP_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_TIMEOUT_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_TIMEOUT_ALERT_MASK 0x20000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_TIMEOUT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TRNG0_TIMEOUT_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_VOLT0_VOLT_ERR_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_VOLT0_VOLT_ERR_ALERT_MASK 0x40000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x80 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x200 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x800 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xd +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x2000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xf +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x8000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MIN_TEMP_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MIN_TEMP_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_TIMEOUT_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_TIMEOUT_ALERT_MASK 0x20000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_TIMEOUT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TRNG0_TIMEOUT_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_VOLT0_VOLT_ERR_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_VOLT0_VOLT_ERR_ALERT_MASK 0x40000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x80 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x200 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x800 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xd +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x2000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xf +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x8000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MIN_TEMP_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MIN_TEMP_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_TIMEOUT_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_TIMEOUT_ALERT_MASK 0x20000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_TIMEOUT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TRNG0_TIMEOUT_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_VOLT0_VOLT_ERR_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_VOLT0_VOLT_ERR_ALERT_MASK 0x40000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x80 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x200 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x800 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xd +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x2000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xf +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x8000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MIN_TEMP_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MIN_TEMP_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MIN_TEMP_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_TIMEOUT_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_TIMEOUT_ALERT_MASK 0x20000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_TIMEOUT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TRNG0_TIMEOUT_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_VOLT0_VOLT_ERR_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_VOLT0_VOLT_ERR_ALERT_MASK 0x40000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_VOLT0_VOLT_ERR_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_HKEY_CTR_MAX_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_AES0_EXEC_STD_CTR_MAX_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x80 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x200 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x800 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xd +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x2000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xf +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x8000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MIN_TEMP_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MIN_TEMP_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_TIMEOUT_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_TIMEOUT_ALERT_MASK 0x20000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_TIMEOUT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TRNG0_TIMEOUT_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_VOLT0_VOLT_ERR_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_VOLT0_VOLT_ERR_ALERT_MASK 0x40000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_LSB 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_MASK 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_LSB 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_MASK 0x2 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_LSB 0x2 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_MASK 0x4 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_LSB 0x3 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_MASK 0x8 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_LSB 0x4 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_MASK 0x10 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_LSB 0x5 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_MASK 0x20 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_LSB 0x6 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_MASK 0x40 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_LSB 0x7 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_MASK 0x80 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_LSB 0x8 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_MASK 0x100 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_LSB 0x9 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_MASK 0x200 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_LSB 0xa +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_MASK 0x400 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_LSB 0xb +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_MASK 0x800 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_LSB 0xc +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_MASK 0x1000 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_LSB 0xd +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_MASK 0x2000 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_LSB 0xe +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_MASK 0x4000 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_LSB 0xf +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_MASK 0x8000 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_LSB 0x10 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_MASK 0x10000 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_LSB 0x11 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_OFFSET 0x403c +#define GC_GLOBALSEC_VERSION_CHANGE_LSB 0x0 +#define GC_GLOBALSEC_VERSION_CHANGE_MASK 0xffffff +#define GC_GLOBALSEC_VERSION_CHANGE_SIZE 0x18 +#define GC_GLOBALSEC_VERSION_CHANGE_DEFAULT 0x105e2 +#define GC_GLOBALSEC_VERSION_CHANGE_OFFSET 0x4070 +#define GC_GLOBALSEC_VERSION_REVISION_LSB 0x18 +#define GC_GLOBALSEC_VERSION_REVISION_MASK 0xff000000 +#define GC_GLOBALSEC_VERSION_REVISION_SIZE 0x8 +#define GC_GLOBALSEC_VERSION_REVISION_DEFAULT 0x10 +#define GC_GLOBALSEC_VERSION_REVISION_OFFSET 0x4070 #define GC_I2C_CTRL_PHASESTEPS_P0_LSB 0x0 #define GC_I2C_CTRL_PHASESTEPS_P0_MASK 0x3f #define GC_I2C_CTRL_PHASESTEPS_P0_SIZE 0x6 @@ -5307,12 +10229,12 @@ #define GC_I2CS_VERSION_CHANGE_LSB 0x0 #define GC_I2CS_VERSION_CHANGE_MASK 0xffffff #define GC_I2CS_VERSION_CHANGE_SIZE 0x18 -#define GC_I2CS_VERSION_CHANGE_DEFAULT 0xb99f +#define GC_I2CS_VERSION_CHANGE_DEFAULT 0xf6a0 #define GC_I2CS_VERSION_CHANGE_OFFSET 0x0 #define GC_I2CS_VERSION_REVISION_LSB 0x18 #define GC_I2CS_VERSION_REVISION_MASK 0xff000000 #define GC_I2CS_VERSION_REVISION_SIZE 0x8 -#define GC_I2CS_VERSION_REVISION_DEFAULT 0x4 +#define GC_I2CS_VERSION_REVISION_DEFAULT 0x6 #define GC_I2CS_VERSION_REVISION_OFFSET 0x0 #define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_LSB 0x0 #define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_MASK 0x1 @@ -5393,22 +10315,22 @@ #define GC_I2CS_READVAL_SDA_MASK 0x1 #define GC_I2CS_READVAL_SDA_SIZE 0x1 #define GC_I2CS_READVAL_SDA_DEFAULT 0x0 -#define GC_I2CS_READVAL_SDA_OFFSET 0x20 +#define GC_I2CS_READVAL_SDA_OFFSET 0x2c #define GC_I2CS_READVAL_SCL_LSB 0x1 #define GC_I2CS_READVAL_SCL_MASK 0x2 #define GC_I2CS_READVAL_SCL_SIZE 0x1 #define GC_I2CS_READVAL_SCL_DEFAULT 0x0 -#define GC_I2CS_READVAL_SCL_OFFSET 0x20 +#define GC_I2CS_READVAL_SCL_OFFSET 0x2c #define GC_I2CS_CTRL_MSR_SDA_LSB 0x0 #define GC_I2CS_CTRL_MSR_SDA_MASK 0x3 #define GC_I2CS_CTRL_MSR_SDA_SIZE 0x2 #define GC_I2CS_CTRL_MSR_SDA_DEFAULT 0x2 -#define GC_I2CS_CTRL_MSR_SDA_OFFSET 0x24 +#define GC_I2CS_CTRL_MSR_SDA_OFFSET 0x30 #define GC_I2CS_CTRL_MSR_SCL_LSB 0x2 #define GC_I2CS_CTRL_MSR_SCL_MASK 0xc #define GC_I2CS_CTRL_MSR_SCL_SIZE 0x2 #define GC_I2CS_CTRL_MSR_SCL_DEFAULT 0x2 -#define GC_I2CS_CTRL_MSR_SCL_OFFSET 0x24 +#define GC_I2CS_CTRL_MSR_SCL_OFFSET 0x30 #define GC_MAU_EN_SYSIBUS_LSB 0x0 #define GC_MAU_EN_SYSIBUS_MASK 0x1 #define GC_MAU_EN_SYSIBUS_SIZE 0x1 @@ -5439,21 +10361,6 @@ #define GC_MAU_TRACEIDX_SYSDBUS_SIZE 0x1 #define GC_MAU_TRACEIDX_SYSDBUS_DEFAULT 0x1 #define GC_MAU_TRACEIDX_SYSDBUS_OFFSET 0x8 -#define GC_PAU_EN_SYSSBUS_LSB 0x0 -#define GC_PAU_EN_SYSSBUS_MASK 0x1 -#define GC_PAU_EN_SYSSBUS_SIZE 0x1 -#define GC_PAU_EN_SYSSBUS_DEFAULT 0x1 -#define GC_PAU_EN_SYSSBUS_OFFSET 0x0 -#define GC_PAU_TRACECLR_SYSSBUS_LSB 0x0 -#define GC_PAU_TRACECLR_SYSSBUS_MASK 0x1 -#define GC_PAU_TRACECLR_SYSSBUS_SIZE 0x1 -#define GC_PAU_TRACECLR_SYSSBUS_DEFAULT 0x1 -#define GC_PAU_TRACECLR_SYSSBUS_OFFSET 0x4 -#define GC_PAU_TRACEIDX_SYSSBUS_LSB 0x0 -#define GC_PAU_TRACEIDX_SYSSBUS_MASK 0x1 -#define GC_PAU_TRACEIDX_SYSSBUS_SIZE 0x1 -#define GC_PAU_TRACEIDX_SYSSBUS_DEFAULT 0x1 -#define GC_PAU_TRACEIDX_SYSSBUS_OFFSET 0x8 #define GC_PINMUX_DIOM0_CTL_DS_LSB 0x0 #define GC_PINMUX_DIOM0_CTL_DS_MASK 0x3 #define GC_PINMUX_DIOM0_CTL_DS_SIZE 0x2 @@ -6154,1181 +11061,811 @@ #define GC_PINMUX_DIOB7_CTL_INV_SIZE 0x1 #define GC_PINMUX_DIOB7_CTL_INV_DEFAULT 0x0 #define GC_PINMUX_DIOB7_CTL_INV_OFFSET 0xdc -#define GC_PINMUX_DIOB8_CTL_DS_LSB 0x0 -#define GC_PINMUX_DIOB8_CTL_DS_MASK 0x3 -#define GC_PINMUX_DIOB8_CTL_DS_SIZE 0x2 -#define GC_PINMUX_DIOB8_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_DIOB8_CTL_DS_OFFSET 0xe4 -#define GC_PINMUX_DIOB8_CTL_IE_LSB 0x2 -#define GC_PINMUX_DIOB8_CTL_IE_MASK 0x4 -#define GC_PINMUX_DIOB8_CTL_IE_SIZE 0x1 -#define GC_PINMUX_DIOB8_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_DIOB8_CTL_IE_OFFSET 0xe4 -#define GC_PINMUX_DIOB8_CTL_PD_LSB 0x3 -#define GC_PINMUX_DIOB8_CTL_PD_MASK 0x8 -#define GC_PINMUX_DIOB8_CTL_PD_SIZE 0x1 -#define GC_PINMUX_DIOB8_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_DIOB8_CTL_PD_OFFSET 0xe4 -#define GC_PINMUX_DIOB8_CTL_PU_LSB 0x4 -#define GC_PINMUX_DIOB8_CTL_PU_MASK 0x10 -#define GC_PINMUX_DIOB8_CTL_PU_SIZE 0x1 -#define GC_PINMUX_DIOB8_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_DIOB8_CTL_PU_OFFSET 0xe4 -#define GC_PINMUX_DIOB8_CTL_INV_LSB 0x5 -#define GC_PINMUX_DIOB8_CTL_INV_MASK 0x20 -#define GC_PINMUX_DIOB8_CTL_INV_SIZE 0x1 -#define GC_PINMUX_DIOB8_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_DIOB8_CTL_INV_OFFSET 0xe4 -#define GC_PINMUX_RTCXOP_CTL_DS_LSB 0x0 -#define GC_PINMUX_RTCXOP_CTL_DS_MASK 0x3 -#define GC_PINMUX_RTCXOP_CTL_DS_SIZE 0x2 -#define GC_PINMUX_RTCXOP_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_RTCXOP_CTL_DS_OFFSET 0xec -#define GC_PINMUX_RTCXOP_CTL_IE_LSB 0x2 -#define GC_PINMUX_RTCXOP_CTL_IE_MASK 0x4 -#define GC_PINMUX_RTCXOP_CTL_IE_SIZE 0x1 -#define GC_PINMUX_RTCXOP_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_RTCXOP_CTL_IE_OFFSET 0xec -#define GC_PINMUX_RTCXOP_CTL_PD_LSB 0x3 -#define GC_PINMUX_RTCXOP_CTL_PD_MASK 0x8 -#define GC_PINMUX_RTCXOP_CTL_PD_SIZE 0x1 -#define GC_PINMUX_RTCXOP_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_RTCXOP_CTL_PD_OFFSET 0xec -#define GC_PINMUX_RTCXOP_CTL_PU_LSB 0x4 -#define GC_PINMUX_RTCXOP_CTL_PU_MASK 0x10 -#define GC_PINMUX_RTCXOP_CTL_PU_SIZE 0x1 -#define GC_PINMUX_RTCXOP_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_RTCXOP_CTL_PU_OFFSET 0xec -#define GC_PINMUX_RTCXOP_CTL_INV_LSB 0x5 -#define GC_PINMUX_RTCXOP_CTL_INV_MASK 0x20 -#define GC_PINMUX_RTCXOP_CTL_INV_SIZE 0x1 -#define GC_PINMUX_RTCXOP_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_RTCXOP_CTL_INV_OFFSET 0xec #define GC_PINMUX_SWDPTRACE_CTL_DS_LSB 0x0 #define GC_PINMUX_SWDPTRACE_CTL_DS_MASK 0x3 #define GC_PINMUX_SWDPTRACE_CTL_DS_SIZE 0x2 #define GC_PINMUX_SWDPTRACE_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_SWDPTRACE_CTL_DS_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_DS_OFFSET 0xe4 #define GC_PINMUX_SWDPTRACE_CTL_IE_LSB 0x2 #define GC_PINMUX_SWDPTRACE_CTL_IE_MASK 0x4 #define GC_PINMUX_SWDPTRACE_CTL_IE_SIZE 0x1 #define GC_PINMUX_SWDPTRACE_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_SWDPTRACE_CTL_IE_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_IE_OFFSET 0xe4 #define GC_PINMUX_SWDPTRACE_CTL_PD_LSB 0x3 #define GC_PINMUX_SWDPTRACE_CTL_PD_MASK 0x8 #define GC_PINMUX_SWDPTRACE_CTL_PD_SIZE 0x1 #define GC_PINMUX_SWDPTRACE_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_SWDPTRACE_CTL_PD_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_PD_OFFSET 0xe4 #define GC_PINMUX_SWDPTRACE_CTL_PU_LSB 0x4 #define GC_PINMUX_SWDPTRACE_CTL_PU_MASK 0x10 #define GC_PINMUX_SWDPTRACE_CTL_PU_SIZE 0x1 #define GC_PINMUX_SWDPTRACE_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_SWDPTRACE_CTL_PU_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_PU_OFFSET 0xe4 #define GC_PINMUX_SWDPTRACE_CTL_INV_LSB 0x5 #define GC_PINMUX_SWDPTRACE_CTL_INV_MASK 0x20 #define GC_PINMUX_SWDPTRACE_CTL_INV_SIZE 0x1 #define GC_PINMUX_SWDPTRACE_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_SWDPTRACE_CTL_INV_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_INV_OFFSET 0xe4 #define GC_PINMUX_SWDPDATA_CTL_DS_LSB 0x0 #define GC_PINMUX_SWDPDATA_CTL_DS_MASK 0x3 #define GC_PINMUX_SWDPDATA_CTL_DS_SIZE 0x2 #define GC_PINMUX_SWDPDATA_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_SWDPDATA_CTL_DS_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_DS_OFFSET 0xec #define GC_PINMUX_SWDPDATA_CTL_IE_LSB 0x2 #define GC_PINMUX_SWDPDATA_CTL_IE_MASK 0x4 #define GC_PINMUX_SWDPDATA_CTL_IE_SIZE 0x1 #define GC_PINMUX_SWDPDATA_CTL_IE_DEFAULT 0x1 -#define GC_PINMUX_SWDPDATA_CTL_IE_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_IE_OFFSET 0xec #define GC_PINMUX_SWDPDATA_CTL_PD_LSB 0x3 #define GC_PINMUX_SWDPDATA_CTL_PD_MASK 0x8 #define GC_PINMUX_SWDPDATA_CTL_PD_SIZE 0x1 #define GC_PINMUX_SWDPDATA_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_SWDPDATA_CTL_PD_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_PD_OFFSET 0xec #define GC_PINMUX_SWDPDATA_CTL_PU_LSB 0x4 #define GC_PINMUX_SWDPDATA_CTL_PU_MASK 0x10 #define GC_PINMUX_SWDPDATA_CTL_PU_SIZE 0x1 #define GC_PINMUX_SWDPDATA_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_SWDPDATA_CTL_PU_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_PU_OFFSET 0xec #define GC_PINMUX_SWDPDATA_CTL_INV_LSB 0x5 #define GC_PINMUX_SWDPDATA_CTL_INV_MASK 0x20 #define GC_PINMUX_SWDPDATA_CTL_INV_SIZE 0x1 #define GC_PINMUX_SWDPDATA_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_SWDPDATA_CTL_INV_OFFSET 0xfc -#define GC_PINMUX_TESTMODE_CTL_DS_LSB 0x0 -#define GC_PINMUX_TESTMODE_CTL_DS_MASK 0x3 -#define GC_PINMUX_TESTMODE_CTL_DS_SIZE 0x2 -#define GC_PINMUX_TESTMODE_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TESTMODE_CTL_DS_OFFSET 0x104 -#define GC_PINMUX_TESTMODE_CTL_IE_LSB 0x2 -#define GC_PINMUX_TESTMODE_CTL_IE_MASK 0x4 -#define GC_PINMUX_TESTMODE_CTL_IE_SIZE 0x1 -#define GC_PINMUX_TESTMODE_CTL_IE_DEFAULT 0x1 -#define GC_PINMUX_TESTMODE_CTL_IE_OFFSET 0x104 -#define GC_PINMUX_TESTMODE_CTL_PD_LSB 0x3 -#define GC_PINMUX_TESTMODE_CTL_PD_MASK 0x8 -#define GC_PINMUX_TESTMODE_CTL_PD_SIZE 0x1 -#define GC_PINMUX_TESTMODE_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TESTMODE_CTL_PD_OFFSET 0x104 -#define GC_PINMUX_TESTMODE_CTL_PU_LSB 0x4 -#define GC_PINMUX_TESTMODE_CTL_PU_MASK 0x10 -#define GC_PINMUX_TESTMODE_CTL_PU_SIZE 0x1 -#define GC_PINMUX_TESTMODE_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TESTMODE_CTL_PU_OFFSET 0x104 -#define GC_PINMUX_TESTMODE_CTL_INV_LSB 0x5 -#define GC_PINMUX_TESTMODE_CTL_INV_MASK 0x20 -#define GC_PINMUX_TESTMODE_CTL_INV_SIZE 0x1 -#define GC_PINMUX_TESTMODE_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TESTMODE_CTL_INV_OFFSET 0x104 +#define GC_PINMUX_SWDPDATA_CTL_INV_OFFSET 0xec #define GC_PINMUX_RESETB_CTL_DS_LSB 0x0 #define GC_PINMUX_RESETB_CTL_DS_MASK 0x3 #define GC_PINMUX_RESETB_CTL_DS_SIZE 0x2 #define GC_PINMUX_RESETB_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_RESETB_CTL_DS_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_DS_OFFSET 0xf4 #define GC_PINMUX_RESETB_CTL_IE_LSB 0x2 #define GC_PINMUX_RESETB_CTL_IE_MASK 0x4 #define GC_PINMUX_RESETB_CTL_IE_SIZE 0x1 #define GC_PINMUX_RESETB_CTL_IE_DEFAULT 0x1 -#define GC_PINMUX_RESETB_CTL_IE_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_IE_OFFSET 0xf4 #define GC_PINMUX_RESETB_CTL_PD_LSB 0x3 #define GC_PINMUX_RESETB_CTL_PD_MASK 0x8 #define GC_PINMUX_RESETB_CTL_PD_SIZE 0x1 #define GC_PINMUX_RESETB_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_RESETB_CTL_PD_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_PD_OFFSET 0xf4 #define GC_PINMUX_RESETB_CTL_PU_LSB 0x4 #define GC_PINMUX_RESETB_CTL_PU_MASK 0x10 #define GC_PINMUX_RESETB_CTL_PU_SIZE 0x1 #define GC_PINMUX_RESETB_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_RESETB_CTL_PU_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_PU_OFFSET 0xf4 #define GC_PINMUX_RESETB_CTL_INV_LSB 0x5 #define GC_PINMUX_RESETB_CTL_INV_MASK 0x20 #define GC_PINMUX_RESETB_CTL_INV_SIZE 0x1 #define GC_PINMUX_RESETB_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_RESETB_CTL_INV_OFFSET 0x10c -#define GC_PINMUX_VIO0_CTL_DS_LSB 0x0 -#define GC_PINMUX_VIO0_CTL_DS_MASK 0x3 -#define GC_PINMUX_VIO0_CTL_DS_SIZE 0x2 -#define GC_PINMUX_VIO0_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_VIO0_CTL_DS_OFFSET 0x114 -#define GC_PINMUX_VIO0_CTL_IE_LSB 0x2 -#define GC_PINMUX_VIO0_CTL_IE_MASK 0x4 -#define GC_PINMUX_VIO0_CTL_IE_SIZE 0x1 -#define GC_PINMUX_VIO0_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_IE_OFFSET 0x114 -#define GC_PINMUX_VIO0_CTL_PD_LSB 0x3 -#define GC_PINMUX_VIO0_CTL_PD_MASK 0x8 -#define GC_PINMUX_VIO0_CTL_PD_SIZE 0x1 -#define GC_PINMUX_VIO0_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_PD_OFFSET 0x114 -#define GC_PINMUX_VIO0_CTL_PU_LSB 0x4 -#define GC_PINMUX_VIO0_CTL_PU_MASK 0x10 -#define GC_PINMUX_VIO0_CTL_PU_SIZE 0x1 -#define GC_PINMUX_VIO0_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_PU_OFFSET 0x114 -#define GC_PINMUX_VIO0_CTL_INV_LSB 0x5 -#define GC_PINMUX_VIO0_CTL_INV_MASK 0x20 -#define GC_PINMUX_VIO0_CTL_INV_SIZE 0x1 -#define GC_PINMUX_VIO0_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_INV_OFFSET 0x114 -#define GC_PINMUX_VIO1_CTL_DS_LSB 0x0 -#define GC_PINMUX_VIO1_CTL_DS_MASK 0x3 -#define GC_PINMUX_VIO1_CTL_DS_SIZE 0x2 -#define GC_PINMUX_VIO1_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_VIO1_CTL_DS_OFFSET 0x11c -#define GC_PINMUX_VIO1_CTL_IE_LSB 0x2 -#define GC_PINMUX_VIO1_CTL_IE_MASK 0x4 -#define GC_PINMUX_VIO1_CTL_IE_SIZE 0x1 -#define GC_PINMUX_VIO1_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_IE_OFFSET 0x11c -#define GC_PINMUX_VIO1_CTL_PD_LSB 0x3 -#define GC_PINMUX_VIO1_CTL_PD_MASK 0x8 -#define GC_PINMUX_VIO1_CTL_PD_SIZE 0x1 -#define GC_PINMUX_VIO1_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_PD_OFFSET 0x11c -#define GC_PINMUX_VIO1_CTL_PU_LSB 0x4 -#define GC_PINMUX_VIO1_CTL_PU_MASK 0x10 -#define GC_PINMUX_VIO1_CTL_PU_SIZE 0x1 -#define GC_PINMUX_VIO1_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_PU_OFFSET 0x11c -#define GC_PINMUX_VIO1_CTL_INV_LSB 0x5 -#define GC_PINMUX_VIO1_CTL_INV_MASK 0x20 -#define GC_PINMUX_VIO1_CTL_INV_SIZE 0x1 -#define GC_PINMUX_VIO1_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_INV_OFFSET 0x11c +#define GC_PINMUX_RESETB_CTL_INV_OFFSET 0xf4 +#define GC_PINMUX_TRSTN_CTL_DS_LSB 0x0 +#define GC_PINMUX_TRSTN_CTL_DS_MASK 0x3 +#define GC_PINMUX_TRSTN_CTL_DS_SIZE 0x2 +#define GC_PINMUX_TRSTN_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_TRSTN_CTL_DS_OFFSET 0xfc +#define GC_PINMUX_TRSTN_CTL_IE_LSB 0x2 +#define GC_PINMUX_TRSTN_CTL_IE_MASK 0x4 +#define GC_PINMUX_TRSTN_CTL_IE_SIZE 0x1 +#define GC_PINMUX_TRSTN_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_TRSTN_CTL_IE_OFFSET 0xfc +#define GC_PINMUX_TRSTN_CTL_PD_LSB 0x3 +#define GC_PINMUX_TRSTN_CTL_PD_MASK 0x8 +#define GC_PINMUX_TRSTN_CTL_PD_SIZE 0x1 +#define GC_PINMUX_TRSTN_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_TRSTN_CTL_PD_OFFSET 0xfc +#define GC_PINMUX_TRSTN_CTL_PU_LSB 0x4 +#define GC_PINMUX_TRSTN_CTL_PU_MASK 0x10 +#define GC_PINMUX_TRSTN_CTL_PU_SIZE 0x1 +#define GC_PINMUX_TRSTN_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_TRSTN_CTL_PU_OFFSET 0xfc +#define GC_PINMUX_TRSTN_CTL_INV_LSB 0x5 +#define GC_PINMUX_TRSTN_CTL_INV_MASK 0x20 +#define GC_PINMUX_TRSTN_CTL_INV_SIZE 0x1 +#define GC_PINMUX_TRSTN_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_TRSTN_CTL_INV_OFFSET 0xfc #define GC_PINMUX_TDI_CTL_DS_LSB 0x0 #define GC_PINMUX_TDI_CTL_DS_MASK 0x3 #define GC_PINMUX_TDI_CTL_DS_SIZE 0x2 #define GC_PINMUX_TDI_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TDI_CTL_DS_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_DS_OFFSET 0x104 #define GC_PINMUX_TDI_CTL_IE_LSB 0x2 #define GC_PINMUX_TDI_CTL_IE_MASK 0x4 #define GC_PINMUX_TDI_CTL_IE_SIZE 0x1 #define GC_PINMUX_TDI_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_IE_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_IE_OFFSET 0x104 #define GC_PINMUX_TDI_CTL_PD_LSB 0x3 #define GC_PINMUX_TDI_CTL_PD_MASK 0x8 #define GC_PINMUX_TDI_CTL_PD_SIZE 0x1 #define GC_PINMUX_TDI_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_PD_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_PD_OFFSET 0x104 #define GC_PINMUX_TDI_CTL_PU_LSB 0x4 #define GC_PINMUX_TDI_CTL_PU_MASK 0x10 #define GC_PINMUX_TDI_CTL_PU_SIZE 0x1 #define GC_PINMUX_TDI_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_PU_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_PU_OFFSET 0x104 #define GC_PINMUX_TDI_CTL_INV_LSB 0x5 #define GC_PINMUX_TDI_CTL_INV_MASK 0x20 #define GC_PINMUX_TDI_CTL_INV_SIZE 0x1 #define GC_PINMUX_TDI_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_INV_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_INV_OFFSET 0x104 #define GC_PINMUX_TMS_CTL_DS_LSB 0x0 #define GC_PINMUX_TMS_CTL_DS_MASK 0x3 #define GC_PINMUX_TMS_CTL_DS_SIZE 0x2 #define GC_PINMUX_TMS_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TMS_CTL_DS_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_DS_OFFSET 0x10c #define GC_PINMUX_TMS_CTL_IE_LSB 0x2 #define GC_PINMUX_TMS_CTL_IE_MASK 0x4 #define GC_PINMUX_TMS_CTL_IE_SIZE 0x1 #define GC_PINMUX_TMS_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_IE_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_IE_OFFSET 0x10c #define GC_PINMUX_TMS_CTL_PD_LSB 0x3 #define GC_PINMUX_TMS_CTL_PD_MASK 0x8 #define GC_PINMUX_TMS_CTL_PD_SIZE 0x1 #define GC_PINMUX_TMS_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_PD_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_PD_OFFSET 0x10c #define GC_PINMUX_TMS_CTL_PU_LSB 0x4 #define GC_PINMUX_TMS_CTL_PU_MASK 0x10 #define GC_PINMUX_TMS_CTL_PU_SIZE 0x1 #define GC_PINMUX_TMS_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_PU_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_PU_OFFSET 0x10c #define GC_PINMUX_TMS_CTL_INV_LSB 0x5 #define GC_PINMUX_TMS_CTL_INV_MASK 0x20 #define GC_PINMUX_TMS_CTL_INV_SIZE 0x1 #define GC_PINMUX_TMS_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_INV_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_INV_OFFSET 0x10c #define GC_PINMUX_TCK_CTL_DS_LSB 0x0 #define GC_PINMUX_TCK_CTL_DS_MASK 0x3 #define GC_PINMUX_TCK_CTL_DS_SIZE 0x2 #define GC_PINMUX_TCK_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TCK_CTL_DS_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_DS_OFFSET 0x114 #define GC_PINMUX_TCK_CTL_IE_LSB 0x2 #define GC_PINMUX_TCK_CTL_IE_MASK 0x4 #define GC_PINMUX_TCK_CTL_IE_SIZE 0x1 #define GC_PINMUX_TCK_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_IE_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_IE_OFFSET 0x114 #define GC_PINMUX_TCK_CTL_PD_LSB 0x3 #define GC_PINMUX_TCK_CTL_PD_MASK 0x8 #define GC_PINMUX_TCK_CTL_PD_SIZE 0x1 #define GC_PINMUX_TCK_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_PD_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_PD_OFFSET 0x114 #define GC_PINMUX_TCK_CTL_PU_LSB 0x4 #define GC_PINMUX_TCK_CTL_PU_MASK 0x10 #define GC_PINMUX_TCK_CTL_PU_SIZE 0x1 #define GC_PINMUX_TCK_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_PU_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_PU_OFFSET 0x114 #define GC_PINMUX_TCK_CTL_INV_LSB 0x5 #define GC_PINMUX_TCK_CTL_INV_MASK 0x20 #define GC_PINMUX_TCK_CTL_INV_SIZE 0x1 #define GC_PINMUX_TCK_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_INV_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_INV_OFFSET 0x114 #define GC_PINMUX_TDO_CTL_DS_LSB 0x0 #define GC_PINMUX_TDO_CTL_DS_MASK 0x3 #define GC_PINMUX_TDO_CTL_DS_SIZE 0x2 #define GC_PINMUX_TDO_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TDO_CTL_DS_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_DS_OFFSET 0x11c #define GC_PINMUX_TDO_CTL_IE_LSB 0x2 #define GC_PINMUX_TDO_CTL_IE_MASK 0x4 #define GC_PINMUX_TDO_CTL_IE_SIZE 0x1 #define GC_PINMUX_TDO_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_IE_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_IE_OFFSET 0x11c #define GC_PINMUX_TDO_CTL_PD_LSB 0x3 #define GC_PINMUX_TDO_CTL_PD_MASK 0x8 #define GC_PINMUX_TDO_CTL_PD_SIZE 0x1 #define GC_PINMUX_TDO_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_PD_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_PD_OFFSET 0x11c #define GC_PINMUX_TDO_CTL_PU_LSB 0x4 #define GC_PINMUX_TDO_CTL_PU_MASK 0x10 #define GC_PINMUX_TDO_CTL_PU_SIZE 0x1 #define GC_PINMUX_TDO_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_PU_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_PU_OFFSET 0x11c #define GC_PINMUX_TDO_CTL_INV_LSB 0x5 #define GC_PINMUX_TDO_CTL_INV_MASK 0x20 #define GC_PINMUX_TDO_CTL_INV_SIZE 0x1 #define GC_PINMUX_TDO_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_INV_OFFSET 0x13c -#define GC_PINMUX_SETHOLD0_DIOM0_LSB 0x0 -#define GC_PINMUX_SETHOLD0_DIOM0_MASK 0x1 -#define GC_PINMUX_SETHOLD0_DIOM0_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOM0_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOM1_LSB 0x1 -#define GC_PINMUX_SETHOLD0_DIOM1_MASK 0x2 -#define GC_PINMUX_SETHOLD0_DIOM1_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOM1_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOM2_LSB 0x2 -#define GC_PINMUX_SETHOLD0_DIOM2_MASK 0x4 -#define GC_PINMUX_SETHOLD0_DIOM2_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOM2_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOM3_LSB 0x3 -#define GC_PINMUX_SETHOLD0_DIOM3_MASK 0x8 -#define GC_PINMUX_SETHOLD0_DIOM3_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOM3_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOM4_LSB 0x4 -#define GC_PINMUX_SETHOLD0_DIOM4_MASK 0x10 -#define GC_PINMUX_SETHOLD0_DIOM4_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOM4_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA0_LSB 0x5 -#define GC_PINMUX_SETHOLD0_DIOA0_MASK 0x20 -#define GC_PINMUX_SETHOLD0_DIOA0_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA0_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA1_LSB 0x6 -#define GC_PINMUX_SETHOLD0_DIOA1_MASK 0x40 -#define GC_PINMUX_SETHOLD0_DIOA1_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA1_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA2_LSB 0x7 -#define GC_PINMUX_SETHOLD0_DIOA2_MASK 0x80 -#define GC_PINMUX_SETHOLD0_DIOA2_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA2_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA3_LSB 0x8 -#define GC_PINMUX_SETHOLD0_DIOA3_MASK 0x100 -#define GC_PINMUX_SETHOLD0_DIOA3_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA3_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA4_LSB 0x9 -#define GC_PINMUX_SETHOLD0_DIOA4_MASK 0x200 -#define GC_PINMUX_SETHOLD0_DIOA4_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA4_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA5_LSB 0xa -#define GC_PINMUX_SETHOLD0_DIOA5_MASK 0x400 -#define GC_PINMUX_SETHOLD0_DIOA5_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA5_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA6_LSB 0xb -#define GC_PINMUX_SETHOLD0_DIOA6_MASK 0x800 -#define GC_PINMUX_SETHOLD0_DIOA6_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA6_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA7_LSB 0xc -#define GC_PINMUX_SETHOLD0_DIOA7_MASK 0x1000 -#define GC_PINMUX_SETHOLD0_DIOA7_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA7_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA8_LSB 0xd -#define GC_PINMUX_SETHOLD0_DIOA8_MASK 0x2000 -#define GC_PINMUX_SETHOLD0_DIOA8_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA8_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA9_LSB 0xe -#define GC_PINMUX_SETHOLD0_DIOA9_MASK 0x4000 -#define GC_PINMUX_SETHOLD0_DIOA9_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA9_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA10_LSB 0xf -#define GC_PINMUX_SETHOLD0_DIOA10_MASK 0x8000 -#define GC_PINMUX_SETHOLD0_DIOA10_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA10_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA11_LSB 0x10 -#define GC_PINMUX_SETHOLD0_DIOA11_MASK 0x10000 -#define GC_PINMUX_SETHOLD0_DIOA11_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA11_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA12_LSB 0x11 -#define GC_PINMUX_SETHOLD0_DIOA12_MASK 0x20000 -#define GC_PINMUX_SETHOLD0_DIOA12_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA12_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA13_LSB 0x12 -#define GC_PINMUX_SETHOLD0_DIOA13_MASK 0x40000 -#define GC_PINMUX_SETHOLD0_DIOA13_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA13_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOA14_LSB 0x13 -#define GC_PINMUX_SETHOLD0_DIOA14_MASK 0x80000 -#define GC_PINMUX_SETHOLD0_DIOA14_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOA14_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOB0_LSB 0x14 -#define GC_PINMUX_SETHOLD0_DIOB0_MASK 0x100000 -#define GC_PINMUX_SETHOLD0_DIOB0_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOB0_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOB1_LSB 0x15 -#define GC_PINMUX_SETHOLD0_DIOB1_MASK 0x200000 -#define GC_PINMUX_SETHOLD0_DIOB1_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOB1_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOB2_LSB 0x16 -#define GC_PINMUX_SETHOLD0_DIOB2_MASK 0x400000 -#define GC_PINMUX_SETHOLD0_DIOB2_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOB2_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOB3_LSB 0x17 -#define GC_PINMUX_SETHOLD0_DIOB3_MASK 0x800000 -#define GC_PINMUX_SETHOLD0_DIOB3_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOB3_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOB4_LSB 0x18 -#define GC_PINMUX_SETHOLD0_DIOB4_MASK 0x1000000 -#define GC_PINMUX_SETHOLD0_DIOB4_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOB4_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOB5_LSB 0x19 -#define GC_PINMUX_SETHOLD0_DIOB5_MASK 0x2000000 -#define GC_PINMUX_SETHOLD0_DIOB5_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOB5_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOB6_LSB 0x1a -#define GC_PINMUX_SETHOLD0_DIOB6_MASK 0x4000000 -#define GC_PINMUX_SETHOLD0_DIOB6_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOB6_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOB7_LSB 0x1b -#define GC_PINMUX_SETHOLD0_DIOB7_MASK 0x8000000 -#define GC_PINMUX_SETHOLD0_DIOB7_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOB7_OFFSET 0x140 -#define GC_PINMUX_SETHOLD0_DIOB8_LSB 0x1c -#define GC_PINMUX_SETHOLD0_DIOB8_MASK 0x10000000 -#define GC_PINMUX_SETHOLD0_DIOB8_SIZE 0x1 -#define GC_PINMUX_SETHOLD0_DIOB8_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD0_DIOB8_OFFSET 0x140 -#define GC_PINMUX_SETHOLD1_RTCXOP_LSB 0xc -#define GC_PINMUX_SETHOLD1_RTCXOP_MASK 0x1000 -#define GC_PINMUX_SETHOLD1_RTCXOP_SIZE 0x1 -#define GC_PINMUX_SETHOLD1_RTCXOP_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD1_RTCXOP_OFFSET 0x144 -#define GC_PINMUX_SETHOLD1_SWDPTRACE_LSB 0xd -#define GC_PINMUX_SETHOLD1_SWDPTRACE_MASK 0x2000 -#define GC_PINMUX_SETHOLD1_SWDPTRACE_SIZE 0x1 -#define GC_PINMUX_SETHOLD1_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD1_SWDPTRACE_OFFSET 0x144 -#define GC_PINMUX_SETHOLD1_SWDPDATA_LSB 0xe -#define GC_PINMUX_SETHOLD1_SWDPDATA_MASK 0x4000 -#define GC_PINMUX_SETHOLD1_SWDPDATA_SIZE 0x1 -#define GC_PINMUX_SETHOLD1_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD1_SWDPDATA_OFFSET 0x144 -#define GC_PINMUX_SETHOLD1_VIO0_LSB 0x12 -#define GC_PINMUX_SETHOLD1_VIO0_MASK 0x40000 -#define GC_PINMUX_SETHOLD1_VIO0_SIZE 0x1 -#define GC_PINMUX_SETHOLD1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD1_VIO0_OFFSET 0x144 -#define GC_PINMUX_SETHOLD1_VIO1_LSB 0x13 -#define GC_PINMUX_SETHOLD1_VIO1_MASK 0x80000 -#define GC_PINMUX_SETHOLD1_VIO1_SIZE 0x1 -#define GC_PINMUX_SETHOLD1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD1_VIO1_OFFSET 0x144 -#define GC_PINMUX_SETHOLD1_TDO_LSB 0x17 -#define GC_PINMUX_SETHOLD1_TDO_MASK 0x800000 -#define GC_PINMUX_SETHOLD1_TDO_SIZE 0x1 -#define GC_PINMUX_SETHOLD1_TDO_DEFAULT 0x0 -#define GC_PINMUX_SETHOLD1_TDO_OFFSET 0x144 -#define GC_PINMUX_CLRHOLD0_DIOM0_LSB 0x0 -#define GC_PINMUX_CLRHOLD0_DIOM0_MASK 0x1 -#define GC_PINMUX_CLRHOLD0_DIOM0_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOM0_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOM1_LSB 0x1 -#define GC_PINMUX_CLRHOLD0_DIOM1_MASK 0x2 -#define GC_PINMUX_CLRHOLD0_DIOM1_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOM1_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOM2_LSB 0x2 -#define GC_PINMUX_CLRHOLD0_DIOM2_MASK 0x4 -#define GC_PINMUX_CLRHOLD0_DIOM2_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOM2_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOM3_LSB 0x3 -#define GC_PINMUX_CLRHOLD0_DIOM3_MASK 0x8 -#define GC_PINMUX_CLRHOLD0_DIOM3_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOM3_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOM4_LSB 0x4 -#define GC_PINMUX_CLRHOLD0_DIOM4_MASK 0x10 -#define GC_PINMUX_CLRHOLD0_DIOM4_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOM4_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA0_LSB 0x5 -#define GC_PINMUX_CLRHOLD0_DIOA0_MASK 0x20 -#define GC_PINMUX_CLRHOLD0_DIOA0_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA0_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA1_LSB 0x6 -#define GC_PINMUX_CLRHOLD0_DIOA1_MASK 0x40 -#define GC_PINMUX_CLRHOLD0_DIOA1_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA1_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA2_LSB 0x7 -#define GC_PINMUX_CLRHOLD0_DIOA2_MASK 0x80 -#define GC_PINMUX_CLRHOLD0_DIOA2_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA2_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA3_LSB 0x8 -#define GC_PINMUX_CLRHOLD0_DIOA3_MASK 0x100 -#define GC_PINMUX_CLRHOLD0_DIOA3_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA3_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA4_LSB 0x9 -#define GC_PINMUX_CLRHOLD0_DIOA4_MASK 0x200 -#define GC_PINMUX_CLRHOLD0_DIOA4_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA4_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA5_LSB 0xa -#define GC_PINMUX_CLRHOLD0_DIOA5_MASK 0x400 -#define GC_PINMUX_CLRHOLD0_DIOA5_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA5_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA6_LSB 0xb -#define GC_PINMUX_CLRHOLD0_DIOA6_MASK 0x800 -#define GC_PINMUX_CLRHOLD0_DIOA6_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA6_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA7_LSB 0xc -#define GC_PINMUX_CLRHOLD0_DIOA7_MASK 0x1000 -#define GC_PINMUX_CLRHOLD0_DIOA7_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA7_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA8_LSB 0xd -#define GC_PINMUX_CLRHOLD0_DIOA8_MASK 0x2000 -#define GC_PINMUX_CLRHOLD0_DIOA8_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA8_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA9_LSB 0xe -#define GC_PINMUX_CLRHOLD0_DIOA9_MASK 0x4000 -#define GC_PINMUX_CLRHOLD0_DIOA9_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA9_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA10_LSB 0xf -#define GC_PINMUX_CLRHOLD0_DIOA10_MASK 0x8000 -#define GC_PINMUX_CLRHOLD0_DIOA10_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA10_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA11_LSB 0x10 -#define GC_PINMUX_CLRHOLD0_DIOA11_MASK 0x10000 -#define GC_PINMUX_CLRHOLD0_DIOA11_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA11_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA12_LSB 0x11 -#define GC_PINMUX_CLRHOLD0_DIOA12_MASK 0x20000 -#define GC_PINMUX_CLRHOLD0_DIOA12_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA12_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA13_LSB 0x12 -#define GC_PINMUX_CLRHOLD0_DIOA13_MASK 0x40000 -#define GC_PINMUX_CLRHOLD0_DIOA13_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA13_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOA14_LSB 0x13 -#define GC_PINMUX_CLRHOLD0_DIOA14_MASK 0x80000 -#define GC_PINMUX_CLRHOLD0_DIOA14_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOA14_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOB0_LSB 0x14 -#define GC_PINMUX_CLRHOLD0_DIOB0_MASK 0x100000 -#define GC_PINMUX_CLRHOLD0_DIOB0_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOB0_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOB1_LSB 0x15 -#define GC_PINMUX_CLRHOLD0_DIOB1_MASK 0x200000 -#define GC_PINMUX_CLRHOLD0_DIOB1_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOB1_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOB2_LSB 0x16 -#define GC_PINMUX_CLRHOLD0_DIOB2_MASK 0x400000 -#define GC_PINMUX_CLRHOLD0_DIOB2_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOB2_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOB3_LSB 0x17 -#define GC_PINMUX_CLRHOLD0_DIOB3_MASK 0x800000 -#define GC_PINMUX_CLRHOLD0_DIOB3_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOB3_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOB4_LSB 0x18 -#define GC_PINMUX_CLRHOLD0_DIOB4_MASK 0x1000000 -#define GC_PINMUX_CLRHOLD0_DIOB4_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOB4_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOB5_LSB 0x19 -#define GC_PINMUX_CLRHOLD0_DIOB5_MASK 0x2000000 -#define GC_PINMUX_CLRHOLD0_DIOB5_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOB5_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOB6_LSB 0x1a -#define GC_PINMUX_CLRHOLD0_DIOB6_MASK 0x4000000 -#define GC_PINMUX_CLRHOLD0_DIOB6_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOB6_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOB7_LSB 0x1b -#define GC_PINMUX_CLRHOLD0_DIOB7_MASK 0x8000000 -#define GC_PINMUX_CLRHOLD0_DIOB7_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOB7_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD0_DIOB8_LSB 0x1c -#define GC_PINMUX_CLRHOLD0_DIOB8_MASK 0x10000000 -#define GC_PINMUX_CLRHOLD0_DIOB8_SIZE 0x1 -#define GC_PINMUX_CLRHOLD0_DIOB8_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD0_DIOB8_OFFSET 0x148 -#define GC_PINMUX_CLRHOLD1_RTCXOP_LSB 0xc -#define GC_PINMUX_CLRHOLD1_RTCXOP_MASK 0x1000 -#define GC_PINMUX_CLRHOLD1_RTCXOP_SIZE 0x1 -#define GC_PINMUX_CLRHOLD1_RTCXOP_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD1_RTCXOP_OFFSET 0x14c -#define GC_PINMUX_CLRHOLD1_SWDPTRACE_LSB 0xd -#define GC_PINMUX_CLRHOLD1_SWDPTRACE_MASK 0x2000 -#define GC_PINMUX_CLRHOLD1_SWDPTRACE_SIZE 0x1 -#define GC_PINMUX_CLRHOLD1_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD1_SWDPTRACE_OFFSET 0x14c -#define GC_PINMUX_CLRHOLD1_SWDPDATA_LSB 0xe -#define GC_PINMUX_CLRHOLD1_SWDPDATA_MASK 0x4000 -#define GC_PINMUX_CLRHOLD1_SWDPDATA_SIZE 0x1 -#define GC_PINMUX_CLRHOLD1_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD1_SWDPDATA_OFFSET 0x14c -#define GC_PINMUX_CLRHOLD1_VIO0_LSB 0x12 -#define GC_PINMUX_CLRHOLD1_VIO0_MASK 0x40000 -#define GC_PINMUX_CLRHOLD1_VIO0_SIZE 0x1 -#define GC_PINMUX_CLRHOLD1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD1_VIO0_OFFSET 0x14c -#define GC_PINMUX_CLRHOLD1_VIO1_LSB 0x13 -#define GC_PINMUX_CLRHOLD1_VIO1_MASK 0x80000 -#define GC_PINMUX_CLRHOLD1_VIO1_SIZE 0x1 -#define GC_PINMUX_CLRHOLD1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD1_VIO1_OFFSET 0x14c -#define GC_PINMUX_CLRHOLD1_TDO_LSB 0x17 -#define GC_PINMUX_CLRHOLD1_TDO_MASK 0x800000 -#define GC_PINMUX_CLRHOLD1_TDO_SIZE 0x1 -#define GC_PINMUX_CLRHOLD1_TDO_DEFAULT 0x0 -#define GC_PINMUX_CLRHOLD1_TDO_OFFSET 0x14c +#define GC_PINMUX_TDO_CTL_INV_OFFSET 0x11c +#define GC_PINMUX_VIO0_CTL_DS_LSB 0x0 +#define GC_PINMUX_VIO0_CTL_DS_MASK 0x3 +#define GC_PINMUX_VIO0_CTL_DS_SIZE 0x2 +#define GC_PINMUX_VIO0_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_VIO0_CTL_DS_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_IE_LSB 0x2 +#define GC_PINMUX_VIO0_CTL_IE_MASK 0x4 +#define GC_PINMUX_VIO0_CTL_IE_SIZE 0x1 +#define GC_PINMUX_VIO0_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_IE_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_PD_LSB 0x3 +#define GC_PINMUX_VIO0_CTL_PD_MASK 0x8 +#define GC_PINMUX_VIO0_CTL_PD_SIZE 0x1 +#define GC_PINMUX_VIO0_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_PD_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_PU_LSB 0x4 +#define GC_PINMUX_VIO0_CTL_PU_MASK 0x10 +#define GC_PINMUX_VIO0_CTL_PU_SIZE 0x1 +#define GC_PINMUX_VIO0_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_PU_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_INV_LSB 0x5 +#define GC_PINMUX_VIO0_CTL_INV_MASK 0x20 +#define GC_PINMUX_VIO0_CTL_INV_SIZE 0x1 +#define GC_PINMUX_VIO0_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_INV_OFFSET 0x124 +#define GC_PINMUX_VIO1_CTL_DS_LSB 0x0 +#define GC_PINMUX_VIO1_CTL_DS_MASK 0x3 +#define GC_PINMUX_VIO1_CTL_DS_SIZE 0x2 +#define GC_PINMUX_VIO1_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_VIO1_CTL_DS_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_IE_LSB 0x2 +#define GC_PINMUX_VIO1_CTL_IE_MASK 0x4 +#define GC_PINMUX_VIO1_CTL_IE_SIZE 0x1 +#define GC_PINMUX_VIO1_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_IE_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_PD_LSB 0x3 +#define GC_PINMUX_VIO1_CTL_PD_MASK 0x8 +#define GC_PINMUX_VIO1_CTL_PD_SIZE 0x1 +#define GC_PINMUX_VIO1_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_PD_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_PU_LSB 0x4 +#define GC_PINMUX_VIO1_CTL_PU_MASK 0x10 +#define GC_PINMUX_VIO1_CTL_PU_SIZE 0x1 +#define GC_PINMUX_VIO1_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_PU_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_INV_LSB 0x5 +#define GC_PINMUX_VIO1_CTL_INV_MASK 0x20 +#define GC_PINMUX_VIO1_CTL_INV_SIZE 0x1 +#define GC_PINMUX_VIO1_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_INV_OFFSET 0x12c #define GC_PINMUX_EXITEN0_DIOM0_LSB 0x0 #define GC_PINMUX_EXITEN0_DIOM0_MASK 0x1 #define GC_PINMUX_EXITEN0_DIOM0_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM0_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOM0_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOM1_LSB 0x1 #define GC_PINMUX_EXITEN0_DIOM1_MASK 0x2 #define GC_PINMUX_EXITEN0_DIOM1_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM1_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOM1_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOM2_LSB 0x2 #define GC_PINMUX_EXITEN0_DIOM2_MASK 0x4 #define GC_PINMUX_EXITEN0_DIOM2_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM2_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOM2_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOM3_LSB 0x3 #define GC_PINMUX_EXITEN0_DIOM3_MASK 0x8 #define GC_PINMUX_EXITEN0_DIOM3_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM3_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOM3_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOM4_LSB 0x4 #define GC_PINMUX_EXITEN0_DIOM4_MASK 0x10 #define GC_PINMUX_EXITEN0_DIOM4_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM4_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOM4_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA0_LSB 0x5 #define GC_PINMUX_EXITEN0_DIOA0_MASK 0x20 #define GC_PINMUX_EXITEN0_DIOA0_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA0_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA0_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA1_LSB 0x6 #define GC_PINMUX_EXITEN0_DIOA1_MASK 0x40 #define GC_PINMUX_EXITEN0_DIOA1_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA1_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA1_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA2_LSB 0x7 #define GC_PINMUX_EXITEN0_DIOA2_MASK 0x80 #define GC_PINMUX_EXITEN0_DIOA2_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA2_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA2_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA3_LSB 0x8 #define GC_PINMUX_EXITEN0_DIOA3_MASK 0x100 #define GC_PINMUX_EXITEN0_DIOA3_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA3_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA3_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA4_LSB 0x9 #define GC_PINMUX_EXITEN0_DIOA4_MASK 0x200 #define GC_PINMUX_EXITEN0_DIOA4_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA4_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA4_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA5_LSB 0xa #define GC_PINMUX_EXITEN0_DIOA5_MASK 0x400 #define GC_PINMUX_EXITEN0_DIOA5_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA5_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA5_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA6_LSB 0xb #define GC_PINMUX_EXITEN0_DIOA6_MASK 0x800 #define GC_PINMUX_EXITEN0_DIOA6_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA6_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA6_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA7_LSB 0xc #define GC_PINMUX_EXITEN0_DIOA7_MASK 0x1000 #define GC_PINMUX_EXITEN0_DIOA7_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA7_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA7_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA8_LSB 0xd #define GC_PINMUX_EXITEN0_DIOA8_MASK 0x2000 #define GC_PINMUX_EXITEN0_DIOA8_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA8_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA8_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA9_LSB 0xe #define GC_PINMUX_EXITEN0_DIOA9_MASK 0x4000 #define GC_PINMUX_EXITEN0_DIOA9_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA9_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA9_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA10_LSB 0xf #define GC_PINMUX_EXITEN0_DIOA10_MASK 0x8000 #define GC_PINMUX_EXITEN0_DIOA10_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA10_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA10_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA11_LSB 0x10 #define GC_PINMUX_EXITEN0_DIOA11_MASK 0x10000 #define GC_PINMUX_EXITEN0_DIOA11_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA11_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA11_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA12_LSB 0x11 #define GC_PINMUX_EXITEN0_DIOA12_MASK 0x20000 #define GC_PINMUX_EXITEN0_DIOA12_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA12_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA12_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA13_LSB 0x12 #define GC_PINMUX_EXITEN0_DIOA13_MASK 0x40000 #define GC_PINMUX_EXITEN0_DIOA13_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA13_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA13_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOA14_LSB 0x13 #define GC_PINMUX_EXITEN0_DIOA14_MASK 0x80000 #define GC_PINMUX_EXITEN0_DIOA14_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA14_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA14_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOB0_LSB 0x14 #define GC_PINMUX_EXITEN0_DIOB0_MASK 0x100000 #define GC_PINMUX_EXITEN0_DIOB0_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB0_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB0_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOB1_LSB 0x15 #define GC_PINMUX_EXITEN0_DIOB1_MASK 0x200000 #define GC_PINMUX_EXITEN0_DIOB1_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB1_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB1_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOB2_LSB 0x16 #define GC_PINMUX_EXITEN0_DIOB2_MASK 0x400000 #define GC_PINMUX_EXITEN0_DIOB2_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB2_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB2_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOB3_LSB 0x17 #define GC_PINMUX_EXITEN0_DIOB3_MASK 0x800000 #define GC_PINMUX_EXITEN0_DIOB3_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB3_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB3_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOB4_LSB 0x18 #define GC_PINMUX_EXITEN0_DIOB4_MASK 0x1000000 #define GC_PINMUX_EXITEN0_DIOB4_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB4_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB4_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOB5_LSB 0x19 #define GC_PINMUX_EXITEN0_DIOB5_MASK 0x2000000 #define GC_PINMUX_EXITEN0_DIOB5_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB5_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB5_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOB6_LSB 0x1a #define GC_PINMUX_EXITEN0_DIOB6_MASK 0x4000000 #define GC_PINMUX_EXITEN0_DIOB6_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB6_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB6_OFFSET 0x260 #define GC_PINMUX_EXITEN0_DIOB7_LSB 0x1b #define GC_PINMUX_EXITEN0_DIOB7_MASK 0x8000000 #define GC_PINMUX_EXITEN0_DIOB7_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB7_OFFSET 0x2e0 -#define GC_PINMUX_EXITEN0_DIOB8_LSB 0x1c -#define GC_PINMUX_EXITEN0_DIOB8_MASK 0x10000000 -#define GC_PINMUX_EXITEN0_DIOB8_SIZE 0x1 -#define GC_PINMUX_EXITEN0_DIOB8_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB8_OFFSET 0x2e0 -#define GC_PINMUX_EXITEN1_RTCXOP_LSB 0xc -#define GC_PINMUX_EXITEN1_RTCXOP_MASK 0x1000 -#define GC_PINMUX_EXITEN1_RTCXOP_SIZE 0x1 -#define GC_PINMUX_EXITEN1_RTCXOP_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_RTCXOP_OFFSET 0x2e4 -#define GC_PINMUX_EXITEN1_SWDPTRACE_LSB 0xd -#define GC_PINMUX_EXITEN1_SWDPTRACE_MASK 0x2000 -#define GC_PINMUX_EXITEN1_SWDPTRACE_SIZE 0x1 -#define GC_PINMUX_EXITEN1_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_SWDPTRACE_OFFSET 0x2e4 -#define GC_PINMUX_EXITEN1_SWDPDATA_LSB 0xe -#define GC_PINMUX_EXITEN1_SWDPDATA_MASK 0x4000 -#define GC_PINMUX_EXITEN1_SWDPDATA_SIZE 0x1 -#define GC_PINMUX_EXITEN1_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_SWDPDATA_OFFSET 0x2e4 -#define GC_PINMUX_EXITEN1_VIO0_LSB 0x12 -#define GC_PINMUX_EXITEN1_VIO0_MASK 0x40000 +#define GC_PINMUX_EXITEN0_DIOB7_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_SWDPTRACE_LSB 0x1c +#define GC_PINMUX_EXITEN0_SWDPTRACE_MASK 0x10000000 +#define GC_PINMUX_EXITEN0_SWDPTRACE_SIZE 0x1 +#define GC_PINMUX_EXITEN0_SWDPTRACE_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_SWDPTRACE_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_SWDPDATA_LSB 0x1d +#define GC_PINMUX_EXITEN0_SWDPDATA_MASK 0x20000000 +#define GC_PINMUX_EXITEN0_SWDPDATA_SIZE 0x1 +#define GC_PINMUX_EXITEN0_SWDPDATA_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_SWDPDATA_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_TRSTN_LSB 0x1e +#define GC_PINMUX_EXITEN0_TRSTN_MASK 0x40000000 +#define GC_PINMUX_EXITEN0_TRSTN_SIZE 0x1 +#define GC_PINMUX_EXITEN0_TRSTN_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_TRSTN_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_TDI_LSB 0x1f +#define GC_PINMUX_EXITEN0_TDI_MASK 0x80000000 +#define GC_PINMUX_EXITEN0_TDI_SIZE 0x1 +#define GC_PINMUX_EXITEN0_TDI_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_TDI_OFFSET 0x260 +#define GC_PINMUX_EXITEN1_TMS_LSB 0x0 +#define GC_PINMUX_EXITEN1_TMS_MASK 0x1 +#define GC_PINMUX_EXITEN1_TMS_SIZE 0x1 +#define GC_PINMUX_EXITEN1_TMS_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_TMS_OFFSET 0x264 +#define GC_PINMUX_EXITEN1_TCK_LSB 0x1 +#define GC_PINMUX_EXITEN1_TCK_MASK 0x2 +#define GC_PINMUX_EXITEN1_TCK_SIZE 0x1 +#define GC_PINMUX_EXITEN1_TCK_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_TCK_OFFSET 0x264 +#define GC_PINMUX_EXITEN1_TDO_LSB 0x2 +#define GC_PINMUX_EXITEN1_TDO_MASK 0x4 +#define GC_PINMUX_EXITEN1_TDO_SIZE 0x1 +#define GC_PINMUX_EXITEN1_TDO_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_TDO_OFFSET 0x264 +#define GC_PINMUX_EXITEN1_VIO0_LSB 0x3 +#define GC_PINMUX_EXITEN1_VIO0_MASK 0x8 #define GC_PINMUX_EXITEN1_VIO0_SIZE 0x1 #define GC_PINMUX_EXITEN1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_VIO0_OFFSET 0x2e4 -#define GC_PINMUX_EXITEN1_VIO1_LSB 0x13 -#define GC_PINMUX_EXITEN1_VIO1_MASK 0x80000 +#define GC_PINMUX_EXITEN1_VIO0_OFFSET 0x264 +#define GC_PINMUX_EXITEN1_VIO1_LSB 0x4 +#define GC_PINMUX_EXITEN1_VIO1_MASK 0x10 #define GC_PINMUX_EXITEN1_VIO1_SIZE 0x1 #define GC_PINMUX_EXITEN1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_VIO1_OFFSET 0x2e4 -#define GC_PINMUX_EXITEN1_TDO_LSB 0x17 -#define GC_PINMUX_EXITEN1_TDO_MASK 0x800000 -#define GC_PINMUX_EXITEN1_TDO_SIZE 0x1 -#define GC_PINMUX_EXITEN1_TDO_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_TDO_OFFSET 0x2e4 +#define GC_PINMUX_EXITEN1_VIO1_OFFSET 0x264 #define GC_PINMUX_EXITEDGE0_DIOM0_LSB 0x0 #define GC_PINMUX_EXITEDGE0_DIOM0_MASK 0x1 #define GC_PINMUX_EXITEDGE0_DIOM0_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM0_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOM0_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOM1_LSB 0x1 #define GC_PINMUX_EXITEDGE0_DIOM1_MASK 0x2 #define GC_PINMUX_EXITEDGE0_DIOM1_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM1_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOM1_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOM2_LSB 0x2 #define GC_PINMUX_EXITEDGE0_DIOM2_MASK 0x4 #define GC_PINMUX_EXITEDGE0_DIOM2_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM2_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOM2_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOM3_LSB 0x3 #define GC_PINMUX_EXITEDGE0_DIOM3_MASK 0x8 #define GC_PINMUX_EXITEDGE0_DIOM3_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM3_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOM3_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOM4_LSB 0x4 #define GC_PINMUX_EXITEDGE0_DIOM4_MASK 0x10 #define GC_PINMUX_EXITEDGE0_DIOM4_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM4_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOM4_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA0_LSB 0x5 #define GC_PINMUX_EXITEDGE0_DIOA0_MASK 0x20 #define GC_PINMUX_EXITEDGE0_DIOA0_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA0_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA0_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA1_LSB 0x6 #define GC_PINMUX_EXITEDGE0_DIOA1_MASK 0x40 #define GC_PINMUX_EXITEDGE0_DIOA1_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA1_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA1_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA2_LSB 0x7 #define GC_PINMUX_EXITEDGE0_DIOA2_MASK 0x80 #define GC_PINMUX_EXITEDGE0_DIOA2_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA2_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA2_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA3_LSB 0x8 #define GC_PINMUX_EXITEDGE0_DIOA3_MASK 0x100 #define GC_PINMUX_EXITEDGE0_DIOA3_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA3_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA3_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA4_LSB 0x9 #define GC_PINMUX_EXITEDGE0_DIOA4_MASK 0x200 #define GC_PINMUX_EXITEDGE0_DIOA4_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA4_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA4_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA5_LSB 0xa #define GC_PINMUX_EXITEDGE0_DIOA5_MASK 0x400 #define GC_PINMUX_EXITEDGE0_DIOA5_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA5_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA5_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA6_LSB 0xb #define GC_PINMUX_EXITEDGE0_DIOA6_MASK 0x800 #define GC_PINMUX_EXITEDGE0_DIOA6_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA6_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA6_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA7_LSB 0xc #define GC_PINMUX_EXITEDGE0_DIOA7_MASK 0x1000 #define GC_PINMUX_EXITEDGE0_DIOA7_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA7_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA7_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA8_LSB 0xd #define GC_PINMUX_EXITEDGE0_DIOA8_MASK 0x2000 #define GC_PINMUX_EXITEDGE0_DIOA8_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA8_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA8_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA9_LSB 0xe #define GC_PINMUX_EXITEDGE0_DIOA9_MASK 0x4000 #define GC_PINMUX_EXITEDGE0_DIOA9_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA9_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA9_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA10_LSB 0xf #define GC_PINMUX_EXITEDGE0_DIOA10_MASK 0x8000 #define GC_PINMUX_EXITEDGE0_DIOA10_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA10_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA10_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA11_LSB 0x10 #define GC_PINMUX_EXITEDGE0_DIOA11_MASK 0x10000 #define GC_PINMUX_EXITEDGE0_DIOA11_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA11_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA11_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA12_LSB 0x11 #define GC_PINMUX_EXITEDGE0_DIOA12_MASK 0x20000 #define GC_PINMUX_EXITEDGE0_DIOA12_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA12_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA12_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA13_LSB 0x12 #define GC_PINMUX_EXITEDGE0_DIOA13_MASK 0x40000 #define GC_PINMUX_EXITEDGE0_DIOA13_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA13_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA13_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOA14_LSB 0x13 #define GC_PINMUX_EXITEDGE0_DIOA14_MASK 0x80000 #define GC_PINMUX_EXITEDGE0_DIOA14_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA14_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA14_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOB0_LSB 0x14 #define GC_PINMUX_EXITEDGE0_DIOB0_MASK 0x100000 #define GC_PINMUX_EXITEDGE0_DIOB0_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB0_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB0_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOB1_LSB 0x15 #define GC_PINMUX_EXITEDGE0_DIOB1_MASK 0x200000 #define GC_PINMUX_EXITEDGE0_DIOB1_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB1_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB1_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOB2_LSB 0x16 #define GC_PINMUX_EXITEDGE0_DIOB2_MASK 0x400000 #define GC_PINMUX_EXITEDGE0_DIOB2_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB2_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB2_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOB3_LSB 0x17 #define GC_PINMUX_EXITEDGE0_DIOB3_MASK 0x800000 #define GC_PINMUX_EXITEDGE0_DIOB3_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB3_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB3_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOB4_LSB 0x18 #define GC_PINMUX_EXITEDGE0_DIOB4_MASK 0x1000000 #define GC_PINMUX_EXITEDGE0_DIOB4_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB4_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB4_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOB5_LSB 0x19 #define GC_PINMUX_EXITEDGE0_DIOB5_MASK 0x2000000 #define GC_PINMUX_EXITEDGE0_DIOB5_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB5_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB5_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOB6_LSB 0x1a #define GC_PINMUX_EXITEDGE0_DIOB6_MASK 0x4000000 #define GC_PINMUX_EXITEDGE0_DIOB6_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB6_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB6_OFFSET 0x268 #define GC_PINMUX_EXITEDGE0_DIOB7_LSB 0x1b #define GC_PINMUX_EXITEDGE0_DIOB7_MASK 0x8000000 #define GC_PINMUX_EXITEDGE0_DIOB7_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB7_OFFSET 0x2e8 -#define GC_PINMUX_EXITEDGE0_DIOB8_LSB 0x1c -#define GC_PINMUX_EXITEDGE0_DIOB8_MASK 0x10000000 -#define GC_PINMUX_EXITEDGE0_DIOB8_SIZE 0x1 -#define GC_PINMUX_EXITEDGE0_DIOB8_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB8_OFFSET 0x2e8 -#define GC_PINMUX_EXITEDGE1_RTCXOP_LSB 0xc -#define GC_PINMUX_EXITEDGE1_RTCXOP_MASK 0x1000 -#define GC_PINMUX_EXITEDGE1_RTCXOP_SIZE 0x1 -#define GC_PINMUX_EXITEDGE1_RTCXOP_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_RTCXOP_OFFSET 0x2ec -#define GC_PINMUX_EXITEDGE1_SWDPTRACE_LSB 0xd -#define GC_PINMUX_EXITEDGE1_SWDPTRACE_MASK 0x2000 -#define GC_PINMUX_EXITEDGE1_SWDPTRACE_SIZE 0x1 -#define GC_PINMUX_EXITEDGE1_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_SWDPTRACE_OFFSET 0x2ec -#define GC_PINMUX_EXITEDGE1_SWDPDATA_LSB 0xe -#define GC_PINMUX_EXITEDGE1_SWDPDATA_MASK 0x4000 -#define GC_PINMUX_EXITEDGE1_SWDPDATA_SIZE 0x1 -#define GC_PINMUX_EXITEDGE1_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_SWDPDATA_OFFSET 0x2ec -#define GC_PINMUX_EXITEDGE1_VIO0_LSB 0x12 -#define GC_PINMUX_EXITEDGE1_VIO0_MASK 0x40000 +#define GC_PINMUX_EXITEDGE0_DIOB7_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_SWDPTRACE_LSB 0x1c +#define GC_PINMUX_EXITEDGE0_SWDPTRACE_MASK 0x10000000 +#define GC_PINMUX_EXITEDGE0_SWDPTRACE_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_SWDPTRACE_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_SWDPTRACE_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_SWDPDATA_LSB 0x1d +#define GC_PINMUX_EXITEDGE0_SWDPDATA_MASK 0x20000000 +#define GC_PINMUX_EXITEDGE0_SWDPDATA_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_SWDPDATA_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_SWDPDATA_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_TRSTN_LSB 0x1e +#define GC_PINMUX_EXITEDGE0_TRSTN_MASK 0x40000000 +#define GC_PINMUX_EXITEDGE0_TRSTN_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_TRSTN_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_TRSTN_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_TDI_LSB 0x1f +#define GC_PINMUX_EXITEDGE0_TDI_MASK 0x80000000 +#define GC_PINMUX_EXITEDGE0_TDI_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_TDI_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_TDI_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE1_TMS_LSB 0x0 +#define GC_PINMUX_EXITEDGE1_TMS_MASK 0x1 +#define GC_PINMUX_EXITEDGE1_TMS_SIZE 0x1 +#define GC_PINMUX_EXITEDGE1_TMS_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_TMS_OFFSET 0x26c +#define GC_PINMUX_EXITEDGE1_TCK_LSB 0x1 +#define GC_PINMUX_EXITEDGE1_TCK_MASK 0x2 +#define GC_PINMUX_EXITEDGE1_TCK_SIZE 0x1 +#define GC_PINMUX_EXITEDGE1_TCK_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_TCK_OFFSET 0x26c +#define GC_PINMUX_EXITEDGE1_TDO_LSB 0x2 +#define GC_PINMUX_EXITEDGE1_TDO_MASK 0x4 +#define GC_PINMUX_EXITEDGE1_TDO_SIZE 0x1 +#define GC_PINMUX_EXITEDGE1_TDO_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_TDO_OFFSET 0x26c +#define GC_PINMUX_EXITEDGE1_VIO0_LSB 0x3 +#define GC_PINMUX_EXITEDGE1_VIO0_MASK 0x8 #define GC_PINMUX_EXITEDGE1_VIO0_SIZE 0x1 #define GC_PINMUX_EXITEDGE1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_VIO0_OFFSET 0x2ec -#define GC_PINMUX_EXITEDGE1_VIO1_LSB 0x13 -#define GC_PINMUX_EXITEDGE1_VIO1_MASK 0x80000 +#define GC_PINMUX_EXITEDGE1_VIO0_OFFSET 0x26c +#define GC_PINMUX_EXITEDGE1_VIO1_LSB 0x4 +#define GC_PINMUX_EXITEDGE1_VIO1_MASK 0x10 #define GC_PINMUX_EXITEDGE1_VIO1_SIZE 0x1 #define GC_PINMUX_EXITEDGE1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_VIO1_OFFSET 0x2ec -#define GC_PINMUX_EXITEDGE1_TDO_LSB 0x17 -#define GC_PINMUX_EXITEDGE1_TDO_MASK 0x800000 -#define GC_PINMUX_EXITEDGE1_TDO_SIZE 0x1 -#define GC_PINMUX_EXITEDGE1_TDO_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_TDO_OFFSET 0x2ec +#define GC_PINMUX_EXITEDGE1_VIO1_OFFSET 0x26c #define GC_PINMUX_EXITINV0_DIOM0_LSB 0x0 #define GC_PINMUX_EXITINV0_DIOM0_MASK 0x1 #define GC_PINMUX_EXITINV0_DIOM0_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM0_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOM0_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOM1_LSB 0x1 #define GC_PINMUX_EXITINV0_DIOM1_MASK 0x2 #define GC_PINMUX_EXITINV0_DIOM1_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM1_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOM1_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOM2_LSB 0x2 #define GC_PINMUX_EXITINV0_DIOM2_MASK 0x4 #define GC_PINMUX_EXITINV0_DIOM2_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM2_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOM2_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOM3_LSB 0x3 #define GC_PINMUX_EXITINV0_DIOM3_MASK 0x8 #define GC_PINMUX_EXITINV0_DIOM3_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM3_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOM3_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOM4_LSB 0x4 #define GC_PINMUX_EXITINV0_DIOM4_MASK 0x10 #define GC_PINMUX_EXITINV0_DIOM4_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM4_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOM4_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA0_LSB 0x5 #define GC_PINMUX_EXITINV0_DIOA0_MASK 0x20 #define GC_PINMUX_EXITINV0_DIOA0_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA0_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA0_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA1_LSB 0x6 #define GC_PINMUX_EXITINV0_DIOA1_MASK 0x40 #define GC_PINMUX_EXITINV0_DIOA1_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA1_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA1_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA2_LSB 0x7 #define GC_PINMUX_EXITINV0_DIOA2_MASK 0x80 #define GC_PINMUX_EXITINV0_DIOA2_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA2_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA2_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA3_LSB 0x8 #define GC_PINMUX_EXITINV0_DIOA3_MASK 0x100 #define GC_PINMUX_EXITINV0_DIOA3_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA3_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA3_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA4_LSB 0x9 #define GC_PINMUX_EXITINV0_DIOA4_MASK 0x200 #define GC_PINMUX_EXITINV0_DIOA4_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA4_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA4_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA5_LSB 0xa #define GC_PINMUX_EXITINV0_DIOA5_MASK 0x400 #define GC_PINMUX_EXITINV0_DIOA5_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA5_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA5_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA6_LSB 0xb #define GC_PINMUX_EXITINV0_DIOA6_MASK 0x800 #define GC_PINMUX_EXITINV0_DIOA6_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA6_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA6_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA7_LSB 0xc #define GC_PINMUX_EXITINV0_DIOA7_MASK 0x1000 #define GC_PINMUX_EXITINV0_DIOA7_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA7_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA7_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA8_LSB 0xd #define GC_PINMUX_EXITINV0_DIOA8_MASK 0x2000 #define GC_PINMUX_EXITINV0_DIOA8_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA8_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA8_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA9_LSB 0xe #define GC_PINMUX_EXITINV0_DIOA9_MASK 0x4000 #define GC_PINMUX_EXITINV0_DIOA9_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA9_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA9_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA10_LSB 0xf #define GC_PINMUX_EXITINV0_DIOA10_MASK 0x8000 #define GC_PINMUX_EXITINV0_DIOA10_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA10_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA10_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA11_LSB 0x10 #define GC_PINMUX_EXITINV0_DIOA11_MASK 0x10000 #define GC_PINMUX_EXITINV0_DIOA11_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA11_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA11_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA12_LSB 0x11 #define GC_PINMUX_EXITINV0_DIOA12_MASK 0x20000 #define GC_PINMUX_EXITINV0_DIOA12_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA12_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA12_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA13_LSB 0x12 #define GC_PINMUX_EXITINV0_DIOA13_MASK 0x40000 #define GC_PINMUX_EXITINV0_DIOA13_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA13_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA13_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOA14_LSB 0x13 #define GC_PINMUX_EXITINV0_DIOA14_MASK 0x80000 #define GC_PINMUX_EXITINV0_DIOA14_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA14_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA14_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOB0_LSB 0x14 #define GC_PINMUX_EXITINV0_DIOB0_MASK 0x100000 #define GC_PINMUX_EXITINV0_DIOB0_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB0_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB0_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOB1_LSB 0x15 #define GC_PINMUX_EXITINV0_DIOB1_MASK 0x200000 #define GC_PINMUX_EXITINV0_DIOB1_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB1_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB1_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOB2_LSB 0x16 #define GC_PINMUX_EXITINV0_DIOB2_MASK 0x400000 #define GC_PINMUX_EXITINV0_DIOB2_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB2_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB2_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOB3_LSB 0x17 #define GC_PINMUX_EXITINV0_DIOB3_MASK 0x800000 #define GC_PINMUX_EXITINV0_DIOB3_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB3_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB3_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOB4_LSB 0x18 #define GC_PINMUX_EXITINV0_DIOB4_MASK 0x1000000 #define GC_PINMUX_EXITINV0_DIOB4_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB4_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB4_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOB5_LSB 0x19 #define GC_PINMUX_EXITINV0_DIOB5_MASK 0x2000000 #define GC_PINMUX_EXITINV0_DIOB5_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB5_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB5_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOB6_LSB 0x1a #define GC_PINMUX_EXITINV0_DIOB6_MASK 0x4000000 #define GC_PINMUX_EXITINV0_DIOB6_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB6_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB6_OFFSET 0x270 #define GC_PINMUX_EXITINV0_DIOB7_LSB 0x1b #define GC_PINMUX_EXITINV0_DIOB7_MASK 0x8000000 #define GC_PINMUX_EXITINV0_DIOB7_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB7_OFFSET 0x2f0 -#define GC_PINMUX_EXITINV0_DIOB8_LSB 0x1c -#define GC_PINMUX_EXITINV0_DIOB8_MASK 0x10000000 -#define GC_PINMUX_EXITINV0_DIOB8_SIZE 0x1 -#define GC_PINMUX_EXITINV0_DIOB8_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB8_OFFSET 0x2f0 -#define GC_PINMUX_EXITINV1_RTCXOP_LSB 0xc -#define GC_PINMUX_EXITINV1_RTCXOP_MASK 0x1000 -#define GC_PINMUX_EXITINV1_RTCXOP_SIZE 0x1 -#define GC_PINMUX_EXITINV1_RTCXOP_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_RTCXOP_OFFSET 0x2f4 -#define GC_PINMUX_EXITINV1_SWDPTRACE_LSB 0xd -#define GC_PINMUX_EXITINV1_SWDPTRACE_MASK 0x2000 -#define GC_PINMUX_EXITINV1_SWDPTRACE_SIZE 0x1 -#define GC_PINMUX_EXITINV1_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_SWDPTRACE_OFFSET 0x2f4 -#define GC_PINMUX_EXITINV1_SWDPDATA_LSB 0xe -#define GC_PINMUX_EXITINV1_SWDPDATA_MASK 0x4000 -#define GC_PINMUX_EXITINV1_SWDPDATA_SIZE 0x1 -#define GC_PINMUX_EXITINV1_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_SWDPDATA_OFFSET 0x2f4 -#define GC_PINMUX_EXITINV1_VIO0_LSB 0x12 -#define GC_PINMUX_EXITINV1_VIO0_MASK 0x40000 +#define GC_PINMUX_EXITINV0_DIOB7_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_SWDPTRACE_LSB 0x1c +#define GC_PINMUX_EXITINV0_SWDPTRACE_MASK 0x10000000 +#define GC_PINMUX_EXITINV0_SWDPTRACE_SIZE 0x1 +#define GC_PINMUX_EXITINV0_SWDPTRACE_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_SWDPTRACE_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_SWDPDATA_LSB 0x1d +#define GC_PINMUX_EXITINV0_SWDPDATA_MASK 0x20000000 +#define GC_PINMUX_EXITINV0_SWDPDATA_SIZE 0x1 +#define GC_PINMUX_EXITINV0_SWDPDATA_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_SWDPDATA_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_TRSTN_LSB 0x1e +#define GC_PINMUX_EXITINV0_TRSTN_MASK 0x40000000 +#define GC_PINMUX_EXITINV0_TRSTN_SIZE 0x1 +#define GC_PINMUX_EXITINV0_TRSTN_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_TRSTN_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_TDI_LSB 0x1f +#define GC_PINMUX_EXITINV0_TDI_MASK 0x80000000 +#define GC_PINMUX_EXITINV0_TDI_SIZE 0x1 +#define GC_PINMUX_EXITINV0_TDI_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_TDI_OFFSET 0x270 +#define GC_PINMUX_EXITINV1_TMS_LSB 0x0 +#define GC_PINMUX_EXITINV1_TMS_MASK 0x1 +#define GC_PINMUX_EXITINV1_TMS_SIZE 0x1 +#define GC_PINMUX_EXITINV1_TMS_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_TMS_OFFSET 0x274 +#define GC_PINMUX_EXITINV1_TCK_LSB 0x1 +#define GC_PINMUX_EXITINV1_TCK_MASK 0x2 +#define GC_PINMUX_EXITINV1_TCK_SIZE 0x1 +#define GC_PINMUX_EXITINV1_TCK_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_TCK_OFFSET 0x274 +#define GC_PINMUX_EXITINV1_TDO_LSB 0x2 +#define GC_PINMUX_EXITINV1_TDO_MASK 0x4 +#define GC_PINMUX_EXITINV1_TDO_SIZE 0x1 +#define GC_PINMUX_EXITINV1_TDO_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_TDO_OFFSET 0x274 +#define GC_PINMUX_EXITINV1_VIO0_LSB 0x3 +#define GC_PINMUX_EXITINV1_VIO0_MASK 0x8 #define GC_PINMUX_EXITINV1_VIO0_SIZE 0x1 #define GC_PINMUX_EXITINV1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_VIO0_OFFSET 0x2f4 -#define GC_PINMUX_EXITINV1_VIO1_LSB 0x13 -#define GC_PINMUX_EXITINV1_VIO1_MASK 0x80000 +#define GC_PINMUX_EXITINV1_VIO0_OFFSET 0x274 +#define GC_PINMUX_EXITINV1_VIO1_LSB 0x4 +#define GC_PINMUX_EXITINV1_VIO1_MASK 0x10 #define GC_PINMUX_EXITINV1_VIO1_SIZE 0x1 #define GC_PINMUX_EXITINV1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_VIO1_OFFSET 0x2f4 -#define GC_PINMUX_EXITINV1_TDO_LSB 0x17 -#define GC_PINMUX_EXITINV1_TDO_MASK 0x800000 -#define GC_PINMUX_EXITINV1_TDO_SIZE 0x1 -#define GC_PINMUX_EXITINV1_TDO_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_TDO_OFFSET 0x2f4 +#define GC_PINMUX_EXITINV1_VIO1_OFFSET 0x274 #define GC_PMU_RESET_PORESETB1_LSB 0x0 #define GC_PMU_RESET_PORESETB1_MASK 0x1 #define GC_PMU_RESET_PORESETB1_SIZE 0x1 @@ -7354,341 +11891,156 @@ #define GC_PMU_RSTSRC_POR_SIZE 0x1 #define GC_PMU_RSTSRC_POR_DEFAULT 0x0 #define GC_PMU_RSTSRC_POR_OFFSET 0xc -#define GC_PMU_RSTSRC_RESETB_LSB 0x1 -#define GC_PMU_RSTSRC_RESETB_MASK 0x2 -#define GC_PMU_RSTSRC_RESETB_SIZE 0x1 -#define GC_PMU_RSTSRC_RESETB_DEFAULT 0x0 -#define GC_PMU_RSTSRC_RESETB_OFFSET 0xc -#define GC_PMU_RSTSRC_EXIT_LSB 0x2 -#define GC_PMU_RSTSRC_EXIT_MASK 0x4 +#define GC_PMU_RSTSRC_EXIT_LSB 0x1 +#define GC_PMU_RSTSRC_EXIT_MASK 0x2 #define GC_PMU_RSTSRC_EXIT_SIZE 0x1 #define GC_PMU_RSTSRC_EXIT_DEFAULT 0x0 #define GC_PMU_RSTSRC_EXIT_OFFSET 0xc -#define GC_PMU_RSTSRC_WDOG_LSB 0x3 -#define GC_PMU_RSTSRC_WDOG_MASK 0x8 +#define GC_PMU_RSTSRC_WDOG_LSB 0x2 +#define GC_PMU_RSTSRC_WDOG_MASK 0x4 #define GC_PMU_RSTSRC_WDOG_SIZE 0x1 #define GC_PMU_RSTSRC_WDOG_DEFAULT 0x0 #define GC_PMU_RSTSRC_WDOG_OFFSET 0xc -#define GC_PMU_RSTSRC_LOCKUP_LSB 0x4 -#define GC_PMU_RSTSRC_LOCKUP_MASK 0x10 +#define GC_PMU_RSTSRC_LOCKUP_LSB 0x3 +#define GC_PMU_RSTSRC_LOCKUP_MASK 0x8 #define GC_PMU_RSTSRC_LOCKUP_SIZE 0x1 #define GC_PMU_RSTSRC_LOCKUP_DEFAULT 0x0 #define GC_PMU_RSTSRC_LOCKUP_OFFSET 0xc -#define GC_PMU_RSTSRC_SYSRESET_LSB 0x5 -#define GC_PMU_RSTSRC_SYSRESET_MASK 0x20 +#define GC_PMU_RSTSRC_SYSRESET_LSB 0x4 +#define GC_PMU_RSTSRC_SYSRESET_MASK 0x10 #define GC_PMU_RSTSRC_SYSRESET_SIZE 0x1 #define GC_PMU_RSTSRC_SYSRESET_DEFAULT 0x0 #define GC_PMU_RSTSRC_SYSRESET_OFFSET 0xc -#define GC_PMU_RSTSRC_SOFTWARE_LSB 0x6 -#define GC_PMU_RSTSRC_SOFTWARE_MASK 0x40 +#define GC_PMU_RSTSRC_SOFTWARE_LSB 0x5 +#define GC_PMU_RSTSRC_SOFTWARE_MASK 0x20 #define GC_PMU_RSTSRC_SOFTWARE_SIZE 0x1 #define GC_PMU_RSTSRC_SOFTWARE_DEFAULT 0x0 #define GC_PMU_RSTSRC_SOFTWARE_OFFSET 0xc -#define GC_PMU_RSTSRC_FST_BRNOUT_LSB 0x7 -#define GC_PMU_RSTSRC_FST_BRNOUT_MASK 0x80 +#define GC_PMU_RSTSRC_FST_BRNOUT_LSB 0x6 +#define GC_PMU_RSTSRC_FST_BRNOUT_MASK 0x40 #define GC_PMU_RSTSRC_FST_BRNOUT_SIZE 0x1 #define GC_PMU_RSTSRC_FST_BRNOUT_DEFAULT 0x0 #define GC_PMU_RSTSRC_FST_BRNOUT_OFFSET 0xc -#define GC_PMU_SETDIS_START_LSB 0x0 -#define GC_PMU_SETDIS_START_MASK 0x1 -#define GC_PMU_SETDIS_START_SIZE 0x1 -#define GC_PMU_SETDIS_START_DEFAULT 0x0 -#define GC_PMU_SETDIS_START_OFFSET 0x14 -#define GC_PMU_SETDIS_VDDL_LSB 0x1 -#define GC_PMU_SETDIS_VDDL_MASK 0x2 -#define GC_PMU_SETDIS_VDDL_SIZE 0x1 -#define GC_PMU_SETDIS_VDDL_DEFAULT 0x0 -#define GC_PMU_SETDIS_VDDL_OFFSET 0x14 -#define GC_PMU_SETDIS_VDDA_LSB 0x2 -#define GC_PMU_SETDIS_VDDA_MASK 0x4 -#define GC_PMU_SETDIS_VDDA_SIZE 0x1 -#define GC_PMU_SETDIS_VDDA_DEFAULT 0x0 -#define GC_PMU_SETDIS_VDDA_OFFSET 0x14 -#define GC_PMU_SETDIS_VDDSRM_LSB 0x3 -#define GC_PMU_SETDIS_VDDSRM_MASK 0x8 -#define GC_PMU_SETDIS_VDDSRM_SIZE 0x1 -#define GC_PMU_SETDIS_VDDSRM_DEFAULT 0x0 -#define GC_PMU_SETDIS_VDDSRM_OFFSET 0x14 -#define GC_PMU_SETDIS_VDDIOF_LSB 0x4 -#define GC_PMU_SETDIS_VDDIOF_MASK 0x10 -#define GC_PMU_SETDIS_VDDIOF_SIZE 0x1 -#define GC_PMU_SETDIS_VDDIOF_DEFAULT 0x0 -#define GC_PMU_SETDIS_VDDIOF_OFFSET 0x14 -#define GC_PMU_SETDIS_VDDLK_LSB 0x5 -#define GC_PMU_SETDIS_VDDLK_MASK 0x20 -#define GC_PMU_SETDIS_VDDLK_SIZE 0x1 -#define GC_PMU_SETDIS_VDDLK_DEFAULT 0x0 -#define GC_PMU_SETDIS_VDDLK_OFFSET 0x14 -#define GC_PMU_SETDIS_VDDSK_LSB 0x6 -#define GC_PMU_SETDIS_VDDSK_MASK 0x40 -#define GC_PMU_SETDIS_VDDSK_SIZE 0x1 -#define GC_PMU_SETDIS_VDDSK_DEFAULT 0x0 -#define GC_PMU_SETDIS_VDDSK_OFFSET 0x14 -#define GC_PMU_SETDIS_VDDSRK_LSB 0x7 -#define GC_PMU_SETDIS_VDDSRK_MASK 0x80 -#define GC_PMU_SETDIS_VDDSRK_SIZE 0x1 -#define GC_PMU_SETDIS_VDDSRK_DEFAULT 0x0 -#define GC_PMU_SETDIS_VDDSRK_OFFSET 0x14 -#define GC_PMU_SETDIS_RETCOMPREF_LSB 0x8 -#define GC_PMU_SETDIS_RETCOMPREF_MASK 0x100 -#define GC_PMU_SETDIS_RETCOMPREF_SIZE 0x1 -#define GC_PMU_SETDIS_RETCOMPREF_DEFAULT 0x0 -#define GC_PMU_SETDIS_RETCOMPREF_OFFSET 0x14 -#define GC_PMU_SETDIS_BIAS_LSB 0x9 -#define GC_PMU_SETDIS_BIAS_MASK 0x200 -#define GC_PMU_SETDIS_BIAS_SIZE 0x1 -#define GC_PMU_SETDIS_BIAS_DEFAULT 0x0 -#define GC_PMU_SETDIS_BIAS_OFFSET 0x14 -#define GC_PMU_SETDIS_BGAP_LSB 0xa -#define GC_PMU_SETDIS_BGAP_MASK 0x400 -#define GC_PMU_SETDIS_BGAP_SIZE 0x1 -#define GC_PMU_SETDIS_BGAP_DEFAULT 0x0 -#define GC_PMU_SETDIS_BGAP_OFFSET 0x14 -#define GC_PMU_SETDIS_VDDXO_LSB 0xb -#define GC_PMU_SETDIS_VDDXO_MASK 0x800 -#define GC_PMU_SETDIS_VDDXO_SIZE 0x1 -#define GC_PMU_SETDIS_VDDXO_DEFAULT 0x0 -#define GC_PMU_SETDIS_VDDXO_OFFSET 0x14 -#define GC_PMU_SETDIS_VDDXOLP_LSB 0xc -#define GC_PMU_SETDIS_VDDXOLP_MASK 0x1000 -#define GC_PMU_SETDIS_VDDXOLP_SIZE 0x1 -#define GC_PMU_SETDIS_VDDXOLP_DEFAULT 0x0 -#define GC_PMU_SETDIS_VDDXOLP_OFFSET 0x14 -#define GC_PMU_SETDIS_SEL_VDDXOLP_LSB 0xd -#define GC_PMU_SETDIS_SEL_VDDXOLP_MASK 0x2000 -#define GC_PMU_SETDIS_SEL_VDDXOLP_SIZE 0x1 -#define GC_PMU_SETDIS_SEL_VDDXOLP_DEFAULT 0x0 -#define GC_PMU_SETDIS_SEL_VDDXOLP_OFFSET 0x14 -#define GC_PMU_SETDIS_XTL_LSB 0xe -#define GC_PMU_SETDIS_XTL_MASK 0x4000 -#define GC_PMU_SETDIS_XTL_SIZE 0x1 -#define GC_PMU_SETDIS_XTL_DEFAULT 0x0 -#define GC_PMU_SETDIS_XTL_OFFSET 0x14 -#define GC_PMU_SETDIS_RC_TRIM_LSB 0xf -#define GC_PMU_SETDIS_RC_TRIM_MASK 0x8000 -#define GC_PMU_SETDIS_RC_TRIM_SIZE 0x1 -#define GC_PMU_SETDIS_RC_TRIM_DEFAULT 0x0 -#define GC_PMU_SETDIS_RC_TRIM_OFFSET 0x14 -#define GC_PMU_SETDIS_RC_NOTRIM_LSB 0x10 -#define GC_PMU_SETDIS_RC_NOTRIM_MASK 0x10000 -#define GC_PMU_SETDIS_RC_NOTRIM_SIZE 0x1 -#define GC_PMU_SETDIS_RC_NOTRIM_DEFAULT 0x0 -#define GC_PMU_SETDIS_RC_NOTRIM_OFFSET 0x14 -#define GC_PMU_SETDIS_BATMON_LSB 0x11 -#define GC_PMU_SETDIS_BATMON_MASK 0x20000 -#define GC_PMU_SETDIS_BATMON_SIZE 0x1 -#define GC_PMU_SETDIS_BATMON_DEFAULT 0x0 -#define GC_PMU_SETDIS_BATMON_OFFSET 0x14 -#define GC_PMU_SETDIS_FST_BRNOUT_PWR_LSB 0x12 -#define GC_PMU_SETDIS_FST_BRNOUT_PWR_MASK 0x40000 -#define GC_PMU_SETDIS_FST_BRNOUT_PWR_SIZE 0x1 -#define GC_PMU_SETDIS_FST_BRNOUT_PWR_DEFAULT 0x0 -#define GC_PMU_SETDIS_FST_BRNOUT_PWR_OFFSET 0x14 -#define GC_PMU_SETDIS_FST_BRNOUT_LSB 0x13 -#define GC_PMU_SETDIS_FST_BRNOUT_MASK 0x80000 -#define GC_PMU_SETDIS_FST_BRNOUT_SIZE 0x1 -#define GC_PMU_SETDIS_FST_BRNOUT_DEFAULT 0x0 -#define GC_PMU_SETDIS_FST_BRNOUT_OFFSET 0x14 -#define GC_PMU_CLRDIS_START_LSB 0x0 -#define GC_PMU_CLRDIS_START_MASK 0x1 -#define GC_PMU_CLRDIS_START_SIZE 0x1 -#define GC_PMU_CLRDIS_START_DEFAULT 0x0 -#define GC_PMU_CLRDIS_START_OFFSET 0x18 -#define GC_PMU_CLRDIS_VDDL_LSB 0x1 -#define GC_PMU_CLRDIS_VDDL_MASK 0x2 -#define GC_PMU_CLRDIS_VDDL_SIZE 0x1 -#define GC_PMU_CLRDIS_VDDL_DEFAULT 0x0 -#define GC_PMU_CLRDIS_VDDL_OFFSET 0x18 -#define GC_PMU_CLRDIS_VDDA_LSB 0x2 -#define GC_PMU_CLRDIS_VDDA_MASK 0x4 -#define GC_PMU_CLRDIS_VDDA_SIZE 0x1 -#define GC_PMU_CLRDIS_VDDA_DEFAULT 0x0 -#define GC_PMU_CLRDIS_VDDA_OFFSET 0x18 -#define GC_PMU_CLRDIS_VDDSRM_LSB 0x3 -#define GC_PMU_CLRDIS_VDDSRM_MASK 0x8 -#define GC_PMU_CLRDIS_VDDSRM_SIZE 0x1 -#define GC_PMU_CLRDIS_VDDSRM_DEFAULT 0x0 -#define GC_PMU_CLRDIS_VDDSRM_OFFSET 0x18 -#define GC_PMU_CLRDIS_VDDIOF_LSB 0x4 -#define GC_PMU_CLRDIS_VDDIOF_MASK 0x10 -#define GC_PMU_CLRDIS_VDDIOF_SIZE 0x1 -#define GC_PMU_CLRDIS_VDDIOF_DEFAULT 0x0 -#define GC_PMU_CLRDIS_VDDIOF_OFFSET 0x18 -#define GC_PMU_CLRDIS_VDDLK_LSB 0x5 -#define GC_PMU_CLRDIS_VDDLK_MASK 0x20 -#define GC_PMU_CLRDIS_VDDLK_SIZE 0x1 -#define GC_PMU_CLRDIS_VDDLK_DEFAULT 0x0 -#define GC_PMU_CLRDIS_VDDLK_OFFSET 0x18 -#define GC_PMU_CLRDIS_VDDSK_LSB 0x6 -#define GC_PMU_CLRDIS_VDDSK_MASK 0x40 -#define GC_PMU_CLRDIS_VDDSK_SIZE 0x1 -#define GC_PMU_CLRDIS_VDDSK_DEFAULT 0x0 -#define GC_PMU_CLRDIS_VDDSK_OFFSET 0x18 -#define GC_PMU_CLRDIS_VDDSRK_LSB 0x7 -#define GC_PMU_CLRDIS_VDDSRK_MASK 0x80 -#define GC_PMU_CLRDIS_VDDSRK_SIZE 0x1 -#define GC_PMU_CLRDIS_VDDSRK_DEFAULT 0x0 -#define GC_PMU_CLRDIS_VDDSRK_OFFSET 0x18 -#define GC_PMU_CLRDIS_RETCOMPREF_LSB 0x8 -#define GC_PMU_CLRDIS_RETCOMPREF_MASK 0x100 -#define GC_PMU_CLRDIS_RETCOMPREF_SIZE 0x1 -#define GC_PMU_CLRDIS_RETCOMPREF_DEFAULT 0x0 -#define GC_PMU_CLRDIS_RETCOMPREF_OFFSET 0x18 -#define GC_PMU_CLRDIS_BIAS_LSB 0x9 -#define GC_PMU_CLRDIS_BIAS_MASK 0x200 -#define GC_PMU_CLRDIS_BIAS_SIZE 0x1 -#define GC_PMU_CLRDIS_BIAS_DEFAULT 0x0 -#define GC_PMU_CLRDIS_BIAS_OFFSET 0x18 -#define GC_PMU_CLRDIS_BGAP_LSB 0xa -#define GC_PMU_CLRDIS_BGAP_MASK 0x400 -#define GC_PMU_CLRDIS_BGAP_SIZE 0x1 -#define GC_PMU_CLRDIS_BGAP_DEFAULT 0x0 -#define GC_PMU_CLRDIS_BGAP_OFFSET 0x18 -#define GC_PMU_CLRDIS_VDDXO_LSB 0xb -#define GC_PMU_CLRDIS_VDDXO_MASK 0x800 -#define GC_PMU_CLRDIS_VDDXO_SIZE 0x1 -#define GC_PMU_CLRDIS_VDDXO_DEFAULT 0x0 -#define GC_PMU_CLRDIS_VDDXO_OFFSET 0x18 -#define GC_PMU_CLRDIS_VDDXOLP_LSB 0xc -#define GC_PMU_CLRDIS_VDDXOLP_MASK 0x1000 -#define GC_PMU_CLRDIS_VDDXOLP_SIZE 0x1 -#define GC_PMU_CLRDIS_VDDXOLP_DEFAULT 0x0 -#define GC_PMU_CLRDIS_VDDXOLP_OFFSET 0x18 -#define GC_PMU_CLRDIS_SEL_VDDXOLP_LSB 0xd -#define GC_PMU_CLRDIS_SEL_VDDXOLP_MASK 0x2000 -#define GC_PMU_CLRDIS_SEL_VDDXOLP_SIZE 0x1 -#define GC_PMU_CLRDIS_SEL_VDDXOLP_DEFAULT 0x0 -#define GC_PMU_CLRDIS_SEL_VDDXOLP_OFFSET 0x18 -#define GC_PMU_CLRDIS_XTL_LSB 0xe -#define GC_PMU_CLRDIS_XTL_MASK 0x4000 -#define GC_PMU_CLRDIS_XTL_SIZE 0x1 -#define GC_PMU_CLRDIS_XTL_DEFAULT 0x0 -#define GC_PMU_CLRDIS_XTL_OFFSET 0x18 -#define GC_PMU_CLRDIS_RC_TRIM_LSB 0xf -#define GC_PMU_CLRDIS_RC_TRIM_MASK 0x8000 -#define GC_PMU_CLRDIS_RC_TRIM_SIZE 0x1 -#define GC_PMU_CLRDIS_RC_TRIM_DEFAULT 0x0 -#define GC_PMU_CLRDIS_RC_TRIM_OFFSET 0x18 -#define GC_PMU_CLRDIS_RC_NOTRIM_LSB 0x10 -#define GC_PMU_CLRDIS_RC_NOTRIM_MASK 0x10000 -#define GC_PMU_CLRDIS_RC_NOTRIM_SIZE 0x1 -#define GC_PMU_CLRDIS_RC_NOTRIM_DEFAULT 0x0 -#define GC_PMU_CLRDIS_RC_NOTRIM_OFFSET 0x18 -#define GC_PMU_CLRDIS_BATMON_LSB 0x11 -#define GC_PMU_CLRDIS_BATMON_MASK 0x20000 -#define GC_PMU_CLRDIS_BATMON_SIZE 0x1 -#define GC_PMU_CLRDIS_BATMON_DEFAULT 0x0 -#define GC_PMU_CLRDIS_BATMON_OFFSET 0x18 -#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_LSB 0x12 -#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_MASK 0x40000 -#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_SIZE 0x1 -#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_DEFAULT 0x0 -#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_OFFSET 0x18 -#define GC_PMU_CLRDIS_FST_BRNOUT_LSB 0x13 -#define GC_PMU_CLRDIS_FST_BRNOUT_MASK 0x80000 -#define GC_PMU_CLRDIS_FST_BRNOUT_SIZE 0x1 -#define GC_PMU_CLRDIS_FST_BRNOUT_DEFAULT 0x0 -#define GC_PMU_CLRDIS_FST_BRNOUT_OFFSET 0x18 -#define GC_PMU_STATDIS_START_LSB 0x0 -#define GC_PMU_STATDIS_START_MASK 0x1 -#define GC_PMU_STATDIS_START_SIZE 0x1 -#define GC_PMU_STATDIS_START_DEFAULT 0x0 -#define GC_PMU_STATDIS_START_OFFSET 0x1c -#define GC_PMU_STATDIS_VDDL_LSB 0x1 -#define GC_PMU_STATDIS_VDDL_MASK 0x2 -#define GC_PMU_STATDIS_VDDL_SIZE 0x1 -#define GC_PMU_STATDIS_VDDL_DEFAULT 0x0 -#define GC_PMU_STATDIS_VDDL_OFFSET 0x1c -#define GC_PMU_STATDIS_VDDA_LSB 0x2 -#define GC_PMU_STATDIS_VDDA_MASK 0x4 -#define GC_PMU_STATDIS_VDDA_SIZE 0x1 -#define GC_PMU_STATDIS_VDDA_DEFAULT 0x0 -#define GC_PMU_STATDIS_VDDA_OFFSET 0x1c -#define GC_PMU_STATDIS_VDDSRM_LSB 0x3 -#define GC_PMU_STATDIS_VDDSRM_MASK 0x8 -#define GC_PMU_STATDIS_VDDSRM_SIZE 0x1 -#define GC_PMU_STATDIS_VDDSRM_DEFAULT 0x0 -#define GC_PMU_STATDIS_VDDSRM_OFFSET 0x1c -#define GC_PMU_STATDIS_VDDIOF_LSB 0x4 -#define GC_PMU_STATDIS_VDDIOF_MASK 0x10 -#define GC_PMU_STATDIS_VDDIOF_SIZE 0x1 -#define GC_PMU_STATDIS_VDDIOF_DEFAULT 0x0 -#define GC_PMU_STATDIS_VDDIOF_OFFSET 0x1c -#define GC_PMU_STATDIS_VDDLK_LSB 0x5 -#define GC_PMU_STATDIS_VDDLK_MASK 0x20 -#define GC_PMU_STATDIS_VDDLK_SIZE 0x1 -#define GC_PMU_STATDIS_VDDLK_DEFAULT 0x0 -#define GC_PMU_STATDIS_VDDLK_OFFSET 0x1c -#define GC_PMU_STATDIS_VDDSK_LSB 0x6 -#define GC_PMU_STATDIS_VDDSK_MASK 0x40 -#define GC_PMU_STATDIS_VDDSK_SIZE 0x1 -#define GC_PMU_STATDIS_VDDSK_DEFAULT 0x0 -#define GC_PMU_STATDIS_VDDSK_OFFSET 0x1c -#define GC_PMU_STATDIS_VDDSRK_LSB 0x7 -#define GC_PMU_STATDIS_VDDSRK_MASK 0x80 -#define GC_PMU_STATDIS_VDDSRK_SIZE 0x1 -#define GC_PMU_STATDIS_VDDSRK_DEFAULT 0x0 -#define GC_PMU_STATDIS_VDDSRK_OFFSET 0x1c -#define GC_PMU_STATDIS_RETCOMPREF_LSB 0x8 -#define GC_PMU_STATDIS_RETCOMPREF_MASK 0x100 -#define GC_PMU_STATDIS_RETCOMPREF_SIZE 0x1 -#define GC_PMU_STATDIS_RETCOMPREF_DEFAULT 0x0 -#define GC_PMU_STATDIS_RETCOMPREF_OFFSET 0x1c -#define GC_PMU_STATDIS_BIAS_LSB 0x9 -#define GC_PMU_STATDIS_BIAS_MASK 0x200 -#define GC_PMU_STATDIS_BIAS_SIZE 0x1 -#define GC_PMU_STATDIS_BIAS_DEFAULT 0x0 -#define GC_PMU_STATDIS_BIAS_OFFSET 0x1c -#define GC_PMU_STATDIS_BGAP_LSB 0xa -#define GC_PMU_STATDIS_BGAP_MASK 0x400 -#define GC_PMU_STATDIS_BGAP_SIZE 0x1 -#define GC_PMU_STATDIS_BGAP_DEFAULT 0x0 -#define GC_PMU_STATDIS_BGAP_OFFSET 0x1c -#define GC_PMU_STATDIS_VDDXO_LSB 0xb -#define GC_PMU_STATDIS_VDDXO_MASK 0x800 -#define GC_PMU_STATDIS_VDDXO_SIZE 0x1 -#define GC_PMU_STATDIS_VDDXO_DEFAULT 0x0 -#define GC_PMU_STATDIS_VDDXO_OFFSET 0x1c -#define GC_PMU_STATDIS_VDDXOLP_LSB 0xc -#define GC_PMU_STATDIS_VDDXOLP_MASK 0x1000 -#define GC_PMU_STATDIS_VDDXOLP_SIZE 0x1 -#define GC_PMU_STATDIS_VDDXOLP_DEFAULT 0x0 -#define GC_PMU_STATDIS_VDDXOLP_OFFSET 0x1c -#define GC_PMU_STATDIS_SEL_VDDXOLP_LSB 0xd -#define GC_PMU_STATDIS_SEL_VDDXOLP_MASK 0x2000 -#define GC_PMU_STATDIS_SEL_VDDXOLP_SIZE 0x1 -#define GC_PMU_STATDIS_SEL_VDDXOLP_DEFAULT 0x0 -#define GC_PMU_STATDIS_SEL_VDDXOLP_OFFSET 0x1c -#define GC_PMU_STATDIS_XTL_LSB 0xe -#define GC_PMU_STATDIS_XTL_MASK 0x4000 -#define GC_PMU_STATDIS_XTL_SIZE 0x1 -#define GC_PMU_STATDIS_XTL_DEFAULT 0x1 -#define GC_PMU_STATDIS_XTL_OFFSET 0x1c -#define GC_PMU_STATDIS_RC_TRIM_LSB 0xf -#define GC_PMU_STATDIS_RC_TRIM_MASK 0x8000 -#define GC_PMU_STATDIS_RC_TRIM_SIZE 0x1 -#define GC_PMU_STATDIS_RC_TRIM_DEFAULT 0x1 -#define GC_PMU_STATDIS_RC_TRIM_OFFSET 0x1c -#define GC_PMU_STATDIS_RC_NOTRIM_LSB 0x10 -#define GC_PMU_STATDIS_RC_NOTRIM_MASK 0x10000 -#define GC_PMU_STATDIS_RC_NOTRIM_SIZE 0x1 -#define GC_PMU_STATDIS_RC_NOTRIM_DEFAULT 0x0 -#define GC_PMU_STATDIS_RC_NOTRIM_OFFSET 0x1c -#define GC_PMU_STATDIS_BATMON_LSB 0x11 -#define GC_PMU_STATDIS_BATMON_MASK 0x20000 -#define GC_PMU_STATDIS_BATMON_SIZE 0x1 -#define GC_PMU_STATDIS_BATMON_DEFAULT 0x1 -#define GC_PMU_STATDIS_BATMON_OFFSET 0x1c -#define GC_PMU_STATDIS_FST_BRNOUT_PWR_LSB 0x12 -#define GC_PMU_STATDIS_FST_BRNOUT_PWR_MASK 0x40000 -#define GC_PMU_STATDIS_FST_BRNOUT_PWR_SIZE 0x1 -#define GC_PMU_STATDIS_FST_BRNOUT_PWR_DEFAULT 0x1 -#define GC_PMU_STATDIS_FST_BRNOUT_PWR_OFFSET 0x1c -#define GC_PMU_STATDIS_FST_BRNOUT_LSB 0x13 -#define GC_PMU_STATDIS_FST_BRNOUT_MASK 0x80000 -#define GC_PMU_STATDIS_FST_BRNOUT_SIZE 0x1 -#define GC_PMU_STATDIS_FST_BRNOUT_DEFAULT 0x1 -#define GC_PMU_STATDIS_FST_BRNOUT_OFFSET 0x1c +#define GC_PMU_RSTSRC_SEC_THREAT_LSB 0x7 +#define GC_PMU_RSTSRC_SEC_THREAT_MASK 0x80 +#define GC_PMU_RSTSRC_SEC_THREAT_SIZE 0x1 +#define GC_PMU_RSTSRC_SEC_THREAT_DEFAULT 0x0 +#define GC_PMU_RSTSRC_SEC_THREAT_OFFSET 0xc +#define GC_PMU_LOW_POWER_DIS_START_LSB 0x0 +#define GC_PMU_LOW_POWER_DIS_START_MASK 0x1 +#define GC_PMU_LOW_POWER_DIS_START_SIZE 0x1 +#define GC_PMU_LOW_POWER_DIS_START_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_DIS_START_OFFSET 0x14 +#define GC_PMU_LOW_POWER_DIS_VDDL_LSB 0x1 +#define GC_PMU_LOW_POWER_DIS_VDDL_MASK 0x2 +#define GC_PMU_LOW_POWER_DIS_VDDL_SIZE 0x1 +#define GC_PMU_LOW_POWER_DIS_VDDL_DEFAULT 0x1 +#define GC_PMU_LOW_POWER_DIS_VDDL_OFFSET 0x14 +#define GC_PMU_LOW_POWER_DIS_VDDIOF_LSB 0x2 +#define GC_PMU_LOW_POWER_DIS_VDDIOF_MASK 0x4 +#define GC_PMU_LOW_POWER_DIS_VDDIOF_SIZE 0x1 +#define GC_PMU_LOW_POWER_DIS_VDDIOF_DEFAULT 0x1 +#define GC_PMU_LOW_POWER_DIS_VDDIOF_OFFSET 0x14 +#define GC_PMU_LOW_POWER_DIS_VDDXO_LSB 0x3 +#define GC_PMU_LOW_POWER_DIS_VDDXO_MASK 0x8 +#define GC_PMU_LOW_POWER_DIS_VDDXO_SIZE 0x1 +#define GC_PMU_LOW_POWER_DIS_VDDXO_DEFAULT 0x1 +#define GC_PMU_LOW_POWER_DIS_VDDXO_OFFSET 0x14 +#define GC_PMU_LOW_POWER_DIS_JTR_RC_LSB 0x4 +#define GC_PMU_LOW_POWER_DIS_JTR_RC_MASK 0x10 +#define GC_PMU_LOW_POWER_DIS_JTR_RC_SIZE 0x1 +#define GC_PMU_LOW_POWER_DIS_JTR_RC_DEFAULT 0x1 +#define GC_PMU_LOW_POWER_DIS_JTR_RC_OFFSET 0x14 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_LSB 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_MASK 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_LSB 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_MASK 0x2 +#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_LSB 0x2 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_MASK 0x4 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_LSB 0x3 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_MASK 0x8 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_LSB 0x4 +#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_MASK 0x10 +#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_LSB 0x5 +#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_MASK 0x20 +#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_PDM25_LSB 0x6 +#define GC_PMU_LOW_POWER_BYPASS_PDM25_MASK 0x40 +#define GC_PMU_LOW_POWER_BYPASS_PDM25_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_PDM25_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_PDM25_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_LSB 0x7 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_MASK 0x80 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_LSB 0x8 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_MASK 0x100 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_OFFSET 0x18 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_LSB 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_MASK 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_OFFSET 0x1c +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_LSB 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_MASK 0x2 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_OFFSET 0x1c +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_LSB 0x2 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_MASK 0x4 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_OFFSET 0x1c +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_LSB 0x3 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_MASK 0x8 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_OFFSET 0x1c +#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_LSB 0x4 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_MASK 0x10 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_OFFSET 0x1c +#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_LSB 0x5 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_MASK 0x20 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_OFFSET 0x1c +#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_LSB 0x6 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_MASK 0x40 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_OFFSET 0x1c +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_LSB 0x7 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_MASK 0x80 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_OFFSET 0x1c +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_LSB 0x8 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_MASK 0x100 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_SIZE 0x1 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_DEFAULT 0x0 +#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_OFFSET 0x1c #define GC_PMU_SETWIC_PROC0_LSB 0x0 #define GC_PMU_SETWIC_PROC0_MASK 0x1 #define GC_PMU_SETWIC_PROC0_SIZE 0x1 @@ -7699,76 +12051,51 @@ #define GC_PMU_CLRWIC_PROC0_SIZE 0x1 #define GC_PMU_CLRWIC_PROC0_DEFAULT 0x0 #define GC_PMU_CLRWIC_PROC0_OFFSET 0x24 -#define GC_PMU_EXCLUSIVE_PROC0_LSB 0x0 -#define GC_PMU_EXCLUSIVE_PROC0_MASK 0x1 -#define GC_PMU_EXCLUSIVE_PROC0_SIZE 0x1 -#define GC_PMU_EXCLUSIVE_PROC0_DEFAULT 0x0 -#define GC_PMU_EXCLUSIVE_PROC0_OFFSET 0x2c -#define GC_PMUSETMODEL_FPGA_TRNG_LDO_PDB_3P3_LSB 0x0 -#define GC_PMUSETMODEL_FPGA_TRNG_LDO_PDB_3P3_MASK 0x1 -#define GC_PMUSETMODEL_FPGA_TRNG_LDO_PDB_3P3_SIZE 0x1 -#define GC_PMUSETMODEL_FPGA_TRNG_LDO_PDB_3P3_DEFAULT 0x0 -#define GC_PMUSETMODEL_FPGA_TRNG_LDO_PDB_3P3_OFFSET 0x44 -#define GC_PMUCLRMODEL_FPGA_TRNG_LDO_PDB_3P3_LSB 0x0 -#define GC_PMUCLRMODEL_FPGA_TRNG_LDO_PDB_3P3_MASK 0x1 -#define GC_PMUCLRMODEL_FPGA_TRNG_LDO_PDB_3P3_SIZE 0x1 -#define GC_PMUCLRMODEL_FPGA_TRNG_LDO_PDB_3P3_DEFAULT 0x0 -#define GC_PMUCLRMODEL_FPGA_TRNG_LDO_PDB_3P3_OFFSET 0x48 -#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_LSB 0x0 -#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_MASK 0x1 -#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_SIZE 0x1 -#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_DEFAULT 0x0 -#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_OFFSET 0x4c -#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_LSB 0x1 -#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_MASK 0x2 -#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_SIZE 0x1 -#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_DEFAULT 0x0 -#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_OFFSET 0x4c -#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_LSB 0x0 -#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_MASK 0x1 -#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_SIZE 0x1 -#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_DEFAULT 0x0 -#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_OFFSET 0x50 -#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_LSB 0x1 -#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_MASK 0x2 -#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_SIZE 0x1 -#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_DEFAULT 0x0 -#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_OFFSET 0x50 +#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_LSB 0x0 +#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_MASK 0x1 +#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_SIZE 0x1 +#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_DEFAULT 0x0 +#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_OFFSET 0x30 +#define GC_PMU_SW_PDB_TIMER_RC_LSB 0x0 +#define GC_PMU_SW_PDB_TIMER_RC_MASK 0x1 +#define GC_PMU_SW_PDB_TIMER_RC_SIZE 0x1 +#define GC_PMU_SW_PDB_TIMER_RC_DEFAULT 0x0 +#define GC_PMU_SW_PDB_TIMER_RC_OFFSET 0x34 +#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_LSB 0x1 +#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_MASK 0x2 +#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_SIZE 0x1 +#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_DEFAULT 0x0 +#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_OFFSET 0x34 +#define GC_PMU_SW_PDB_FST_BRNOUT_LSB 0x2 +#define GC_PMU_SW_PDB_FST_BRNOUT_MASK 0x4 +#define GC_PMU_SW_PDB_FST_BRNOUT_SIZE 0x1 +#define GC_PMU_SW_PDB_FST_BRNOUT_DEFAULT 0x0 +#define GC_PMU_SW_PDB_FST_BRNOUT_OFFSET 0x34 +#define GC_PMU_SW_PDB_SECURE_BATMON_LSB 0x0 +#define GC_PMU_SW_PDB_SECURE_BATMON_MASK 0x1 +#define GC_PMU_SW_PDB_SECURE_BATMON_SIZE 0x1 +#define GC_PMU_SW_PDB_SECURE_BATMON_DEFAULT 0x0 +#define GC_PMU_SW_PDB_SECURE_BATMON_OFFSET 0x38 +#define GC_PMU_SW_PDB_SECURE_XTL_LSB 0x1 +#define GC_PMU_SW_PDB_SECURE_XTL_MASK 0x2 +#define GC_PMU_SW_PDB_SECURE_XTL_SIZE 0x1 +#define GC_PMU_SW_PDB_SECURE_XTL_DEFAULT 0x0 +#define GC_PMU_SW_PDB_SECURE_XTL_OFFSET 0x38 #define GC_PMU_VREF_REG_LSB 0x0 #define GC_PMU_VREF_REG_MASK 0xf #define GC_PMU_VREF_REG_SIZE 0x4 -#define GC_PMU_VREF_REG_DEFAULT 0x8 -#define GC_PMU_VREF_REG_OFFSET 0x54 -#define GC_PMU_VREF_RET_LSB 0x4 -#define GC_PMU_VREF_RET_MASK 0xf0 -#define GC_PMU_VREF_RET_SIZE 0x4 -#define GC_PMU_VREF_RET_DEFAULT 0x8 -#define GC_PMU_VREF_RET_OFFSET 0x54 -#define GC_PMU_VREF_RLDOCTRL_LSB 0x8 -#define GC_PMU_VREF_RLDOCTRL_MASK 0xf00 -#define GC_PMU_VREF_RLDOCTRL_SIZE 0x4 -#define GC_PMU_VREF_RLDOCTRL_DEFAULT 0xf -#define GC_PMU_VREF_RLDOCTRL_OFFSET 0x54 -#define GC_PMU_VREF_RLDOLNA_LSB 0xc -#define GC_PMU_VREF_RLDOLNA_MASK 0xf000 -#define GC_PMU_VREF_RLDOLNA_SIZE 0x4 -#define GC_PMU_VREF_RLDOLNA_DEFAULT 0xf -#define GC_PMU_VREF_RLDOLNA_OFFSET 0x54 -#define GC_PMU_VREF_RLDOLO_LSB 0x10 -#define GC_PMU_VREF_RLDOLO_MASK 0xf0000 -#define GC_PMU_VREF_RLDOLO_SIZE 0x4 -#define GC_PMU_VREF_RLDOLO_DEFAULT 0xf -#define GC_PMU_VREF_RLDOLO_OFFSET 0x54 -#define GC_PMU_VREF_LDOXO_LSB 0x14 -#define GC_PMU_VREF_LDOXO_MASK 0xf00000 +#define GC_PMU_VREF_REG_DEFAULT 0xb +#define GC_PMU_VREF_REG_OFFSET 0x3c +#define GC_PMU_VREF_LDOXO_LSB 0x4 +#define GC_PMU_VREF_LDOXO_MASK 0xf0 #define GC_PMU_VREF_LDOXO_SIZE 0x4 #define GC_PMU_VREF_LDOXO_DEFAULT 0xf -#define GC_PMU_VREF_LDOXO_OFFSET 0x54 -#define GC_PMU_VREF_BATMON_LSB 0x18 -#define GC_PMU_VREF_BATMON_MASK 0x7000000 +#define GC_PMU_VREF_LDOXO_OFFSET 0x3c +#define GC_PMU_VREF_BATMON_LSB 0x8 +#define GC_PMU_VREF_BATMON_MASK 0x700 #define GC_PMU_VREF_BATMON_SIZE 0x3 #define GC_PMU_VREF_BATMON_DEFAULT 0x0 -#define GC_PMU_VREF_BATMON_OFFSET 0x54 +#define GC_PMU_VREF_BATMON_OFFSET 0x3c #define GC_PMU_VREF_BATMON_V1P9 0x2 #define GC_PMU_VREF_BATMON_V1P8 0x1 #define GC_PMU_VREF_BATMON_V1P7 0x0 @@ -7777,1516 +12104,1696 @@ #define GC_PMU_VREF_BATMON_V2P1 0x4 #define GC_PMU_VREF_BATMON_V2P2 0x5 #define GC_PMU_VREF_BATMON_V2P3 0x6 -#define GC_PMU_VREFCMP_CMP1_LSB 0x0 -#define GC_PMU_VREFCMP_CMP1_MASK 0x1f -#define GC_PMU_VREFCMP_CMP1_SIZE 0x5 -#define GC_PMU_VREFCMP_CMP1_DEFAULT 0x0 -#define GC_PMU_VREFCMP_CMP1_OFFSET 0x58 -#define GC_PMU_VREFCMP_CMP2_LSB 0x5 -#define GC_PMU_VREFCMP_CMP2_MASK 0x3e0 -#define GC_PMU_VREFCMP_CMP2_SIZE 0x5 -#define GC_PMU_VREFCMP_CMP2_DEFAULT 0x0 -#define GC_PMU_VREFCMP_CMP2_OFFSET 0x58 -#define GC_PMU_VREFCMP_VHYSTCMP1_LSB 0xa -#define GC_PMU_VREFCMP_VHYSTCMP1_MASK 0x1c00 -#define GC_PMU_VREFCMP_VHYSTCMP1_SIZE 0x3 -#define GC_PMU_VREFCMP_VHYSTCMP1_DEFAULT 0x0 -#define GC_PMU_VREFCMP_VHYSTCMP1_OFFSET 0x58 -#define GC_PMU_VREFCMP_VHYSTCMP2_LSB 0xd -#define GC_PMU_VREFCMP_VHYSTCMP2_MASK 0xe000 -#define GC_PMU_VREFCMP_VHYSTCMP2_SIZE 0x3 -#define GC_PMU_VREFCMP_VHYSTCMP2_DEFAULT 0x0 -#define GC_PMU_VREFCMP_VHYSTCMP2_OFFSET 0x58 -#define GC_PMU_RBIAS_CTRL_LSB 0x0 -#define GC_PMU_RBIAS_CTRL_MASK 0xff -#define GC_PMU_RBIAS_CTRL_SIZE 0x8 -#define GC_PMU_RBIAS_CTRL_DEFAULT 0x0 -#define GC_PMU_RBIAS_CTRL_OFFSET 0x5c -#define GC_PMU_RBIASLO_TUNEIR10ADC_LSB 0x0 -#define GC_PMU_RBIASLO_TUNEIR10ADC_MASK 0x3 -#define GC_PMU_RBIASLO_TUNEIR10ADC_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10ADC_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10ADC_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10ADC2_LSB 0x2 -#define GC_PMU_RBIASLO_TUNEIR10ADC2_MASK 0xc -#define GC_PMU_RBIASLO_TUNEIR10ADC2_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10ADC2_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10ADC2_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10ADC3_LSB 0x4 -#define GC_PMU_RBIASLO_TUNEIR10ADC3_MASK 0x30 -#define GC_PMU_RBIASLO_TUNEIR10ADC3_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10ADC3_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10ADC3_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_LSB 0x6 -#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_MASK 0xc0 -#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10ADC4_LSB 0x8 -#define GC_PMU_RBIASLO_TUNEIR10ADC4_MASK 0x300 -#define GC_PMU_RBIASLO_TUNEIR10ADC4_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10ADC4_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10ADC4_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10COMP_LSB 0xa -#define GC_PMU_RBIASLO_TUNEIR10COMP_MASK 0xc00 -#define GC_PMU_RBIASLO_TUNEIR10COMP_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10COMP_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10COMP_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10COMP2_LSB 0xc -#define GC_PMU_RBIASLO_TUNEIR10COMP2_MASK 0x3000 -#define GC_PMU_RBIASLO_TUNEIR10COMP2_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10COMP2_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10COMP2_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10REGXO_LSB 0xe -#define GC_PMU_RBIASLO_TUNEIR10REGXO_MASK 0xc000 -#define GC_PMU_RBIASLO_TUNEIR10REGXO_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10REGXO_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10REGXO_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_LSB 0x10 -#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_MASK 0x30000 -#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_LSB 0x12 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_MASK 0xc0000 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_LSB 0x14 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_MASK 0x300000 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10REGREF_LSB 0x16 -#define GC_PMU_RBIASLO_TUNEIR10REGREF_MASK 0xc00000 -#define GC_PMU_RBIASLO_TUNEIR10REGREF_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10REGREF_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10REGREF_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_LSB 0x18 -#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_MASK 0x3000000 -#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10REGLOG_LSB 0x1a -#define GC_PMU_RBIASLO_TUNEIR10REGLOG_MASK 0xc000000 -#define GC_PMU_RBIASLO_TUNEIR10REGLOG_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10REGLOG_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10REGLOG_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_LSB 0x1c -#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_MASK 0x30000000 -#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_OFFSET 0x60 -#define GC_PMU_RBIASLO_TUNEIR10REGLNA_LSB 0x1e -#define GC_PMU_RBIASLO_TUNEIR10REGLNA_MASK 0xc0000000 -#define GC_PMU_RBIASLO_TUNEIR10REGLNA_SIZE 0x2 -#define GC_PMU_RBIASLO_TUNEIR10REGLNA_DEFAULT 0x0 -#define GC_PMU_RBIASLO_TUNEIR10REGLNA_OFFSET 0x60 -#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_LSB 0x0 -#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_MASK 0x3 -#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_SIZE 0x2 -#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_DEFAULT 0x0 -#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_OFFSET 0x64 -#define GC_PMU_RBIASHI_TUNEIR10REGLO_LSB 0x2 -#define GC_PMU_RBIASHI_TUNEIR10REGLO_MASK 0xc -#define GC_PMU_RBIASHI_TUNEIR10REGLO_SIZE 0x2 -#define GC_PMU_RBIASHI_TUNEIR10REGLO_DEFAULT 0x0 -#define GC_PMU_RBIASHI_TUNEIR10REGLO_OFFSET 0x64 -#define GC_PMU_RBIASHI_TUNEIR10REGAREF_LSB 0x4 -#define GC_PMU_RBIASHI_TUNEIR10REGAREF_MASK 0x30 -#define GC_PMU_RBIASHI_TUNEIR10REGAREF_SIZE 0x2 -#define GC_PMU_RBIASHI_TUNEIR10REGAREF_DEFAULT 0x0 -#define GC_PMU_RBIASHI_TUNEIR10REGAREF_OFFSET 0x64 -#define GC_PMU_RBIASHI_TUNEIR10REGA_LSB 0x6 -#define GC_PMU_RBIASHI_TUNEIR10REGA_MASK 0xc0 -#define GC_PMU_RBIASHI_TUNEIR10REGA_SIZE 0x2 -#define GC_PMU_RBIASHI_TUNEIR10REGA_DEFAULT 0x0 -#define GC_PMU_RBIASHI_TUNEIR10REGA_OFFSET 0x64 -#define GC_PMU_RBIASHI_TUNEIR10REG6_LSB 0x8 -#define GC_PMU_RBIASHI_TUNEIR10REG6_MASK 0x300 -#define GC_PMU_RBIASHI_TUNEIR10REG6_SIZE 0x2 -#define GC_PMU_RBIASHI_TUNEIR10REG6_DEFAULT 0x0 -#define GC_PMU_RBIASHI_TUNEIR10REG6_OFFSET 0x64 -#define GC_PMU_RBIASHI_TUNEIR10REG7_LSB 0xa -#define GC_PMU_RBIASHI_TUNEIR10REG7_MASK 0xc00 -#define GC_PMU_RBIASHI_TUNEIR10REG7_SIZE 0x2 -#define GC_PMU_RBIASHI_TUNEIR10REG7_DEFAULT 0x0 -#define GC_PMU_RBIASHI_TUNEIR10REG7_OFFSET 0x64 -#define GC_PMU_RBIASHI_TUNEIR10REG8_LSB 0xc -#define GC_PMU_RBIASHI_TUNEIR10REG8_MASK 0x3000 -#define GC_PMU_RBIASHI_TUNEIR10REG8_SIZE 0x2 -#define GC_PMU_RBIASHI_TUNEIR10REG8_DEFAULT 0x0 -#define GC_PMU_RBIASHI_TUNEIR10REG8_OFFSET 0x64 -#define GC_PMU_RBIASHI_TUNEIR10REG9_LSB 0xe -#define GC_PMU_RBIASHI_TUNEIR10REG9_MASK 0xc000 -#define GC_PMU_RBIASHI_TUNEIR10REG9_SIZE 0x2 -#define GC_PMU_RBIASHI_TUNEIR10REG9_DEFAULT 0x0 -#define GC_PMU_RBIASHI_TUNEIR10REG9_OFFSET 0x64 -#define GC_PMU_RBIASHI_TUNEIR10OPAMP_LSB 0x10 -#define GC_PMU_RBIASHI_TUNEIR10OPAMP_MASK 0x30000 -#define GC_PMU_RBIASHI_TUNEIR10OPAMP_SIZE 0x2 -#define GC_PMU_RBIASHI_TUNEIR10OPAMP_DEFAULT 0x0 -#define GC_PMU_RBIASHI_TUNEIR10OPAMP_OFFSET 0x64 -#define GC_PMU_SETHOLDVREF_REG_LSB 0x0 -#define GC_PMU_SETHOLDVREF_REG_MASK 0x1 -#define GC_PMU_SETHOLDVREF_REG_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_REG_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_REG_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_RET_LSB 0x1 -#define GC_PMU_SETHOLDVREF_RET_MASK 0x2 -#define GC_PMU_SETHOLDVREF_RET_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_RET_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_RET_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_BIASCTRL_LSB 0x2 -#define GC_PMU_SETHOLDVREF_BIASCTRL_MASK 0x4 -#define GC_PMU_SETHOLDVREF_BIASCTRL_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_BIASCTRL_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_BIASCTRL_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_BIASTUNER_LSB 0x3 -#define GC_PMU_SETHOLDVREF_BIASTUNER_MASK 0x8 -#define GC_PMU_SETHOLDVREF_BIASTUNER_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_BIASTUNER_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_BIASTUNER_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_LDOLNA_LSB 0x4 -#define GC_PMU_SETHOLDVREF_LDOLNA_MASK 0x10 -#define GC_PMU_SETHOLDVREF_LDOLNA_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_LDOLNA_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_LDOLNA_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_LDOLO_LSB 0x5 -#define GC_PMU_SETHOLDVREF_LDOLO_MASK 0x20 -#define GC_PMU_SETHOLDVREF_LDOLO_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_LDOLO_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_LDOLO_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_LDOCTRL_LSB 0x6 -#define GC_PMU_SETHOLDVREF_LDOCTRL_MASK 0x40 -#define GC_PMU_SETHOLDVREF_LDOCTRL_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_LDOCTRL_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_LDOCTRL_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_LDOXO_LSB 0x7 -#define GC_PMU_SETHOLDVREF_LDOXO_MASK 0x80 -#define GC_PMU_SETHOLDVREF_LDOXO_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_LDOXO_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_LDOXO_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_BATMON_LSB 0x8 -#define GC_PMU_SETHOLDVREF_BATMON_MASK 0x100 -#define GC_PMU_SETHOLDVREF_BATMON_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_BATMON_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_BATMON_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_CMP1_LSB 0x9 -#define GC_PMU_SETHOLDVREF_CMP1_MASK 0x200 -#define GC_PMU_SETHOLDVREF_CMP1_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_CMP1_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_CMP1_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_CMP2_LSB 0xa -#define GC_PMU_SETHOLDVREF_CMP2_MASK 0x400 -#define GC_PMU_SETHOLDVREF_CMP2_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_CMP2_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_CMP2_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_VHYSTCMP1_LSB 0xb -#define GC_PMU_SETHOLDVREF_VHYSTCMP1_MASK 0x800 -#define GC_PMU_SETHOLDVREF_VHYSTCMP1_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_VHYSTCMP1_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_VHYSTCMP1_OFFSET 0x68 -#define GC_PMU_SETHOLDVREF_VHYSTCMP2_LSB 0xc -#define GC_PMU_SETHOLDVREF_VHYSTCMP2_MASK 0x1000 -#define GC_PMU_SETHOLDVREF_VHYSTCMP2_SIZE 0x1 -#define GC_PMU_SETHOLDVREF_VHYSTCMP2_DEFAULT 0x0 -#define GC_PMU_SETHOLDVREF_VHYSTCMP2_OFFSET 0x68 -#define GC_PMU_CLRHOLDVREF_REG_LSB 0x0 -#define GC_PMU_CLRHOLDVREF_REG_MASK 0x1 -#define GC_PMU_CLRHOLDVREF_REG_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_REG_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_REG_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_RET_LSB 0x1 -#define GC_PMU_CLRHOLDVREF_RET_MASK 0x2 -#define GC_PMU_CLRHOLDVREF_RET_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_RET_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_RET_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_BIASCTRL_LSB 0x2 -#define GC_PMU_CLRHOLDVREF_BIASCTRL_MASK 0x4 -#define GC_PMU_CLRHOLDVREF_BIASCTRL_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_BIASCTRL_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_BIASCTRL_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_BIASTUNER_LSB 0x3 -#define GC_PMU_CLRHOLDVREF_BIASTUNER_MASK 0x8 -#define GC_PMU_CLRHOLDVREF_BIASTUNER_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_BIASTUNER_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_BIASTUNER_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_LDOLNA_LSB 0x4 -#define GC_PMU_CLRHOLDVREF_LDOLNA_MASK 0x10 -#define GC_PMU_CLRHOLDVREF_LDOLNA_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_LDOLNA_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_LDOLNA_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_LDOLO_LSB 0x5 -#define GC_PMU_CLRHOLDVREF_LDOLO_MASK 0x20 -#define GC_PMU_CLRHOLDVREF_LDOLO_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_LDOLO_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_LDOLO_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_LDOCTRL_LSB 0x6 -#define GC_PMU_CLRHOLDVREF_LDOCTRL_MASK 0x40 -#define GC_PMU_CLRHOLDVREF_LDOCTRL_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_LDOCTRL_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_LDOCTRL_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_LDOXO_LSB 0x7 -#define GC_PMU_CLRHOLDVREF_LDOXO_MASK 0x80 -#define GC_PMU_CLRHOLDVREF_LDOXO_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_LDOXO_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_LDOXO_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_BATMON_LSB 0x8 -#define GC_PMU_CLRHOLDVREF_BATMON_MASK 0x100 -#define GC_PMU_CLRHOLDVREF_BATMON_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_BATMON_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_BATMON_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_CMP1_LSB 0x9 -#define GC_PMU_CLRHOLDVREF_CMP1_MASK 0x200 -#define GC_PMU_CLRHOLDVREF_CMP1_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_CMP1_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_CMP1_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_CMP2_LSB 0xa -#define GC_PMU_CLRHOLDVREF_CMP2_MASK 0x400 -#define GC_PMU_CLRHOLDVREF_CMP2_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_CMP2_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_CMP2_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_LSB 0xb -#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_MASK 0x800 -#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_OFFSET 0x6c -#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_LSB 0xc -#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_MASK 0x1000 -#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_SIZE 0x1 -#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_DEFAULT 0x0 -#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_OFFSET 0x6c #define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_LSB 0x0 #define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_MASK 0x3 #define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_SIZE 0x2 #define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_DEFAULT 0x0 -#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_OFFSET 0x74 +#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_OFFSET 0x44 #define GC_PMU_B_REG_DIG_CTRL_SPARE_LSB 0x2 #define GC_PMU_B_REG_DIG_CTRL_SPARE_MASK 0x3c #define GC_PMU_B_REG_DIG_CTRL_SPARE_SIZE 0x4 #define GC_PMU_B_REG_DIG_CTRL_SPARE_DEFAULT 0x0 -#define GC_PMU_B_REG_DIG_CTRL_SPARE_OFFSET 0x74 -#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_LSB 0x0 -#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_MASK 0x1 -#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_SIZE 0x1 -#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_DEFAULT 0x0 -#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_OFFSET 0x78 -#define GC_PMU_EXITPD_MASK_PD_EXIT_LSB 0x0 -#define GC_PMU_EXITPD_MASK_PD_EXIT_MASK 0x1 -#define GC_PMU_EXITPD_MASK_PD_EXIT_SIZE 0x1 -#define GC_PMU_EXITPD_MASK_PD_EXIT_DEFAULT 0x1 -#define GC_PMU_EXITPD_MASK_PD_EXIT_OFFSET 0x84 -#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_LSB 0x1 -#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_MASK 0x2 +#define GC_PMU_B_REG_DIG_CTRL_SPARE_OFFSET 0x44 +#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_LSB 0x0 +#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_MASK 0x1 +#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_SIZE 0x1 +#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_DEFAULT 0x0 +#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_OFFSET 0x48 +#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_LSB 0x1 +#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_MASK 0x2 +#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_SIZE 0x1 +#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_DEFAULT 0x0 +#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_OFFSET 0x48 +#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_LSB 0x2 +#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_MASK 0x4 +#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_SIZE 0x1 +#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_DEFAULT 0x0 +#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_OFFSET 0x48 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_LSB 0x3 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_MASK 0x8 #define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_SIZE 0x1 -#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x1 -#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x84 -#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_LSB 0x2 -#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_MASK 0x4 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x0 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x48 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_LSB 0x4 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_MASK 0x10 #define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_SIZE 0x1 -#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x1 -#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x84 -#define GC_PMU_EXITPD_SRC_PD_EXIT_LSB 0x0 -#define GC_PMU_EXITPD_SRC_PD_EXIT_MASK 0x1 -#define GC_PMU_EXITPD_SRC_PD_EXIT_SIZE 0x1 -#define GC_PMU_EXITPD_SRC_PD_EXIT_DEFAULT 0x0 -#define GC_PMU_EXITPD_SRC_PD_EXIT_OFFSET 0x88 -#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_LSB 0x1 -#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_MASK 0x2 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x0 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x48 +#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_LSB 0x0 +#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_MASK 0x1 +#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_SIZE 0x1 +#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_DEFAULT 0x0 +#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_OFFSET 0x4c +#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_LSB 0x1 +#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_MASK 0x2 +#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_SIZE 0x1 +#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_DEFAULT 0x0 +#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_OFFSET 0x4c +#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_LSB 0x2 +#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_MASK 0x4 +#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_SIZE 0x1 +#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_DEFAULT 0x0 +#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_OFFSET 0x4c +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_LSB 0x3 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_MASK 0x8 #define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_SIZE 0x1 #define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x0 -#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x88 -#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_LSB 0x2 -#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_MASK 0x4 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x4c +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_LSB 0x4 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_MASK 0x10 #define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_SIZE 0x1 #define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x0 -#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x88 -#define GC_PMU_EXITPD_MON_PD_EXIT_LSB 0x0 -#define GC_PMU_EXITPD_MON_PD_EXIT_MASK 0x1 -#define GC_PMU_EXITPD_MON_PD_EXIT_SIZE 0x1 -#define GC_PMU_EXITPD_MON_PD_EXIT_DEFAULT 0x0 -#define GC_PMU_EXITPD_MON_PD_EXIT_OFFSET 0x8c -#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_LSB 0x1 -#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_MASK 0x2 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x4c +#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_LSB 0x0 +#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_MASK 0x1 +#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_SIZE 0x1 +#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_DEFAULT 0x0 +#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_OFFSET 0x50 +#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_LSB 0x1 +#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_MASK 0x2 +#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_SIZE 0x1 +#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_DEFAULT 0x0 +#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_OFFSET 0x50 +#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_LSB 0x2 +#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_MASK 0x4 +#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_SIZE 0x1 +#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_DEFAULT 0x0 +#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_OFFSET 0x50 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_LSB 0x3 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_MASK 0x8 #define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_SIZE 0x1 #define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x0 -#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x8c -#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_LSB 0x2 -#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_MASK 0x4 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x50 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_LSB 0x4 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_MASK 0x10 #define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_SIZE 0x1 #define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x0 -#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x8c +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x50 #define GC_PMU_OSC_CTRL_XTL_READYB_LSB 0x0 #define GC_PMU_OSC_CTRL_XTL_READYB_MASK 0x1 #define GC_PMU_OSC_CTRL_XTL_READYB_SIZE 0x1 #define GC_PMU_OSC_CTRL_XTL_READYB_DEFAULT 0x1 -#define GC_PMU_OSC_CTRL_XTL_READYB_OFFSET 0xa0 -#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_LSB 0x1 -#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_MASK 0x2 -#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_SIZE 0x1 -#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_DEFAULT 0x1 -#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_OFFSET 0xa0 +#define GC_PMU_OSC_CTRL_XTL_READYB_OFFSET 0x54 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_LSB 0x0 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_MASK 0x1 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_SIZE 0x1 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_DEFAULT 0x1 -#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_OFFSET 0xa4 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_OFFSET 0x58 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_LSB 0x1 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_MASK 0x2 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_SIZE 0x1 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_DEFAULT 0x1 -#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_OFFSET 0xa4 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_OFFSET 0x58 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_LSB 0x2 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_MASK 0x4 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_SIZE 0x1 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_DEFAULT 0x1 -#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_OFFSET 0xa4 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_OFFSET 0x58 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_LSB 0x3 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_MASK 0x8 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_SIZE 0x1 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_DEFAULT 0x1 -#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_OFFSET 0xa4 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_OFFSET 0x58 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_LSB 0x4 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_MASK 0x10 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_SIZE 0x1 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_DEFAULT 0x1 -#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_OFFSET 0xa4 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_OFFSET 0x58 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_LSB 0x5 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_MASK 0x20 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_SIZE 0x1 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_DEFAULT 0x1 -#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_OFFSET 0xa4 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_OFFSET 0x58 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_LSB 0x6 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_MASK 0x40 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_SIZE 0x1 #define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_DEFAULT 0x1 -#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_OFFSET 0xa4 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_OFFSET 0x58 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_LSB 0x0 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_MASK 0x1 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_SIZE 0x1 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_DEFAULT 0x1 -#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_OFFSET 0xa8 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_OFFSET 0x5c #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_LSB 0x1 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_MASK 0x2 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_SIZE 0x1 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_DEFAULT 0x1 -#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_OFFSET 0xa8 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_OFFSET 0x5c #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_LSB 0x2 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_MASK 0x4 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_SIZE 0x1 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_DEFAULT 0x1 -#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_OFFSET 0xa8 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_OFFSET 0x5c #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_LSB 0x3 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_MASK 0x8 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_SIZE 0x1 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_DEFAULT 0x1 -#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_OFFSET 0xa8 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_OFFSET 0x5c #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_LSB 0x4 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_MASK 0x10 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_SIZE 0x1 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_DEFAULT 0x1 -#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_OFFSET 0xa8 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_OFFSET 0x5c #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_LSB 0x5 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_MASK 0x20 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_SIZE 0x1 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_DEFAULT 0x1 -#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_OFFSET 0xa8 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_OFFSET 0x5c #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_LSB 0x6 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_MASK 0x40 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_SIZE 0x1 #define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_DEFAULT 0x1 -#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_OFFSET 0xa8 -#define GC_PMU_PERICLKSET0_DAES0_LSB 0x0 -#define GC_PMU_PERICLKSET0_DAES0_MASK 0x1 -#define GC_PMU_PERICLKSET0_DAES0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DAES0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DAES0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DAES1_LSB 0x1 -#define GC_PMU_PERICLKSET0_DAES1_MASK 0x2 -#define GC_PMU_PERICLKSET0_DAES1_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DAES1_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DAES1_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DCAMO0_LSB 0x2 -#define GC_PMU_PERICLKSET0_DCAMO0_MASK 0x4 -#define GC_PMU_PERICLKSET0_DCAMO0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DCAMO0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DCAMO0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DFLASH0_LSB 0x3 -#define GC_PMU_PERICLKSET0_DFLASH0_MASK 0x8 -#define GC_PMU_PERICLKSET0_DFLASH0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DFLASH0_DEFAULT 0x1 -#define GC_PMU_PERICLKSET0_DFLASH0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DGPIO0_LSB 0x4 -#define GC_PMU_PERICLKSET0_DGPIO0_MASK 0x10 -#define GC_PMU_PERICLKSET0_DGPIO0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DGPIO0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DGPIO0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DGPIO1_LSB 0x5 -#define GC_PMU_PERICLKSET0_DGPIO1_MASK 0x20 -#define GC_PMU_PERICLKSET0_DGPIO1_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DGPIO1_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DGPIO1_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DI2C0_LSB 0x6 -#define GC_PMU_PERICLKSET0_DI2C0_MASK 0x40 -#define GC_PMU_PERICLKSET0_DI2C0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DI2C0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DI2C0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DI2C1_LSB 0x7 -#define GC_PMU_PERICLKSET0_DI2C1_MASK 0x80 -#define GC_PMU_PERICLKSET0_DI2C1_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DI2C1_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DI2C1_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DI2CS0_LSB 0x8 -#define GC_PMU_PERICLKSET0_DI2CS0_MASK 0x100 -#define GC_PMU_PERICLKSET0_DI2CS0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DI2CS0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DI2CS0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DMAU_LSB 0x9 -#define GC_PMU_PERICLKSET0_DMAU_MASK 0x200 -#define GC_PMU_PERICLKSET0_DMAU_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DMAU_DEFAULT 0x1 -#define GC_PMU_PERICLKSET0_DMAU_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DPAU_LSB 0xa -#define GC_PMU_PERICLKSET0_DPAU_MASK 0x400 -#define GC_PMU_PERICLKSET0_DPAU_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DPAU_DEFAULT 0x1 -#define GC_PMU_PERICLKSET0_DPAU_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DPINMUX_LSB 0xb -#define GC_PMU_PERICLKSET0_DPINMUX_MASK 0x800 -#define GC_PMU_PERICLKSET0_DPINMUX_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DPINMUX_DEFAULT 0x1 -#define GC_PMU_PERICLKSET0_DPINMUX_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DPMU_LSB 0xc -#define GC_PMU_PERICLKSET0_DPMU_MASK 0x1000 -#define GC_PMU_PERICLKSET0_DPMU_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DPMU_DEFAULT 0x1 -#define GC_PMU_PERICLKSET0_DPMU_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DRBOX0_LSB 0xd -#define GC_PMU_PERICLKSET0_DRBOX0_MASK 0x2000 -#define GC_PMU_PERICLKSET0_DRBOX0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DRBOX0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DRBOX0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DRTC0_LSB 0xe -#define GC_PMU_PERICLKSET0_DRTC0_MASK 0x4000 -#define GC_PMU_PERICLKSET0_DRTC0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DRTC0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DRTC0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DSHA0_LSB 0xf -#define GC_PMU_PERICLKSET0_DSHA0_MASK 0x8000 -#define GC_PMU_PERICLKSET0_DSHA0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DSHA0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DSHA0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DSPI0_LSB 0x10 -#define GC_PMU_PERICLKSET0_DSPI0_MASK 0x10000 -#define GC_PMU_PERICLKSET0_DSPI0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DSPI0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DSPI0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DSPS0_LSB 0x11 -#define GC_PMU_PERICLKSET0_DSPS0_MASK 0x20000 -#define GC_PMU_PERICLKSET0_DSPS0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DSPS0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DSPS0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DSWDP0_LSB 0x12 -#define GC_PMU_PERICLKSET0_DSWDP0_MASK 0x40000 -#define GC_PMU_PERICLKSET0_DSWDP0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DSWDP0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DSWDP0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DTEMP0_LSB 0x13 -#define GC_PMU_PERICLKSET0_DTEMP0_MASK 0x80000 -#define GC_PMU_PERICLKSET0_DTEMP0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DTEMP0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DTEMP0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DTIMEHS0_LSB 0x14 -#define GC_PMU_PERICLKSET0_DTIMEHS0_MASK 0x100000 -#define GC_PMU_PERICLKSET0_DTIMEHS0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DTIMEHS0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DTIMEHS0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DTIMEHS1_LSB 0x15 -#define GC_PMU_PERICLKSET0_DTIMEHS1_MASK 0x200000 -#define GC_PMU_PERICLKSET0_DTIMEHS1_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DTIMEHS1_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DTIMEHS1_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DTIMELS0_LSB 0x16 -#define GC_PMU_PERICLKSET0_DTIMELS0_MASK 0x400000 -#define GC_PMU_PERICLKSET0_DTIMELS0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DTIMELS0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DTIMELS0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DTRNG0_LSB 0x17 -#define GC_PMU_PERICLKSET0_DTRNG0_MASK 0x800000 -#define GC_PMU_PERICLKSET0_DTRNG0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DTRNG0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DTRNG0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DUART0_LSB 0x18 -#define GC_PMU_PERICLKSET0_DUART0_MASK 0x1000000 -#define GC_PMU_PERICLKSET0_DUART0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DUART0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DUART0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DUART1_LSB 0x19 -#define GC_PMU_PERICLKSET0_DUART1_MASK 0x2000000 -#define GC_PMU_PERICLKSET0_DUART1_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DUART1_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DUART1_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DUART2_LSB 0x1a -#define GC_PMU_PERICLKSET0_DUART2_MASK 0x4000000 -#define GC_PMU_PERICLKSET0_DUART2_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DUART2_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DUART2_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DUSB0_LSB 0x1b -#define GC_PMU_PERICLKSET0_DUSB0_MASK 0x8000000 -#define GC_PMU_PERICLKSET0_DUSB0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DUSB0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DUSB0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_LSB 0x1c -#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_MASK 0x10000000 -#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DWATCHDOG0_LSB 0x1d -#define GC_PMU_PERICLKSET0_DWATCHDOG0_MASK 0x20000000 -#define GC_PMU_PERICLKSET0_DWATCHDOG0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DWATCHDOG0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DWATCHDOG0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_DXO0_LSB 0x1e -#define GC_PMU_PERICLKSET0_DXO0_MASK 0x40000000 -#define GC_PMU_PERICLKSET0_DXO0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DXO0_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DXO0_OFFSET 0xac -#define GC_PMU_PERICLKSET0_PERI0_LSB 0x1f -#define GC_PMU_PERICLKSET0_PERI0_MASK 0x80000000 -#define GC_PMU_PERICLKSET0_PERI0_SIZE 0x1 -#define GC_PMU_PERICLKSET0_PERI0_DEFAULT 0x1 -#define GC_PMU_PERICLKSET0_PERI0_OFFSET 0xac -#define GC_PMU_PERICLKCLR0_DAES0_LSB 0x0 -#define GC_PMU_PERICLKCLR0_DAES0_MASK 0x1 -#define GC_PMU_PERICLKCLR0_DAES0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DAES0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DAES0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DAES1_LSB 0x1 -#define GC_PMU_PERICLKCLR0_DAES1_MASK 0x2 -#define GC_PMU_PERICLKCLR0_DAES1_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DAES1_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DAES1_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DCAMO0_LSB 0x2 -#define GC_PMU_PERICLKCLR0_DCAMO0_MASK 0x4 -#define GC_PMU_PERICLKCLR0_DCAMO0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DCAMO0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DCAMO0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DFLASH0_LSB 0x3 -#define GC_PMU_PERICLKCLR0_DFLASH0_MASK 0x8 -#define GC_PMU_PERICLKCLR0_DFLASH0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DFLASH0_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR0_DFLASH0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DGPIO0_LSB 0x4 -#define GC_PMU_PERICLKCLR0_DGPIO0_MASK 0x10 -#define GC_PMU_PERICLKCLR0_DGPIO0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DGPIO0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DGPIO0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DGPIO1_LSB 0x5 -#define GC_PMU_PERICLKCLR0_DGPIO1_MASK 0x20 -#define GC_PMU_PERICLKCLR0_DGPIO1_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DGPIO1_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DGPIO1_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DI2C0_LSB 0x6 -#define GC_PMU_PERICLKCLR0_DI2C0_MASK 0x40 -#define GC_PMU_PERICLKCLR0_DI2C0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DI2C0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DI2C0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DI2C1_LSB 0x7 -#define GC_PMU_PERICLKCLR0_DI2C1_MASK 0x80 -#define GC_PMU_PERICLKCLR0_DI2C1_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DI2C1_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DI2C1_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DI2CS0_LSB 0x8 -#define GC_PMU_PERICLKCLR0_DI2CS0_MASK 0x100 -#define GC_PMU_PERICLKCLR0_DI2CS0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DI2CS0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DI2CS0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DMAU_LSB 0x9 -#define GC_PMU_PERICLKCLR0_DMAU_MASK 0x200 -#define GC_PMU_PERICLKCLR0_DMAU_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DMAU_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR0_DMAU_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DPAU_LSB 0xa -#define GC_PMU_PERICLKCLR0_DPAU_MASK 0x400 -#define GC_PMU_PERICLKCLR0_DPAU_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DPAU_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR0_DPAU_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DPINMUX_LSB 0xb -#define GC_PMU_PERICLKCLR0_DPINMUX_MASK 0x800 -#define GC_PMU_PERICLKCLR0_DPINMUX_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DPINMUX_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR0_DPINMUX_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DPMU_LSB 0xc -#define GC_PMU_PERICLKCLR0_DPMU_MASK 0x1000 -#define GC_PMU_PERICLKCLR0_DPMU_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DPMU_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR0_DPMU_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DRBOX0_LSB 0xd -#define GC_PMU_PERICLKCLR0_DRBOX0_MASK 0x2000 -#define GC_PMU_PERICLKCLR0_DRBOX0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DRBOX0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DRBOX0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DRTC0_LSB 0xe -#define GC_PMU_PERICLKCLR0_DRTC0_MASK 0x4000 -#define GC_PMU_PERICLKCLR0_DRTC0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DRTC0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DRTC0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DSHA0_LSB 0xf -#define GC_PMU_PERICLKCLR0_DSHA0_MASK 0x8000 -#define GC_PMU_PERICLKCLR0_DSHA0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DSHA0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DSHA0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DSPI0_LSB 0x10 -#define GC_PMU_PERICLKCLR0_DSPI0_MASK 0x10000 -#define GC_PMU_PERICLKCLR0_DSPI0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DSPI0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DSPI0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DSPS0_LSB 0x11 -#define GC_PMU_PERICLKCLR0_DSPS0_MASK 0x20000 -#define GC_PMU_PERICLKCLR0_DSPS0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DSPS0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DSPS0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DSWDP0_LSB 0x12 -#define GC_PMU_PERICLKCLR0_DSWDP0_MASK 0x40000 -#define GC_PMU_PERICLKCLR0_DSWDP0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DSWDP0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DSWDP0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DTEMP0_LSB 0x13 -#define GC_PMU_PERICLKCLR0_DTEMP0_MASK 0x80000 -#define GC_PMU_PERICLKCLR0_DTEMP0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DTEMP0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DTEMP0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DTIMEHS0_LSB 0x14 -#define GC_PMU_PERICLKCLR0_DTIMEHS0_MASK 0x100000 -#define GC_PMU_PERICLKCLR0_DTIMEHS0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DTIMEHS0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DTIMEHS0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DTIMEHS1_LSB 0x15 -#define GC_PMU_PERICLKCLR0_DTIMEHS1_MASK 0x200000 -#define GC_PMU_PERICLKCLR0_DTIMEHS1_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DTIMEHS1_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DTIMEHS1_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DTIMELS0_LSB 0x16 -#define GC_PMU_PERICLKCLR0_DTIMELS0_MASK 0x400000 -#define GC_PMU_PERICLKCLR0_DTIMELS0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DTIMELS0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DTIMELS0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DTRNG0_LSB 0x17 -#define GC_PMU_PERICLKCLR0_DTRNG0_MASK 0x800000 -#define GC_PMU_PERICLKCLR0_DTRNG0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DTRNG0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DTRNG0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DUART0_LSB 0x18 -#define GC_PMU_PERICLKCLR0_DUART0_MASK 0x1000000 -#define GC_PMU_PERICLKCLR0_DUART0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DUART0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DUART0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DUART1_LSB 0x19 -#define GC_PMU_PERICLKCLR0_DUART1_MASK 0x2000000 -#define GC_PMU_PERICLKCLR0_DUART1_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DUART1_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DUART1_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DUART2_LSB 0x1a -#define GC_PMU_PERICLKCLR0_DUART2_MASK 0x4000000 -#define GC_PMU_PERICLKCLR0_DUART2_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DUART2_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DUART2_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DUSB0_LSB 0x1b -#define GC_PMU_PERICLKCLR0_DUSB0_MASK 0x8000000 -#define GC_PMU_PERICLKCLR0_DUSB0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DUSB0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DUSB0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_LSB 0x1c -#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_MASK 0x10000000 -#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DWATCHDOG0_LSB 0x1d -#define GC_PMU_PERICLKCLR0_DWATCHDOG0_MASK 0x20000000 -#define GC_PMU_PERICLKCLR0_DWATCHDOG0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DWATCHDOG0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DWATCHDOG0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_DXO0_LSB 0x1e -#define GC_PMU_PERICLKCLR0_DXO0_MASK 0x40000000 -#define GC_PMU_PERICLKCLR0_DXO0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DXO0_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DXO0_OFFSET 0xb0 -#define GC_PMU_PERICLKCLR0_PERI0_LSB 0x1f -#define GC_PMU_PERICLKCLR0_PERI0_MASK 0x80000000 -#define GC_PMU_PERICLKCLR0_PERI0_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_PERI0_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR0_PERI0_OFFSET 0xb0 -#define GC_PMU_PERICLKSET1_PERI1_LSB 0x0 -#define GC_PMU_PERICLKSET1_PERI1_MASK 0x1 -#define GC_PMU_PERICLKSET1_PERI1_SIZE 0x1 -#define GC_PMU_PERICLKSET1_PERI1_DEFAULT 0x1 -#define GC_PMU_PERICLKSET1_PERI1_OFFSET 0xb4 -#define GC_PMU_PERICLKSET1_PERI_MATRIX_LSB 0x1 -#define GC_PMU_PERICLKSET1_PERI_MATRIX_MASK 0x2 -#define GC_PMU_PERICLKSET1_PERI_MATRIX_SIZE 0x1 -#define GC_PMU_PERICLKSET1_PERI_MATRIX_DEFAULT 0x1 -#define GC_PMU_PERICLKSET1_PERI_MATRIX_OFFSET 0xb4 -#define GC_PMU_PERICLKCLR1_PERI1_LSB 0x0 -#define GC_PMU_PERICLKCLR1_PERI1_MASK 0x1 -#define GC_PMU_PERICLKCLR1_PERI1_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_PERI1_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR1_PERI1_OFFSET 0xb8 -#define GC_PMU_PERICLKCLR1_PERI_MATRIX_LSB 0x1 -#define GC_PMU_PERICLKCLR1_PERI_MATRIX_MASK 0x2 -#define GC_PMU_PERICLKCLR1_PERI_MATRIX_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_PERI_MATRIX_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR1_PERI_MATRIX_OFFSET 0xb8 -#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_LSB 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_MASK 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_LSB 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_MASK 0x2 -#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_LSB 0x2 -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_MASK 0x4 -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_LSB 0x3 -#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_MASK 0x8 -#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_LSB 0x4 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_MASK 0x10 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_LSB 0x5 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_MASK 0x20 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_LSB 0x6 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_MASK 0x40 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_LSB 0x7 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_MASK 0x80 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_LSB 0x8 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_MASK 0x100 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_LSB 0x9 -#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_MASK 0x200 -#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_LSB 0xa -#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_MASK 0x400 -#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_LSB 0xb -#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_MASK 0x800 -#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_LSB 0xc -#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_MASK 0x1000 -#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_LSB 0xd -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_MASK 0x2000 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_LSB 0xe -#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_MASK 0x4000 -#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_LSB 0xf -#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_MASK 0x8000 -#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_LSB 0x10 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_MASK 0x10000 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_LSB 0x11 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_MASK 0x20000 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_LSB 0x12 -#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_MASK 0x40000 -#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_LSB 0x13 -#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_MASK 0x80000 -#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_LSB 0x14 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_MASK 0x100000 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_LSB 0x15 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_MASK 0x200000 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_LSB 0x16 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_MASK 0x400000 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_LSB 0x17 -#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_MASK 0x800000 -#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_LSB 0x18 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_MASK 0x1000000 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_LSB 0x19 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_MASK 0x2000000 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_LSB 0x1a -#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_MASK 0x4000000 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_LSB 0x1b -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_MASK 0x8000000 -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_LSB 0x1c -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_MASK 0x10000000 -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_LSB 0x1d -#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_MASK 0x20000000 -#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_LSB 0x1e -#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_MASK 0x40000000 -#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPSET0_PERI0_LSB 0x1f -#define GC_PMU_PERIGATEONSLEEPSET0_PERI0_MASK 0x80000000 -#define GC_PMU_PERIGATEONSLEEPSET0_PERI0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_PERI0_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_PERI0_OFFSET 0xbc -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_LSB 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_MASK 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_LSB 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_MASK 0x2 -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_LSB 0x2 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_MASK 0x4 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_LSB 0x3 -#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_MASK 0x8 -#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_LSB 0x4 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_MASK 0x10 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_LSB 0x5 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_MASK 0x20 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_LSB 0x6 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_MASK 0x40 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_LSB 0x7 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_MASK 0x80 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_LSB 0x8 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_MASK 0x100 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_LSB 0x9 -#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_MASK 0x200 -#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_LSB 0xa -#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_MASK 0x400 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_LSB 0xb -#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_MASK 0x800 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_LSB 0xc -#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_MASK 0x1000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_LSB 0xd -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_MASK 0x2000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_LSB 0xe -#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_MASK 0x4000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_LSB 0xf -#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_MASK 0x8000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_LSB 0x10 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_MASK 0x10000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_LSB 0x11 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_MASK 0x20000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_LSB 0x12 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_MASK 0x40000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_LSB 0x13 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_MASK 0x80000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_LSB 0x14 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_MASK 0x100000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_LSB 0x15 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_MASK 0x200000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_LSB 0x16 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_MASK 0x400000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_LSB 0x17 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_MASK 0x800000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_LSB 0x18 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_MASK 0x1000000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_LSB 0x19 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_MASK 0x2000000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_LSB 0x1a -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_MASK 0x4000000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_LSB 0x1b -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_MASK 0x8000000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_LSB 0x1c -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_MASK 0x10000000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_LSB 0x1d -#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_MASK 0x20000000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_LSB 0x1e -#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_MASK 0x40000000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPCLR0_PERI0_LSB 0x1f -#define GC_PMU_PERIGATEONSLEEPCLR0_PERI0_MASK 0x80000000 -#define GC_PMU_PERIGATEONSLEEPCLR0_PERI0_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_PERI0_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_PERI0_OFFSET 0xc0 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_LSB 0x0 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_MASK 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_OFFSET 0xc4 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_LSB 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_MASK 0x2 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_OFFSET 0xc4 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_LSB 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_MASK 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_OFFSET 0xc8 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_LSB 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_MASK 0x2 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_DEFAULT 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_OFFSET 0xc8 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_OFFSET 0x5c +#define GC_PMU_PERICLKSET0_DAES0_CLK_LSB 0x0 +#define GC_PMU_PERICLKSET0_DAES0_CLK_MASK 0x1 +#define GC_PMU_PERICLKSET0_DAES0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DAES0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DAES0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_LSB 0x1 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_MASK 0x2 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_LSB 0x2 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_MASK 0x4 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_LSB 0x3 +#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_MASK 0x8 +#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DDMA0_CLK_LSB 0x4 +#define GC_PMU_PERICLKSET0_DDMA0_CLK_MASK 0x10 +#define GC_PMU_PERICLKSET0_DDMA0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DDMA0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DDMA0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DFLASH0_CLK_LSB 0x5 +#define GC_PMU_PERICLKSET0_DFLASH0_CLK_MASK 0x20 +#define GC_PMU_PERICLKSET0_DFLASH0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DFLASH0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DFLASH0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DFUSE0_CLK_LSB 0x6 +#define GC_PMU_PERICLKSET0_DFUSE0_CLK_MASK 0x40 +#define GC_PMU_PERICLKSET0_DFUSE0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DFUSE0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DFUSE0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_LSB 0x7 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_MASK 0x80 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_LSB 0x8 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DGPIO0_CLK_LSB 0x9 +#define GC_PMU_PERICLKSET0_DGPIO0_CLK_MASK 0x200 +#define GC_PMU_PERICLKSET0_DGPIO0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DGPIO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DGPIO0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DGPIO1_CLK_LSB 0xa +#define GC_PMU_PERICLKSET0_DGPIO1_CLK_MASK 0x400 +#define GC_PMU_PERICLKSET0_DGPIO1_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DGPIO1_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DGPIO1_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_LSB 0xb +#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_MASK 0x800 +#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_LSB 0xc +#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_MASK 0x1000 +#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DI2CS0_CLK_LSB 0xd +#define GC_PMU_PERICLKSET0_DI2CS0_CLK_MASK 0x2000 +#define GC_PMU_PERICLKSET0_DI2CS0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DI2CS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DI2CS0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DMAU_CLK_LSB 0xe +#define GC_PMU_PERICLKSET0_DMAU_CLK_MASK 0x4000 +#define GC_PMU_PERICLKSET0_DMAU_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DMAU_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DMAU_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_LSB 0xf +#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_MASK 0x8000 +#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_LSB 0x10 +#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_MASK 0x10000 +#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_LSB 0x11 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_MASK 0x20000 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_LSB 0x12 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DPINMUX_CLK_LSB 0x13 +#define GC_PMU_PERICLKSET0_DPINMUX_CLK_MASK 0x80000 +#define GC_PMU_PERICLKSET0_DPINMUX_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DPINMUX_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DPINMUX_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DPMU_CLK_LSB 0x14 +#define GC_PMU_PERICLKSET0_DPMU_CLK_MASK 0x100000 +#define GC_PMU_PERICLKSET0_DPMU_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DPMU_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DPMU_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_LSB 0x15 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_MASK 0x200000 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_LSB 0x16 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_MASK 0x400000 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DRDD0_CLK_LSB 0x17 +#define GC_PMU_PERICLKSET0_DRDD0_CLK_MASK 0x800000 +#define GC_PMU_PERICLKSET0_DRDD0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DRDD0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DRDD0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_LSB 0x18 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_MASK 0x1000000 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_LSB 0x19 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_MASK 0x2000000 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DSHA0_CLK_LSB 0x1a +#define GC_PMU_PERICLKSET0_DSHA0_CLK_MASK 0x4000000 +#define GC_PMU_PERICLKSET0_DSHA0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSHA0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DSHA0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_LSB 0x1b +#define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_LSB 0x1c +#define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_MASK 0x10000000 +#define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_LSB 0x1d +#define GC_PMU_PERICLKSET0_DSPS0_CLK_MASK 0x20000000 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_LSB 0x1e +#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_MASK 0x40000000 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DSWDP0_CLK_LSB 0x1f +#define GC_PMU_PERICLKSET0_DSWDP0_CLK_MASK 0x80000000 +#define GC_PMU_PERICLKSET0_DSWDP0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSWDP0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DSWDP0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKCLR0_DAES0_CLK_LSB 0x0 +#define GC_PMU_PERICLKCLR0_DAES0_CLK_MASK 0x1 +#define GC_PMU_PERICLKCLR0_DAES0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DAES0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DAES0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_LSB 0x1 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_MASK 0x2 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_LSB 0x2 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_MASK 0x4 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_LSB 0x3 +#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_MASK 0x8 +#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DDMA0_CLK_LSB 0x4 +#define GC_PMU_PERICLKCLR0_DDMA0_CLK_MASK 0x10 +#define GC_PMU_PERICLKCLR0_DDMA0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DDMA0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DDMA0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_LSB 0x5 +#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_MASK 0x20 +#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_LSB 0x6 +#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_MASK 0x40 +#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_LSB 0x7 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_MASK 0x80 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_LSB 0x8 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_LSB 0x9 +#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_MASK 0x200 +#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_LSB 0xa +#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_MASK 0x400 +#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_LSB 0xb +#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_MASK 0x800 +#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_LSB 0xc +#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_MASK 0x1000 +#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_LSB 0xd +#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_MASK 0x2000 +#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DMAU_CLK_LSB 0xe +#define GC_PMU_PERICLKCLR0_DMAU_CLK_MASK 0x4000 +#define GC_PMU_PERICLKCLR0_DMAU_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DMAU_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DMAU_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_LSB 0xf +#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_MASK 0x8000 +#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_LSB 0x10 +#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_MASK 0x10000 +#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_LSB 0x11 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_MASK 0x20000 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_LSB 0x12 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_LSB 0x13 +#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_MASK 0x80000 +#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DPMU_CLK_LSB 0x14 +#define GC_PMU_PERICLKCLR0_DPMU_CLK_MASK 0x100000 +#define GC_PMU_PERICLKCLR0_DPMU_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DPMU_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DPMU_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_LSB 0x15 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_MASK 0x200000 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_LSB 0x16 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_MASK 0x400000 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DRDD0_CLK_LSB 0x17 +#define GC_PMU_PERICLKCLR0_DRDD0_CLK_MASK 0x800000 +#define GC_PMU_PERICLKCLR0_DRDD0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DRDD0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DRDD0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_LSB 0x18 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_MASK 0x1000000 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_LSB 0x19 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_MASK 0x2000000 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DSHA0_CLK_LSB 0x1a +#define GC_PMU_PERICLKCLR0_DSHA0_CLK_MASK 0x4000000 +#define GC_PMU_PERICLKCLR0_DSHA0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSHA0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DSHA0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_LSB 0x1b +#define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_LSB 0x1c +#define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_MASK 0x10000000 +#define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_LSB 0x1d +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_MASK 0x20000000 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_LSB 0x1e +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_MASK 0x40000000 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_LSB 0x1f +#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_MASK 0x80000000 +#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_OFFSET 0x64 +#define GC_PMU_PERICLKSET1_DTEMP0_CLK_LSB 0x0 +#define GC_PMU_PERICLKSET1_DTEMP0_CLK_MASK 0x1 +#define GC_PMU_PERICLKSET1_DTEMP0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DTEMP0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_DTEMP0_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_MASK 0x2 +#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_LSB 0x2 +#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_MASK 0x4 +#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_LSB 0x3 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_MASK 0x8 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_LSB 0x4 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_MASK 0x10 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_LSB 0x5 +#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_MASK 0x20 +#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DTRNG0_CLK_LSB 0x6 +#define GC_PMU_PERICLKSET1_DTRNG0_CLK_MASK 0x40 +#define GC_PMU_PERICLKSET1_DTRNG0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DTRNG0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_DTRNG0_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_LSB 0x7 +#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_LSB 0x8 +#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_LSB 0x9 +#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_MASK 0x200 +#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_LSB 0xa +#define GC_PMU_PERICLKSET1_DUSB0_CLK_MASK 0x400 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_LSB 0xb +#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_MASK 0x800 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DVOLT0_CLK_LSB 0xc +#define GC_PMU_PERICLKSET1_DVOLT0_CLK_MASK 0x1000 +#define GC_PMU_PERICLKSET1_DVOLT0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DVOLT0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DVOLT0_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_LSB 0xd +#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_MASK 0x2000 +#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DXO0_CLK_LSB 0xe +#define GC_PMU_PERICLKSET1_DXO0_CLK_MASK 0x4000 +#define GC_PMU_PERICLKSET1_DXO0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DXO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DXO0_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_LSB 0xf +#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_MASK 0x8000 +#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_LSB 0x10 +#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_MASK 0x10000 +#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_LSB 0x11 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_MASK 0x20000 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_LSB 0x12 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_MASK 0x40000 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_SIZE 0x1 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_OFFSET 0x68 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_LSB 0x13 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_MASK 0x80000 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_OFFSET 0x68 +#define GC_PMU_PERICLKCLR1_DTEMP0_CLK_LSB 0x0 +#define GC_PMU_PERICLKCLR1_DTEMP0_CLK_MASK 0x1 +#define GC_PMU_PERICLKCLR1_DTEMP0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DTEMP0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_DTEMP0_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_MASK 0x2 +#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_LSB 0x2 +#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_MASK 0x4 +#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_LSB 0x3 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_MASK 0x8 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_LSB 0x4 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_MASK 0x10 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_LSB 0x5 +#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_MASK 0x20 +#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_LSB 0x6 +#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_MASK 0x40 +#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_LSB 0x7 +#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_LSB 0x8 +#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_LSB 0x9 +#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_MASK 0x200 +#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_LSB 0xa +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_MASK 0x400 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_LSB 0xb +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_MASK 0x800 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_LSB 0xc +#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_MASK 0x1000 +#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_LSB 0xd +#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_MASK 0x2000 +#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DXO0_CLK_LSB 0xe +#define GC_PMU_PERICLKCLR1_DXO0_CLK_MASK 0x4000 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_LSB 0xf +#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_MASK 0x8000 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_LSB 0x10 +#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_MASK 0x10000 +#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_LSB 0x11 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_MASK 0x20000 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_LSB 0x12 +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_MASK 0x40000 +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_OFFSET 0x6c +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_LSB 0x13 +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_MASK 0x80000 +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_OFFSET 0x6c +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_CLK_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_CLK_MASK 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_MASK 0x2 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_MASK 0x8 +#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_LSB 0xe +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_LSB 0xf +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_LSB 0x10 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_LSB 0x11 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_MASK 0x20000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_LSB 0x12 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_LSB 0x13 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_MASK 0x80000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_LSB 0x14 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_MASK 0x100000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_LSB 0x15 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_MASK 0x200000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_LSB 0x16 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_MASK 0x400000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_LSB 0x17 +#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_MASK 0x800000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_LSB 0x18 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_MASK 0x1000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_LSB 0x19 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_MASK 0x2000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_CLK_LSB 0x1a +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_CLK_MASK 0x4000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_LSB 0x1b +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_LSB 0x1c +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_MASK 0x10000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_LSB 0x1d +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_MASK 0x20000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_LSB 0x1e +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_MASK 0x40000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_LSB 0x1f +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_MASK 0x80000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_CLK_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_CLK_MASK 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_MASK 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_MASK 0x8 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_LSB 0xe +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_LSB 0xf +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_LSB 0x10 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_LSB 0x11 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_MASK 0x20000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_LSB 0x12 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_LSB 0x13 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_MASK 0x80000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_LSB 0x14 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_MASK 0x100000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_LSB 0x15 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_MASK 0x200000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_LSB 0x16 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_MASK 0x400000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_LSB 0x17 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_MASK 0x800000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_LSB 0x18 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_MASK 0x1000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_LSB 0x19 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_MASK 0x2000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_CLK_LSB 0x1a +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_CLK_MASK 0x4000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_LSB 0x1b +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_LSB 0x1c +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_MASK 0x10000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_LSB 0x1d +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_MASK 0x20000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_LSB 0x1e +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_MASK 0x40000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_LSB 0x1f +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_MASK 0x80000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPSET1_DTEMP0_CLK_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DTEMP0_CLK_MASK 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTEMP0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTEMP0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DTEMP0_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_MASK 0x2 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_MASK 0x8 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_LSB 0xe +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_LSB 0xf +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_LSB 0x10 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_LSB 0x11 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_MASK 0x20000 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_LSB 0x12 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_MASK 0x40000 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_LSB 0x13 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_MASK 0x80000 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_OFFSET 0x78 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTEMP0_CLK_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTEMP0_CLK_MASK 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTEMP0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTEMP0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTEMP0_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_MASK 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_MASK 0x8 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_LSB 0xe +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_LSB 0xf +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_LSB 0x10 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_LSB 0x11 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_MASK 0x20000 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_LSB 0x12 +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_MASK 0x40000 +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_OFFSET 0x7c +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_LSB 0x13 +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_MASK 0x80000 +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_OFFSET 0x7c #define GC_PMU_CLK0_HCLKGATEEN_LSB 0x0 #define GC_PMU_CLK0_HCLKGATEEN_MASK 0x1 #define GC_PMU_CLK0_HCLKGATEEN_SIZE 0x1 #define GC_PMU_CLK0_HCLKGATEEN_DEFAULT 0x1 -#define GC_PMU_CLK0_HCLKGATEEN_OFFSET 0xcc +#define GC_PMU_CLK0_HCLKGATEEN_OFFSET 0x80 #define GC_PMU_CLK0_DAPCLKGATEEN_LSB 0x1 #define GC_PMU_CLK0_DAPCLKGATEEN_MASK 0x2 #define GC_PMU_CLK0_DAPCLKGATEEN_SIZE 0x1 #define GC_PMU_CLK0_DAPCLKGATEEN_DEFAULT 0x1 -#define GC_PMU_CLK0_DAPCLKGATEEN_OFFSET 0xcc +#define GC_PMU_CLK0_DAPCLKGATEEN_OFFSET 0x80 #define GC_PMU_CLK0_TPIUGATEEN_LSB 0x2 #define GC_PMU_CLK0_TPIUGATEEN_MASK 0x4 #define GC_PMU_CLK0_TPIUGATEEN_SIZE 0x1 #define GC_PMU_CLK0_TPIUGATEEN_DEFAULT 0x1 -#define GC_PMU_CLK0_TPIUGATEEN_OFFSET 0xcc +#define GC_PMU_CLK0_TPIUGATEEN_OFFSET 0x80 #define GC_PMU_CLK0_FCLKEN_LSB 0x3 #define GC_PMU_CLK0_FCLKEN_MASK 0x8 #define GC_PMU_CLK0_FCLKEN_SIZE 0x1 #define GC_PMU_CLK0_FCLKEN_DEFAULT 0x1 -#define GC_PMU_CLK0_FCLKEN_OFFSET 0xcc +#define GC_PMU_CLK0_FCLKEN_OFFSET 0x80 #define GC_PMU_CLK0_DAPCLKEN_LSB 0x4 #define GC_PMU_CLK0_DAPCLKEN_MASK 0x10 #define GC_PMU_CLK0_DAPCLKEN_SIZE 0x1 #define GC_PMU_CLK0_DAPCLKEN_DEFAULT 0x1 -#define GC_PMU_CLK0_DAPCLKEN_OFFSET 0xcc +#define GC_PMU_CLK0_DAPCLKEN_OFFSET 0x80 #define GC_PMU_CLK0_TPIUCLKEN_LSB 0x5 #define GC_PMU_CLK0_TPIUCLKEN_MASK 0x20 #define GC_PMU_CLK0_TPIUCLKEN_SIZE 0x1 #define GC_PMU_CLK0_TPIUCLKEN_DEFAULT 0x0 -#define GC_PMU_CLK0_TPIUCLKEN_OFFSET 0xcc +#define GC_PMU_CLK0_TPIUCLKEN_OFFSET 0x80 #define GC_PMU_CLK0_TRACECLKEN_LSB 0x6 #define GC_PMU_CLK0_TRACECLKEN_MASK 0x40 #define GC_PMU_CLK0_TRACECLKEN_SIZE 0x1 #define GC_PMU_CLK0_TRACECLKEN_DEFAULT 0x0 -#define GC_PMU_CLK0_TRACECLKEN_OFFSET 0xcc -#define GC_PMU_CLK1_HCLKGATEEN_LSB 0x0 -#define GC_PMU_CLK1_HCLKGATEEN_MASK 0x1 -#define GC_PMU_CLK1_HCLKGATEEN_SIZE 0x1 -#define GC_PMU_CLK1_HCLKGATEEN_DEFAULT 0x1 -#define GC_PMU_CLK1_HCLKGATEEN_OFFSET 0xd0 -#define GC_PMU_CLK1_DAPCLKGATEEN_LSB 0x1 -#define GC_PMU_CLK1_DAPCLKGATEEN_MASK 0x2 -#define GC_PMU_CLK1_DAPCLKGATEEN_SIZE 0x1 -#define GC_PMU_CLK1_DAPCLKGATEEN_DEFAULT 0x1 -#define GC_PMU_CLK1_DAPCLKGATEEN_OFFSET 0xd0 -#define GC_PMU_CLK1_TPIUGATEEN_LSB 0x2 -#define GC_PMU_CLK1_TPIUGATEEN_MASK 0x4 -#define GC_PMU_CLK1_TPIUGATEEN_SIZE 0x1 -#define GC_PMU_CLK1_TPIUGATEEN_DEFAULT 0x1 -#define GC_PMU_CLK1_TPIUGATEEN_OFFSET 0xd0 -#define GC_PMU_CLK1_FCLKEN_LSB 0x3 -#define GC_PMU_CLK1_FCLKEN_MASK 0x8 -#define GC_PMU_CLK1_FCLKEN_SIZE 0x1 -#define GC_PMU_CLK1_FCLKEN_DEFAULT 0x1 -#define GC_PMU_CLK1_FCLKEN_OFFSET 0xd0 -#define GC_PMU_CLK1_DAPCLKEN_LSB 0x4 -#define GC_PMU_CLK1_DAPCLKEN_MASK 0x10 -#define GC_PMU_CLK1_DAPCLKEN_SIZE 0x1 -#define GC_PMU_CLK1_DAPCLKEN_DEFAULT 0x1 -#define GC_PMU_CLK1_DAPCLKEN_OFFSET 0xd0 -#define GC_PMU_CLK1_TPIUCLKEN_LSB 0x5 -#define GC_PMU_CLK1_TPIUCLKEN_MASK 0x20 -#define GC_PMU_CLK1_TPIUCLKEN_SIZE 0x1 -#define GC_PMU_CLK1_TPIUCLKEN_DEFAULT 0x0 -#define GC_PMU_CLK1_TPIUCLKEN_OFFSET 0xd0 -#define GC_PMU_CLK1_TRACECLKEN_LSB 0x6 -#define GC_PMU_CLK1_TRACECLKEN_MASK 0x40 -#define GC_PMU_CLK1_TRACECLKEN_SIZE 0x1 -#define GC_PMU_CLK1_TRACECLKEN_DEFAULT 0x0 -#define GC_PMU_CLK1_TRACECLKEN_OFFSET 0xd0 -#define GC_PMU_RST0_DSHA0_LSB 0x0 -#define GC_PMU_RST0_DSHA0_MASK 0x1 -#define GC_PMU_RST0_DSHA0_SIZE 0x1 -#define GC_PMU_RST0_DSHA0_DEFAULT 0x0 -#define GC_PMU_RST0_DSHA0_OFFSET 0xd4 -#define GC_PMU_RST0_DUSB0_LSB 0x1 -#define GC_PMU_RST0_DUSB0_MASK 0x2 -#define GC_PMU_RST0_DUSB0_SIZE 0x1 -#define GC_PMU_RST0_DUSB0_DEFAULT 0x0 -#define GC_PMU_RST0_DUSB0_OFFSET 0xd4 -#define GC_PMU_RST0_PERI0_LSB 0x2 -#define GC_PMU_RST0_PERI0_MASK 0x4 -#define GC_PMU_RST0_PERI0_SIZE 0x1 -#define GC_PMU_RST0_PERI0_DEFAULT 0x0 -#define GC_PMU_RST0_PERI0_OFFSET 0xd4 -#define GC_PMU_RST0_DUART1_LSB 0x3 -#define GC_PMU_RST0_DUART1_MASK 0x8 -#define GC_PMU_RST0_DUART1_SIZE 0x1 -#define GC_PMU_RST0_DUART1_DEFAULT 0x0 -#define GC_PMU_RST0_DUART1_OFFSET 0xd4 -#define GC_PMU_RST0_DTEMP0_LSB 0x4 -#define GC_PMU_RST0_DTEMP0_MASK 0x10 -#define GC_PMU_RST0_DTEMP0_SIZE 0x1 -#define GC_PMU_RST0_DTEMP0_DEFAULT 0x0 -#define GC_PMU_RST0_DTEMP0_OFFSET 0xd4 -#define GC_PMU_RST0_DRBOX0_LSB 0x5 -#define GC_PMU_RST0_DRBOX0_MASK 0x20 -#define GC_PMU_RST0_DRBOX0_SIZE 0x1 -#define GC_PMU_RST0_DRBOX0_DEFAULT 0x0 -#define GC_PMU_RST0_DRBOX0_OFFSET 0xd4 -#define GC_PMU_RST0_DWATCHDOG0_LSB 0x6 -#define GC_PMU_RST0_DWATCHDOG0_MASK 0x40 -#define GC_PMU_RST0_DWATCHDOG0_SIZE 0x1 -#define GC_PMU_RST0_DWATCHDOG0_DEFAULT 0x0 -#define GC_PMU_RST0_DWATCHDOG0_OFFSET 0xd4 -#define GC_PMU_RST0_DI2CS0_LSB 0x7 -#define GC_PMU_RST0_DI2CS0_MASK 0x80 -#define GC_PMU_RST0_DI2CS0_SIZE 0x1 -#define GC_PMU_RST0_DI2CS0_DEFAULT 0x0 -#define GC_PMU_RST0_DI2CS0_OFFSET 0xd4 -#define GC_PMU_RST0_DXO0_LSB 0x8 -#define GC_PMU_RST0_DXO0_MASK 0x100 -#define GC_PMU_RST0_DXO0_SIZE 0x1 -#define GC_PMU_RST0_DXO0_DEFAULT 0x0 -#define GC_PMU_RST0_DXO0_OFFSET 0xd4 -#define GC_PMU_RST0_DPAU_LSB 0x9 -#define GC_PMU_RST0_DPAU_MASK 0x200 -#define GC_PMU_RST0_DPAU_SIZE 0x1 -#define GC_PMU_RST0_DPAU_DEFAULT 0x0 -#define GC_PMU_RST0_DPAU_OFFSET 0xd4 -#define GC_PMU_RST0_DI2C1_LSB 0xa -#define GC_PMU_RST0_DI2C1_MASK 0x400 -#define GC_PMU_RST0_DI2C1_SIZE 0x1 -#define GC_PMU_RST0_DI2C1_DEFAULT 0x0 -#define GC_PMU_RST0_DI2C1_OFFSET 0xd4 -#define GC_PMU_RST0_DAES0_LSB 0xb -#define GC_PMU_RST0_DAES0_MASK 0x800 +#define GC_PMU_CLK0_TRACECLKEN_OFFSET 0x80 +#define GC_PMU_RST0_DAES0_LSB 0x0 +#define GC_PMU_RST0_DAES0_MASK 0x1 #define GC_PMU_RST0_DAES0_SIZE 0x1 #define GC_PMU_RST0_DAES0_DEFAULT 0x0 -#define GC_PMU_RST0_DAES0_OFFSET 0xd4 -#define GC_PMU_RST0_PERI1_LSB 0xc -#define GC_PMU_RST0_PERI1_MASK 0x1000 -#define GC_PMU_RST0_PERI1_SIZE 0x1 -#define GC_PMU_RST0_PERI1_DEFAULT 0x0 -#define GC_PMU_RST0_PERI1_OFFSET 0xd4 -#define GC_PMU_RST0_DUSB0_USB_PHY_CLK_LSB 0xd -#define GC_PMU_RST0_DUSB0_USB_PHY_CLK_MASK 0x2000 -#define GC_PMU_RST0_DUSB0_USB_PHY_CLK_SIZE 0x1 -#define GC_PMU_RST0_DUSB0_USB_PHY_CLK_DEFAULT 0x0 -#define GC_PMU_RST0_DUSB0_USB_PHY_CLK_OFFSET 0xd4 -#define GC_PMU_RST0_DGPIO1_LSB 0xe -#define GC_PMU_RST0_DGPIO1_MASK 0x4000 +#define GC_PMU_RST0_DAES0_OFFSET 0x84 +#define GC_PMU_RST0_DCAMO0_LSB 0x1 +#define GC_PMU_RST0_DCAMO0_MASK 0x2 +#define GC_PMU_RST0_DCAMO0_SIZE 0x1 +#define GC_PMU_RST0_DCAMO0_DEFAULT 0x0 +#define GC_PMU_RST0_DCAMO0_OFFSET 0x84 +#define GC_PMU_RST0_DCAMO0_CLK_RTC_LSB 0x2 +#define GC_PMU_RST0_DCAMO0_CLK_RTC_MASK 0x4 +#define GC_PMU_RST0_DCAMO0_CLK_RTC_SIZE 0x1 +#define GC_PMU_RST0_DCAMO0_CLK_RTC_DEFAULT 0x0 +#define GC_PMU_RST0_DCAMO0_CLK_RTC_OFFSET 0x84 +#define GC_PMU_RST0_DCRYPTO0_LSB 0x3 +#define GC_PMU_RST0_DCRYPTO0_MASK 0x8 +#define GC_PMU_RST0_DCRYPTO0_SIZE 0x1 +#define GC_PMU_RST0_DCRYPTO0_DEFAULT 0x0 +#define GC_PMU_RST0_DCRYPTO0_OFFSET 0x84 +#define GC_PMU_RST0_DDMA0_LSB 0x4 +#define GC_PMU_RST0_DDMA0_MASK 0x10 +#define GC_PMU_RST0_DDMA0_SIZE 0x1 +#define GC_PMU_RST0_DDMA0_DEFAULT 0x0 +#define GC_PMU_RST0_DDMA0_OFFSET 0x84 +#define GC_PMU_RST0_DFLASH0_LSB 0x5 +#define GC_PMU_RST0_DFLASH0_MASK 0x20 +#define GC_PMU_RST0_DFLASH0_SIZE 0x1 +#define GC_PMU_RST0_DFLASH0_DEFAULT 0x0 +#define GC_PMU_RST0_DFLASH0_OFFSET 0x84 +#define GC_PMU_RST0_DFUSE0_LSB 0x6 +#define GC_PMU_RST0_DFUSE0_MASK 0x40 +#define GC_PMU_RST0_DFUSE0_SIZE 0x1 +#define GC_PMU_RST0_DFUSE0_DEFAULT 0x0 +#define GC_PMU_RST0_DFUSE0_OFFSET 0x84 +#define GC_PMU_RST0_DGLOBALSEC_LSB 0x7 +#define GC_PMU_RST0_DGLOBALSEC_MASK 0x80 +#define GC_PMU_RST0_DGLOBALSEC_SIZE 0x1 +#define GC_PMU_RST0_DGLOBALSEC_DEFAULT 0x0 +#define GC_PMU_RST0_DGLOBALSEC_OFFSET 0x84 +#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_LSB 0x8 +#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_MASK 0x100 +#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_OFFSET 0x84 +#define GC_PMU_RST0_DGPIO0_LSB 0x9 +#define GC_PMU_RST0_DGPIO0_MASK 0x200 +#define GC_PMU_RST0_DGPIO0_SIZE 0x1 +#define GC_PMU_RST0_DGPIO0_DEFAULT 0x0 +#define GC_PMU_RST0_DGPIO0_OFFSET 0x84 +#define GC_PMU_RST0_DGPIO1_LSB 0xa +#define GC_PMU_RST0_DGPIO1_MASK 0x400 #define GC_PMU_RST0_DGPIO1_SIZE 0x1 #define GC_PMU_RST0_DGPIO1_DEFAULT 0x0 -#define GC_PMU_RST0_DGPIO1_OFFSET 0xd4 -#define GC_PMU_RST0_DUART0_LSB 0xf -#define GC_PMU_RST0_DUART0_MASK 0x8000 -#define GC_PMU_RST0_DUART0_SIZE 0x1 -#define GC_PMU_RST0_DUART0_DEFAULT 0x0 -#define GC_PMU_RST0_DUART0_OFFSET 0xd4 -#define GC_PMU_RST0_DPMU_LSB 0x10 -#define GC_PMU_RST0_DPMU_MASK 0x10000 -#define GC_PMU_RST0_DPMU_SIZE 0x1 -#define GC_PMU_RST0_DPMU_DEFAULT 0x0 -#define GC_PMU_RST0_DPMU_OFFSET 0xd4 -#define GC_PMU_RST0_DRTC0_LSB 0x11 -#define GC_PMU_RST0_DRTC0_MASK 0x20000 -#define GC_PMU_RST0_DRTC0_SIZE 0x1 -#define GC_PMU_RST0_DRTC0_DEFAULT 0x0 -#define GC_PMU_RST0_DRTC0_OFFSET 0xd4 -#define GC_PMU_RST0_DSWDP0_LSB 0x12 -#define GC_PMU_RST0_DSWDP0_MASK 0x40000 -#define GC_PMU_RST0_DSWDP0_SIZE 0x1 -#define GC_PMU_RST0_DSWDP0_DEFAULT 0x0 -#define GC_PMU_RST0_DSWDP0_OFFSET 0xd4 -#define GC_PMU_RST0_DI2C0_LSB 0x13 -#define GC_PMU_RST0_DI2C0_MASK 0x80000 -#define GC_PMU_RST0_DI2C0_SIZE 0x1 -#define GC_PMU_RST0_DI2C0_DEFAULT 0x0 -#define GC_PMU_RST0_DI2C0_OFFSET 0xd4 -#define GC_PMU_RST0_DUART2_LSB 0x14 -#define GC_PMU_RST0_DUART2_MASK 0x100000 -#define GC_PMU_RST0_DUART2_SIZE 0x1 -#define GC_PMU_RST0_DUART2_DEFAULT 0x0 -#define GC_PMU_RST0_DUART2_OFFSET 0xd4 -#define GC_PMU_RST0_DTIMELS0_LSB 0x15 -#define GC_PMU_RST0_DTIMELS0_MASK 0x200000 -#define GC_PMU_RST0_DTIMELS0_SIZE 0x1 -#define GC_PMU_RST0_DTIMELS0_DEFAULT 0x0 -#define GC_PMU_RST0_DTIMELS0_OFFSET 0xd4 -#define GC_PMU_RST0_DTRNG0_LSB 0x16 -#define GC_PMU_RST0_DTRNG0_MASK 0x400000 -#define GC_PMU_RST0_DTRNG0_SIZE 0x1 -#define GC_PMU_RST0_DTRNG0_DEFAULT 0x0 -#define GC_PMU_RST0_DTRNG0_OFFSET 0xd4 -#define GC_PMU_RST0_DMAU_LSB 0x17 -#define GC_PMU_RST0_DMAU_MASK 0x800000 +#define GC_PMU_RST0_DGPIO1_OFFSET 0x84 +#define GC_PMU_RST0_DI2C0_CLK_TIMER_LSB 0xb +#define GC_PMU_RST0_DI2C0_CLK_TIMER_MASK 0x800 +#define GC_PMU_RST0_DI2C0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST0_DI2C0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST0_DI2C0_CLK_TIMER_OFFSET 0x84 +#define GC_PMU_RST0_DI2C1_CLK_TIMER_LSB 0xc +#define GC_PMU_RST0_DI2C1_CLK_TIMER_MASK 0x1000 +#define GC_PMU_RST0_DI2C1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST0_DI2C1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST0_DI2C1_CLK_TIMER_OFFSET 0x84 +#define GC_PMU_RST0_DI2CS0_LSB 0xd +#define GC_PMU_RST0_DI2CS0_MASK 0x2000 +#define GC_PMU_RST0_DI2CS0_SIZE 0x1 +#define GC_PMU_RST0_DI2CS0_DEFAULT 0x0 +#define GC_PMU_RST0_DI2CS0_OFFSET 0x84 +#define GC_PMU_RST0_DMAU_LSB 0xe +#define GC_PMU_RST0_DMAU_MASK 0x4000 #define GC_PMU_RST0_DMAU_SIZE 0x1 #define GC_PMU_RST0_DMAU_DEFAULT 0x0 -#define GC_PMU_RST0_DMAU_OFFSET 0xd4 -#define GC_PMU_RST0_DSPS0_LSB 0x18 -#define GC_PMU_RST0_DSPS0_MASK 0x1000000 +#define GC_PMU_RST0_DMAU_OFFSET 0x84 +#define GC_PMU_RST0_DPERI_APB0_LSB 0xf +#define GC_PMU_RST0_DPERI_APB0_MASK 0x8000 +#define GC_PMU_RST0_DPERI_APB0_SIZE 0x1 +#define GC_PMU_RST0_DPERI_APB0_DEFAULT 0x0 +#define GC_PMU_RST0_DPERI_APB0_OFFSET 0x84 +#define GC_PMU_RST0_DPERI_APB1_LSB 0x10 +#define GC_PMU_RST0_DPERI_APB1_MASK 0x10000 +#define GC_PMU_RST0_DPERI_APB1_SIZE 0x1 +#define GC_PMU_RST0_DPERI_APB1_DEFAULT 0x0 +#define GC_PMU_RST0_DPERI_APB1_OFFSET 0x84 +#define GC_PMU_RST0_DPERI_APB2_LSB 0x11 +#define GC_PMU_RST0_DPERI_APB2_MASK 0x20000 +#define GC_PMU_RST0_DPERI_APB2_SIZE 0x1 +#define GC_PMU_RST0_DPERI_APB2_DEFAULT 0x0 +#define GC_PMU_RST0_DPERI_APB2_OFFSET 0x84 +#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_LSB 0x12 +#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_OFFSET 0x84 +#define GC_PMU_RST0_DPINMUX_AON_LSB 0x13 +#define GC_PMU_RST0_DPINMUX_AON_MASK 0x80000 +#define GC_PMU_RST0_DPINMUX_AON_SIZE 0x1 +#define GC_PMU_RST0_DPINMUX_AON_DEFAULT 0x0 +#define GC_PMU_RST0_DPINMUX_AON_OFFSET 0x84 +#define GC_PMU_RST0_DPMU_AON_LSB 0x14 +#define GC_PMU_RST0_DPMU_AON_MASK 0x100000 +#define GC_PMU_RST0_DPMU_AON_SIZE 0x1 +#define GC_PMU_RST0_DPMU_AON_DEFAULT 0x0 +#define GC_PMU_RST0_DPMU_AON_OFFSET 0x84 +#define GC_PMU_RST0_DRBOX0_AON_LSB 0x15 +#define GC_PMU_RST0_DRBOX0_AON_MASK 0x200000 +#define GC_PMU_RST0_DRBOX0_AON_SIZE 0x1 +#define GC_PMU_RST0_DRBOX0_AON_DEFAULT 0x0 +#define GC_PMU_RST0_DRBOX0_AON_OFFSET 0x84 +#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_LSB 0x16 +#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_MASK 0x400000 +#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_SIZE 0x1 +#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_DEFAULT 0x0 +#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_OFFSET 0x84 +#define GC_PMU_RST0_DRDD0_LSB 0x17 +#define GC_PMU_RST0_DRDD0_MASK 0x800000 +#define GC_PMU_RST0_DRDD0_SIZE 0x1 +#define GC_PMU_RST0_DRDD0_DEFAULT 0x0 +#define GC_PMU_RST0_DRDD0_OFFSET 0x84 +#define GC_PMU_RST0_DRTC0_AON_LSB 0x18 +#define GC_PMU_RST0_DRTC0_AON_MASK 0x1000000 +#define GC_PMU_RST0_DRTC0_AON_SIZE 0x1 +#define GC_PMU_RST0_DRTC0_AON_DEFAULT 0x0 +#define GC_PMU_RST0_DRTC0_AON_OFFSET 0x84 +#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_LSB 0x19 +#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_MASK 0x2000000 +#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_SIZE 0x1 +#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_DEFAULT 0x0 +#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_OFFSET 0x84 +#define GC_PMU_RST0_DSHA0_LSB 0x1a +#define GC_PMU_RST0_DSHA0_MASK 0x4000000 +#define GC_PMU_RST0_DSHA0_SIZE 0x1 +#define GC_PMU_RST0_DSHA0_DEFAULT 0x0 +#define GC_PMU_RST0_DSHA0_OFFSET 0x84 +#define GC_PMU_RST0_DSPI0_CLK_TIMER_LSB 0x1b +#define GC_PMU_RST0_DSPI0_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_RST0_DSPI0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST0_DSPI0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST0_DSPI0_CLK_TIMER_OFFSET 0x84 +#define GC_PMU_RST0_DSPI1_CLK_TIMER_LSB 0x1c +#define GC_PMU_RST0_DSPI1_CLK_TIMER_MASK 0x10000000 +#define GC_PMU_RST0_DSPI1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST0_DSPI1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST0_DSPI1_CLK_TIMER_OFFSET 0x84 +#define GC_PMU_RST0_DSPS0_LSB 0x1d +#define GC_PMU_RST0_DSPS0_MASK 0x20000000 #define GC_PMU_RST0_DSPS0_SIZE 0x1 #define GC_PMU_RST0_DSPS0_DEFAULT 0x0 -#define GC_PMU_RST0_DSPS0_OFFSET 0xd4 -#define GC_PMU_RST0_DSPI0_LSB 0x19 -#define GC_PMU_RST0_DSPI0_MASK 0x2000000 -#define GC_PMU_RST0_DSPI0_SIZE 0x1 -#define GC_PMU_RST0_DSPI0_DEFAULT 0x0 -#define GC_PMU_RST0_DSPI0_OFFSET 0xd4 -#define GC_PMU_RST0_DPINMUX_LSB 0x1a -#define GC_PMU_RST0_DPINMUX_MASK 0x4000000 -#define GC_PMU_RST0_DPINMUX_SIZE 0x1 -#define GC_PMU_RST0_DPINMUX_DEFAULT 0x0 -#define GC_PMU_RST0_DPINMUX_OFFSET 0xd4 -#define GC_PMU_RST0_DTIMEHS1_LSB 0x1b -#define GC_PMU_RST0_DTIMEHS1_MASK 0x8000000 -#define GC_PMU_RST0_DTIMEHS1_SIZE 0x1 -#define GC_PMU_RST0_DTIMEHS1_DEFAULT 0x0 -#define GC_PMU_RST0_DTIMEHS1_OFFSET 0xd4 -#define GC_PMU_RST0_DFLASH0_LSB 0x1c -#define GC_PMU_RST0_DFLASH0_MASK 0x10000000 -#define GC_PMU_RST0_DFLASH0_SIZE 0x1 -#define GC_PMU_RST0_DFLASH0_DEFAULT 0x0 -#define GC_PMU_RST0_DFLASH0_OFFSET 0xd4 -#define GC_PMU_RST0_DTIMEHS0_LSB 0x1d -#define GC_PMU_RST0_DTIMEHS0_MASK 0x20000000 -#define GC_PMU_RST0_DTIMEHS0_SIZE 0x1 -#define GC_PMU_RST0_DTIMEHS0_DEFAULT 0x0 -#define GC_PMU_RST0_DTIMEHS0_OFFSET 0xd4 -#define GC_PMU_RST0_PERI_MATRIX_LSB 0x1e -#define GC_PMU_RST0_PERI_MATRIX_MASK 0x40000000 -#define GC_PMU_RST0_PERI_MATRIX_SIZE 0x1 -#define GC_PMU_RST0_PERI_MATRIX_DEFAULT 0x0 -#define GC_PMU_RST0_PERI_MATRIX_OFFSET 0xd4 -#define GC_PMU_RST0_DCAMO0_LSB 0x1f -#define GC_PMU_RST0_DCAMO0_MASK 0x80000000 -#define GC_PMU_RST0_DCAMO0_SIZE 0x1 -#define GC_PMU_RST0_DCAMO0_DEFAULT 0x0 -#define GC_PMU_RST0_DCAMO0_OFFSET 0xd4 -#define GC_PMU_RST1_DGPIO0_LSB 0x0 -#define GC_PMU_RST1_DGPIO0_MASK 0x1 -#define GC_PMU_RST1_DGPIO0_SIZE 0x1 -#define GC_PMU_RST1_DGPIO0_DEFAULT 0x0 -#define GC_PMU_RST1_DGPIO0_OFFSET 0xd8 -#define GC_PMU_RST1_DAES1_LSB 0x1 -#define GC_PMU_RST1_DAES1_MASK 0x2 -#define GC_PMU_RST1_DAES1_SIZE 0x1 -#define GC_PMU_RST1_DAES1_DEFAULT 0x0 -#define GC_PMU_RST1_DAES1_OFFSET 0xd8 +#define GC_PMU_RST0_DSPS0_OFFSET 0x84 +#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_LSB 0x1e +#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_MASK 0x40000000 +#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0 +#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_OFFSET 0x84 +#define GC_PMU_RST0_DSWDP0_LSB 0x1f +#define GC_PMU_RST0_DSWDP0_MASK 0x80000000 +#define GC_PMU_RST0_DSWDP0_SIZE 0x1 +#define GC_PMU_RST0_DSWDP0_DEFAULT 0x0 +#define GC_PMU_RST0_DSWDP0_OFFSET 0x84 +#define GC_PMU_RST1_DTEMP0_LSB 0x0 +#define GC_PMU_RST1_DTEMP0_MASK 0x1 +#define GC_PMU_RST1_DTEMP0_SIZE 0x1 +#define GC_PMU_RST1_DTEMP0_DEFAULT 0x0 +#define GC_PMU_RST1_DTEMP0_OFFSET 0x88 +#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_MASK 0x2 +#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_OFFSET 0x88 +#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_LSB 0x2 +#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_MASK 0x4 +#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_OFFSET 0x88 +#define GC_PMU_RST1_DTIMELS0_AON_LSB 0x3 +#define GC_PMU_RST1_DTIMELS0_AON_MASK 0x8 +#define GC_PMU_RST1_DTIMELS0_AON_SIZE 0x1 +#define GC_PMU_RST1_DTIMELS0_AON_DEFAULT 0x0 +#define GC_PMU_RST1_DTIMELS0_AON_OFFSET 0x88 +#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_LSB 0x4 +#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_MASK 0x10 +#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_SIZE 0x1 +#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_DEFAULT 0x0 +#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_OFFSET 0x88 +#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_LSB 0x5 +#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_MASK 0x20 +#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_OFFSET 0x88 +#define GC_PMU_RST1_DTRNG0_LSB 0x6 +#define GC_PMU_RST1_DTRNG0_MASK 0x40 +#define GC_PMU_RST1_DTRNG0_SIZE 0x1 +#define GC_PMU_RST1_DTRNG0_DEFAULT 0x0 +#define GC_PMU_RST1_DTRNG0_OFFSET 0x88 +#define GC_PMU_RST1_DUART0_CLK_TIMER_LSB 0x7 +#define GC_PMU_RST1_DUART0_CLK_TIMER_MASK 0x80 +#define GC_PMU_RST1_DUART0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST1_DUART0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST1_DUART0_CLK_TIMER_OFFSET 0x88 +#define GC_PMU_RST1_DUART1_CLK_TIMER_LSB 0x8 +#define GC_PMU_RST1_DUART1_CLK_TIMER_MASK 0x100 +#define GC_PMU_RST1_DUART1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST1_DUART1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST1_DUART1_CLK_TIMER_OFFSET 0x88 +#define GC_PMU_RST1_DUART2_CLK_TIMER_LSB 0x9 +#define GC_PMU_RST1_DUART2_CLK_TIMER_MASK 0x200 +#define GC_PMU_RST1_DUART2_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST1_DUART2_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST1_DUART2_CLK_TIMER_OFFSET 0x88 +#define GC_PMU_RST1_DUSB0_LSB 0xa +#define GC_PMU_RST1_DUSB0_MASK 0x400 +#define GC_PMU_RST1_DUSB0_SIZE 0x1 +#define GC_PMU_RST1_DUSB0_DEFAULT 0x0 +#define GC_PMU_RST1_DUSB0_OFFSET 0x88 +#define GC_PMU_RST1_DUSB0_AON_LSB 0xb +#define GC_PMU_RST1_DUSB0_AON_MASK 0x800 +#define GC_PMU_RST1_DUSB0_AON_SIZE 0x1 +#define GC_PMU_RST1_DUSB0_AON_DEFAULT 0x0 +#define GC_PMU_RST1_DUSB0_AON_OFFSET 0x88 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_LSB 0xc +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_MASK 0x1000 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_SIZE 0x1 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_OFFSET 0x88 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_LSB 0xd +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_MASK 0x2000 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_SIZE 0x1 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_DEFAULT 0x0 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_OFFSET 0x88 +#define GC_PMU_RST1_DVOLT0_LSB 0xe +#define GC_PMU_RST1_DVOLT0_MASK 0x4000 +#define GC_PMU_RST1_DVOLT0_SIZE 0x1 +#define GC_PMU_RST1_DVOLT0_DEFAULT 0x0 +#define GC_PMU_RST1_DVOLT0_OFFSET 0x88 +#define GC_PMU_RST1_DWATCHDOG0_LSB 0xf +#define GC_PMU_RST1_DWATCHDOG0_MASK 0x8000 +#define GC_PMU_RST1_DWATCHDOG0_SIZE 0x1 +#define GC_PMU_RST1_DWATCHDOG0_DEFAULT 0x0 +#define GC_PMU_RST1_DWATCHDOG0_OFFSET 0x88 +#define GC_PMU_RST1_DXO0_AON_LSB 0x10 +#define GC_PMU_RST1_DXO0_AON_MASK 0x10000 +#define GC_PMU_RST1_DXO0_AON_SIZE 0x1 +#define GC_PMU_RST1_DXO0_AON_DEFAULT 0x0 +#define GC_PMU_RST1_DXO0_AON_OFFSET 0x88 +#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_LSB 0x11 +#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_MASK 0x20000 +#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_SIZE 0x1 +#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_DEFAULT 0x0 +#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_OFFSET 0x88 +#define GC_PMU_RST1_PERI_MASTER_MATRIX_LSB 0x12 +#define GC_PMU_RST1_PERI_MASTER_MATRIX_MASK 0x40000 +#define GC_PMU_RST1_PERI_MASTER_MATRIX_SIZE 0x1 +#define GC_PMU_RST1_PERI_MASTER_MATRIX_DEFAULT 0x0 +#define GC_PMU_RST1_PERI_MASTER_MATRIX_OFFSET 0x88 +#define GC_PMU_RST1_PERI_MATRIX_LSB 0x13 +#define GC_PMU_RST1_PERI_MATRIX_MASK 0x80000 +#define GC_PMU_RST1_PERI_MATRIX_SIZE 0x1 +#define GC_PMU_RST1_PERI_MATRIX_DEFAULT 0x0 +#define GC_PMU_RST1_PERI_MATRIX_OFFSET 0x88 +#define GC_PMU_RST1_SEC_FABRIC_LSB 0x14 +#define GC_PMU_RST1_SEC_FABRIC_MASK 0x100000 +#define GC_PMU_RST1_SEC_FABRIC_SIZE 0x1 +#define GC_PMU_RST1_SEC_FABRIC_DEFAULT 0x0 +#define GC_PMU_RST1_SEC_FABRIC_OFFSET 0x88 +#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_LSB 0x15 +#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_MASK 0x200000 +#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_OFFSET 0x88 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_LSB 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_MASK 0x1 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_SIZE 0x1 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_OFFSET 0x10c +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_LSB 0x1 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_MASK 0x2 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_SIZE 0x1 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_OFFSET 0x10c +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_LSB 0x2 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_MASK 0x4 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_SIZE 0x1 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_OFFSET 0x10c +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_LSB 0x3 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_MASK 0x8 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_SIZE 0x1 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_OFFSET 0x10c #define GC_PMU_FUSE_CTRL_WRITE_LSB 0x0 #define GC_PMU_FUSE_CTRL_WRITE_MASK 0x1 #define GC_PMU_FUSE_CTRL_WRITE_SIZE 0x1 #define GC_PMU_FUSE_CTRL_WRITE_DEFAULT 0x0 -#define GC_PMU_FUSE_CTRL_WRITE_OFFSET 0x100 +#define GC_PMU_FUSE_CTRL_WRITE_OFFSET 0x128 #define GC_PMU_FUSE_WR_ID_PKG_LSB 0x0 #define GC_PMU_FUSE_WR_ID_PKG_MASK 0x7 #define GC_PMU_FUSE_WR_ID_PKG_SIZE 0x3 #define GC_PMU_FUSE_WR_ID_PKG_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_ID_PKG_OFFSET 0x10c +#define GC_PMU_FUSE_WR_ID_PKG_OFFSET 0x134 #define GC_PMU_FUSE_WR_ID_BIN_LSB 0x3 #define GC_PMU_FUSE_WR_ID_BIN_MASK 0x38 #define GC_PMU_FUSE_WR_ID_BIN_SIZE 0x3 #define GC_PMU_FUSE_WR_ID_BIN_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_ID_BIN_OFFSET 0x10c +#define GC_PMU_FUSE_WR_ID_BIN_OFFSET 0x134 #define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_LSB 0x0 #define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_MASK 0xfffffff #define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_SIZE 0x1c #define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_OFFSET 0x110 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_OFFSET 0x138 #define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_LSB 0x1c #define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_MASK 0x10000000 #define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_SIZE 0x1 #define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_OFFSET 0x110 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_OFFSET 0x138 #define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_LSB 0x0 #define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_MASK 0xff #define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_SIZE 0x8 #define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_OFFSET 0x114 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_OFFSET 0x13c #define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_LSB 0x8 #define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_MASK 0x100 #define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_SIZE 0x1 #define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_OFFSET 0x114 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_OFFSET 0x13c #define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_LSB 0x0 #define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_MASK 0xf #define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_SIZE 0x4 #define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_OFFSET 0x118 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_OFFSET 0x140 #define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_LSB 0x4 #define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_MASK 0x10 #define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_SIZE 0x1 #define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_OFFSET 0x118 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_OFFSET 0x140 #define GC_PMU_FUSE_WR_LOCK_TESTMODE_LSB 0x0 #define GC_PMU_FUSE_WR_LOCK_TESTMODE_MASK 0x1 #define GC_PMU_FUSE_WR_LOCK_TESTMODE_SIZE 0x1 #define GC_PMU_FUSE_WR_LOCK_TESTMODE_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_LOCK_TESTMODE_OFFSET 0x11c +#define GC_PMU_FUSE_WR_LOCK_TESTMODE_OFFSET 0x144 #define GC_PMU_FUSE_WR_LOCK_DAP_LSB 0x1 #define GC_PMU_FUSE_WR_LOCK_DAP_MASK 0x2 #define GC_PMU_FUSE_WR_LOCK_DAP_SIZE 0x1 #define GC_PMU_FUSE_WR_LOCK_DAP_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_LOCK_DAP_OFFSET 0x11c +#define GC_PMU_FUSE_WR_LOCK_DAP_OFFSET 0x144 #define GC_PMU_FUSE_WR_LOCK_FUSE_LSB 0x2 #define GC_PMU_FUSE_WR_LOCK_FUSE_MASK 0x4 #define GC_PMU_FUSE_WR_LOCK_FUSE_SIZE 0x1 #define GC_PMU_FUSE_WR_LOCK_FUSE_DEFAULT 0x0 -#define GC_PMU_FUSE_WR_LOCK_FUSE_OFFSET 0x11c +#define GC_PMU_FUSE_WR_LOCK_FUSE_OFFSET 0x144 #define GC_PMU_FUSE_RD_ID_PKG_LSB 0x0 #define GC_PMU_FUSE_RD_ID_PKG_MASK 0x7 #define GC_PMU_FUSE_RD_ID_PKG_SIZE 0x3 #define GC_PMU_FUSE_RD_ID_PKG_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_ID_PKG_OFFSET 0x13c +#define GC_PMU_FUSE_RD_ID_PKG_OFFSET 0x164 #define GC_PMU_FUSE_RD_ID_BIN_LSB 0x3 #define GC_PMU_FUSE_RD_ID_BIN_MASK 0x38 #define GC_PMU_FUSE_RD_ID_BIN_SIZE 0x3 #define GC_PMU_FUSE_RD_ID_BIN_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_ID_BIN_OFFSET 0x13c +#define GC_PMU_FUSE_RD_ID_BIN_OFFSET 0x164 #define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_LSB 0x0 #define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_MASK 0xfffffff #define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_SIZE 0x1c #define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_OFFSET 0x140 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_OFFSET 0x168 #define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_LSB 0x1c #define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_MASK 0x10000000 #define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_SIZE 0x1 #define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_OFFSET 0x140 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_OFFSET 0x168 #define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_LSB 0x0 #define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_MASK 0xff #define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_SIZE 0x8 #define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_OFFSET 0x144 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_OFFSET 0x16c #define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_LSB 0x8 #define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_MASK 0x100 #define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_SIZE 0x1 #define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_OFFSET 0x144 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_OFFSET 0x16c #define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_LSB 0x0 #define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_MASK 0xf #define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_SIZE 0x4 #define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_OFFSET 0x148 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_OFFSET 0x170 #define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_LSB 0x4 #define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_MASK 0x10 #define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_SIZE 0x1 #define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_OFFSET 0x148 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_OFFSET 0x170 #define GC_PMU_FUSE_RD_LOCK_TESTMODE_LSB 0x0 #define GC_PMU_FUSE_RD_LOCK_TESTMODE_MASK 0x1 #define GC_PMU_FUSE_RD_LOCK_TESTMODE_SIZE 0x1 #define GC_PMU_FUSE_RD_LOCK_TESTMODE_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_LOCK_TESTMODE_OFFSET 0x14c +#define GC_PMU_FUSE_RD_LOCK_TESTMODE_OFFSET 0x174 #define GC_PMU_FUSE_RD_LOCK_DAP_LSB 0x1 #define GC_PMU_FUSE_RD_LOCK_DAP_MASK 0x2 #define GC_PMU_FUSE_RD_LOCK_DAP_SIZE 0x1 #define GC_PMU_FUSE_RD_LOCK_DAP_DEFAULT 0x1 -#define GC_PMU_FUSE_RD_LOCK_DAP_OFFSET 0x14c +#define GC_PMU_FUSE_RD_LOCK_DAP_OFFSET 0x174 #define GC_PMU_FUSE_RD_LOCK_FUSE_LSB 0x2 #define GC_PMU_FUSE_RD_LOCK_FUSE_MASK 0x4 #define GC_PMU_FUSE_RD_LOCK_FUSE_SIZE 0x1 #define GC_PMU_FUSE_RD_LOCK_FUSE_DEFAULT 0x0 -#define GC_PMU_FUSE_RD_LOCK_FUSE_OFFSET 0x14c +#define GC_PMU_FUSE_RD_LOCK_FUSE_OFFSET 0x174 #define GC_PMU_FUSE_TIMING_WRITE_LSB 0x0 #define GC_PMU_FUSE_TIMING_WRITE_MASK 0xffff #define GC_PMU_FUSE_TIMING_WRITE_SIZE 0x10 #define GC_PMU_FUSE_TIMING_WRITE_DEFAULT 0x7d -#define GC_PMU_FUSE_TIMING_WRITE_OFFSET 0x164 +#define GC_PMU_FUSE_TIMING_WRITE_OFFSET 0x18c #define GC_PMU_FUSE_TIMING_READ_LSB 0x10 #define GC_PMU_FUSE_TIMING_READ_MASK 0xffff0000 #define GC_PMU_FUSE_TIMING_READ_SIZE 0x10 #define GC_PMU_FUSE_TIMING_READ_DEFAULT 0x8 -#define GC_PMU_FUSE_TIMING_READ_OFFSET 0x164 +#define GC_PMU_FUSE_TIMING_READ_OFFSET 0x18c #define GC_PMU_FUSE_OVRD_CSB_LSB 0x0 #define GC_PMU_FUSE_OVRD_CSB_MASK 0x1 #define GC_PMU_FUSE_OVRD_CSB_SIZE 0x1 #define GC_PMU_FUSE_OVRD_CSB_DEFAULT 0x1 -#define GC_PMU_FUSE_OVRD_CSB_OFFSET 0x16c +#define GC_PMU_FUSE_OVRD_CSB_OFFSET 0x194 #define GC_PMU_FUSE_OVRD_PGM_LSB 0x1 #define GC_PMU_FUSE_OVRD_PGM_MASK 0x2 #define GC_PMU_FUSE_OVRD_PGM_SIZE 0x1 #define GC_PMU_FUSE_OVRD_PGM_DEFAULT 0x0 -#define GC_PMU_FUSE_OVRD_PGM_OFFSET 0x16c +#define GC_PMU_FUSE_OVRD_PGM_OFFSET 0x194 #define GC_PMU_FUSE_OVRD_SCK_LSB 0x2 #define GC_PMU_FUSE_OVRD_SCK_MASK 0x4 #define GC_PMU_FUSE_OVRD_SCK_SIZE 0x1 #define GC_PMU_FUSE_OVRD_SCK_DEFAULT 0x0 -#define GC_PMU_FUSE_OVRD_SCK_OFFSET 0x16c +#define GC_PMU_FUSE_OVRD_SCK_OFFSET 0x194 #define GC_PMU_FUSE_DBG_STATE_LSB 0x0 #define GC_PMU_FUSE_DBG_STATE_MASK 0xf #define GC_PMU_FUSE_DBG_STATE_SIZE 0x4 #define GC_PMU_FUSE_DBG_STATE_DEFAULT 0x0 -#define GC_PMU_FUSE_DBG_STATE_OFFSET 0x170 +#define GC_PMU_FUSE_DBG_STATE_OFFSET 0x198 #define GC_PMU_FUSE_DBG_IDLE_LSB 0x4 #define GC_PMU_FUSE_DBG_IDLE_MASK 0x10 #define GC_PMU_FUSE_DBG_IDLE_SIZE 0x1 #define GC_PMU_FUSE_DBG_IDLE_DEFAULT 0x0 -#define GC_PMU_FUSE_DBG_IDLE_OFFSET 0x170 -#define GC_PMU_ICTRL_SLEEP_LSB 0x0 -#define GC_PMU_ICTRL_SLEEP_MASK 0x1 -#define GC_PMU_ICTRL_SLEEP_SIZE 0x1 -#define GC_PMU_ICTRL_SLEEP_DEFAULT 0x0 -#define GC_PMU_ICTRL_SLEEP_OFFSET 0x174 -#define GC_PMU_ISTAT_SLEEP_LSB 0x0 -#define GC_PMU_ISTAT_SLEEP_MASK 0x1 -#define GC_PMU_ISTAT_SLEEP_SIZE 0x1 -#define GC_PMU_ISTAT_SLEEP_DEFAULT 0x0 -#define GC_PMU_ISTAT_SLEEP_OFFSET 0x178 -#define GC_PMU_ISTAT_HIBER_LSB 0x1 -#define GC_PMU_ISTAT_HIBER_MASK 0x2 -#define GC_PMU_ISTAT_HIBER_SIZE 0x1 -#define GC_PMU_ISTAT_HIBER_DEFAULT 0x0 -#define GC_PMU_ISTAT_HIBER_OFFSET 0x178 -#define GC_PMU_ISTAT_PWRDN_LSB 0x2 -#define GC_PMU_ISTAT_PWRDN_MASK 0x4 -#define GC_PMU_ISTAT_PWRDN_SIZE 0x1 -#define GC_PMU_ISTAT_PWRDN_DEFAULT 0x0 -#define GC_PMU_ISTAT_PWRDN_OFFSET 0x178 +#define GC_PMU_FUSE_DBG_IDLE_OFFSET 0x198 +#define GC_PMU_INT_ENABLE_INTR_WAKEUP_LSB 0x0 +#define GC_PMU_INT_ENABLE_INTR_WAKEUP_MASK 0x1 +#define GC_PMU_INT_ENABLE_INTR_WAKEUP_SIZE 0x1 +#define GC_PMU_INT_ENABLE_INTR_WAKEUP_DEFAULT 0x0 +#define GC_PMU_INT_ENABLE_INTR_WAKEUP_OFFSET 0x19c +#define GC_PMU_INT_STATE_INTR_WAKEUP_LSB 0x0 +#define GC_PMU_INT_STATE_INTR_WAKEUP_MASK 0x1 +#define GC_PMU_INT_STATE_INTR_WAKEUP_SIZE 0x1 +#define GC_PMU_INT_STATE_INTR_WAKEUP_DEFAULT 0x0 +#define GC_PMU_INT_STATE_INTR_WAKEUP_OFFSET 0x1a0 +#define GC_PMU_INT_TEST_INTR_WAKEUP_LSB 0x0 +#define GC_PMU_INT_TEST_INTR_WAKEUP_MASK 0x1 +#define GC_PMU_INT_TEST_INTR_WAKEUP_SIZE 0x1 +#define GC_PMU_INT_TEST_INTR_WAKEUP_DEFAULT 0x0 +#define GC_PMU_INT_TEST_INTR_WAKEUP_OFFSET 0x1a4 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_LSB 0x0 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_MASK 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_SIZE 0x1 @@ -9297,56 +13804,31 @@ #define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_SIZE 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_DEFAULT 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_OFFSET 0x1008 -#define GC_PMU_HW_CONTROLS_LNA_PDB_LSB 0x0 -#define GC_PMU_HW_CONTROLS_LNA_PDB_MASK 0x1 -#define GC_PMU_HW_CONTROLS_LNA_PDB_SIZE 0x1 -#define GC_PMU_HW_CONTROLS_LNA_PDB_DEFAULT 0x0 -#define GC_PMU_HW_CONTROLS_LNA_PDB_OFFSET 0x101c -#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_LSB 0x1 -#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_MASK 0x2 -#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_SIZE 0x1 -#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_DEFAULT 0x0 -#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_OFFSET 0x101c -#define GC_PMU_HW_CONTROLS_AUXADC_PDB_LSB 0x2 -#define GC_PMU_HW_CONTROLS_AUXADC_PDB_MASK 0x4 -#define GC_PMU_HW_CONTROLS_AUXADC_PDB_SIZE 0x1 -#define GC_PMU_HW_CONTROLS_AUXADC_PDB_DEFAULT 0x0 -#define GC_PMU_HW_CONTROLS_AUXADC_PDB_OFFSET 0x101c -#define GC_PMU_HW_CONTROLS_PA_PDB_LSB 0x3 -#define GC_PMU_HW_CONTROLS_PA_PDB_MASK 0x8 -#define GC_PMU_HW_CONTROLS_PA_PDB_SIZE 0x1 -#define GC_PMU_HW_CONTROLS_PA_PDB_DEFAULT 0x0 -#define GC_PMU_HW_CONTROLS_PA_PDB_OFFSET 0x101c -#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_LSB 0x4 -#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_MASK 0x10 -#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_SIZE 0x1 -#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_DEFAULT 0x0 -#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_OFFSET 0x101c #define GC_PMU_ANTEST_TRNG_VLDO_EN_LSB 0x0 #define GC_PMU_ANTEST_TRNG_VLDO_EN_MASK 0x1 #define GC_PMU_ANTEST_TRNG_VLDO_EN_SIZE 0x1 #define GC_PMU_ANTEST_TRNG_VLDO_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TRNG_VLDO_EN_OFFSET 0x1024 +#define GC_PMU_ANTEST_TRNG_VLDO_EN_OFFSET 0x101c #define GC_PMU_ANTEST_TEMP_DIFF_EN_LSB 0x0 #define GC_PMU_ANTEST_TEMP_DIFF_EN_MASK 0x1 #define GC_PMU_ANTEST_TEMP_DIFF_EN_SIZE 0x1 #define GC_PMU_ANTEST_TEMP_DIFF_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_DIFF_EN_OFFSET 0x1028 +#define GC_PMU_ANTEST_TEMP_DIFF_EN_OFFSET 0x1020 #define GC_PMU_ANTEST_TEMP_CM_EN_LSB 0x1 #define GC_PMU_ANTEST_TEMP_CM_EN_MASK 0x2 #define GC_PMU_ANTEST_TEMP_CM_EN_SIZE 0x1 #define GC_PMU_ANTEST_TEMP_CM_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_CM_EN_OFFSET 0x1028 +#define GC_PMU_ANTEST_TEMP_CM_EN_OFFSET 0x1020 #define GC_PMU_ANTEST_TEMP_REF_EN_LSB 0x2 #define GC_PMU_ANTEST_TEMP_REF_EN_MASK 0x4 #define GC_PMU_ANTEST_TEMP_REF_EN_SIZE 0x1 #define GC_PMU_ANTEST_TEMP_REF_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_REF_EN_OFFSET 0x1028 +#define GC_PMU_ANTEST_TEMP_REF_EN_OFFSET 0x1020 #define GC_PMU_ANTEST_TEMP_VPTAT_EN_LSB 0x3 #define GC_PMU_ANTEST_TEMP_VPTAT_EN_MASK 0x8 #define GC_PMU_ANTEST_TEMP_VPTAT_EN_SIZE 0x1 #define GC_PMU_ANTEST_TEMP_VPTAT_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_VPTAT_EN_OFFSET 0x1028 +#define GC_PMU_ANTEST_TEMP_VPTAT_EN_OFFSET 0x1020 #define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_LSB 0x0 #define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_MASK 0xf #define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_SIZE 0x4 @@ -9357,6 +13839,11 @@ #define GC_PMU_TESTBUS_CTRL_TEST_MUX_SUB_CTRL_SIZE 0x4 #define GC_PMU_TESTBUS_CTRL_TEST_MUX_SUB_CTRL_DEFAULT 0x0 #define GC_PMU_TESTBUS_CTRL_TEST_MUX_SUB_CTRL_OFFSET 0x2000 +#define GC_PMU_TESTBUS_CTRL_BOUT_EN_LSB 0x8 +#define GC_PMU_TESTBUS_CTRL_BOUT_EN_MASK 0x100 +#define GC_PMU_TESTBUS_CTRL_BOUT_EN_SIZE 0x1 +#define GC_PMU_TESTBUS_CTRL_BOUT_EN_DEFAULT 0x0 +#define GC_PMU_TESTBUS_CTRL_BOUT_EN_OFFSET 0x2000 #define GC_PMU_CHIP_ID_JTAG_STANDARD_LSB 0x0 #define GC_PMU_CHIP_ID_JTAG_STANDARD_MASK 0x1 #define GC_PMU_CHIP_ID_JTAG_STANDARD_SIZE 0x1 @@ -9380,58 +13867,638 @@ #define GC_PMU_VERSION_CHANGE_LSB 0x0 #define GC_PMU_VERSION_CHANGE_MASK 0xffffff #define GC_PMU_VERSION_CHANGE_SIZE 0x18 -#define GC_PMU_VERSION_CHANGE_DEFAULT 0xc244 +#define GC_PMU_VERSION_CHANGE_DEFAULT 0x10370 #define GC_PMU_VERSION_CHANGE_OFFSET 0x1fffc #define GC_PMU_VERSION_REVISION_LSB 0x18 #define GC_PMU_VERSION_REVISION_MASK 0xff000000 #define GC_PMU_VERSION_REVISION_SIZE 0x8 -#define GC_PMU_VERSION_REVISION_DEFAULT 0x11 +#define GC_PMU_VERSION_REVISION_DEFAULT 0x1f #define GC_PMU_VERSION_REVISION_OFFSET 0x1fffc +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_LSB 0x0 +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_MASK 0x1 +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_LSB 0x1 +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_MASK 0x2 +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_LSB 0x2 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_MASK 0x4 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_LSB 0x3 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_MASK 0x8 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_LSB 0x4 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_MASK 0x10 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_LSB 0x5 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_MASK 0x20 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_LSB 0x6 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_MASK 0x40 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_LSB 0x7 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_MASK 0x80 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_LSB 0x8 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_MASK 0x100 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_LSB 0x9 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_MASK 0x200 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_LSB 0xa +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_MASK 0x400 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_LSB 0xb +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_MASK 0x800 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_LSB 0xc +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_MASK 0x1000 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_LSB 0xd +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_MASK 0x2000 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_LSB 0xe +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_MASK 0x4000 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_OFFSET 0x0 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_LSB 0x0 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_MASK 0x1 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_LSB 0x1 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_MASK 0x2 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_LSB 0x2 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_MASK 0x4 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_LSB 0x3 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_MASK 0x8 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_LSB 0x4 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_MASK 0x10 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_LSB 0x5 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_MASK 0x20 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_LSB 0x6 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_MASK 0x40 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_LSB 0x7 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_MASK 0x80 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_LSB 0x8 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_MASK 0x100 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_LSB 0x9 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_MASK 0x200 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_LSB 0xa +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_MASK 0x400 +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_LSB 0xb +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_MASK 0x800 +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_LSB 0xc +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_MASK 0x1000 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_LSB 0xd +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_MASK 0x2000 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_LSB 0xe +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_MASK 0x4000 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_OFFSET 0x4 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_LSB 0x0 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_MASK 0x1 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_LSB 0x1 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_MASK 0x2 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_LSB 0x2 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_MASK 0x4 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_LSB 0x3 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_MASK 0x8 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_LSB 0x4 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_MASK 0x10 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_LSB 0x5 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_MASK 0x20 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_LSB 0x6 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_MASK 0x40 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_LSB 0x7 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_MASK 0x80 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_LSB 0x8 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_MASK 0x100 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_LSB 0x9 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_MASK 0x200 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_LSB 0xa +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_MASK 0x400 +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_LSB 0xb +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_MASK 0x800 +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_LSB 0xc +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_MASK 0x1000 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_LSB 0xd +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_MASK 0x2000 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_LSB 0xe +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_MASK 0x4000 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_OFFSET 0x8 +#define GC_RBOX_OVERRIDE_OUTPUT_EN_LSB 0x0 +#define GC_RBOX_OVERRIDE_OUTPUT_EN_MASK 0x7f +#define GC_RBOX_OVERRIDE_OUTPUT_EN_SIZE 0x7 +#define GC_RBOX_OVERRIDE_OUTPUT_EN_DEFAULT 0x0 +#define GC_RBOX_OVERRIDE_OUTPUT_EN_OFFSET 0x18 +#define GC_RBOX_OVERRIDE_OUTPUT_VAL_LSB 0x7 +#define GC_RBOX_OVERRIDE_OUTPUT_VAL_MASK 0x3f80 +#define GC_RBOX_OVERRIDE_OUTPUT_VAL_SIZE 0x7 +#define GC_RBOX_OVERRIDE_OUTPUT_VAL_DEFAULT 0x0 +#define GC_RBOX_OVERRIDE_OUTPUT_VAL_OFFSET 0x18 +#define GC_RBOX_OVERRIDE_OUTPUT_OEN_LSB 0xe +#define GC_RBOX_OVERRIDE_OUTPUT_OEN_MASK 0x1fc000 +#define GC_RBOX_OVERRIDE_OUTPUT_OEN_SIZE 0x7 +#define GC_RBOX_OVERRIDE_OUTPUT_OEN_DEFAULT 0x0 +#define GC_RBOX_OVERRIDE_OUTPUT_OEN_OFFSET 0x18 +#define GC_RBOX_CHECK_IO_INPUTS_LSB 0x0 +#define GC_RBOX_CHECK_IO_INPUTS_MASK 0x3f +#define GC_RBOX_CHECK_IO_INPUTS_SIZE 0x6 +#define GC_RBOX_CHECK_IO_INPUTS_DEFAULT 0x0 +#define GC_RBOX_CHECK_IO_INPUTS_OFFSET 0x1c +#define GC_RBOX_CHECK_IO_OUTPUTS_LSB 0x6 +#define GC_RBOX_CHECK_IO_OUTPUTS_MASK 0x1fc0 +#define GC_RBOX_CHECK_IO_OUTPUTS_SIZE 0x7 +#define GC_RBOX_CHECK_IO_OUTPUTS_DEFAULT 0x0 +#define GC_RBOX_CHECK_IO_OUTPUTS_OFFSET 0x1c +#define GC_RBOX_CHECK_IO_OENS_LSB 0xd +#define GC_RBOX_CHECK_IO_OENS_MASK 0xfe000 +#define GC_RBOX_CHECK_IO_OENS_SIZE 0x7 +#define GC_RBOX_CHECK_IO_OENS_DEFAULT 0x0 +#define GC_RBOX_CHECK_IO_OENS_OFFSET 0x1c +#define GC_RBOX_STATUS_FUSE_READY_LSB 0x0 +#define GC_RBOX_STATUS_FUSE_READY_MASK 0x1 +#define GC_RBOX_STATUS_FUSE_READY_SIZE 0x1 +#define GC_RBOX_STATUS_FUSE_READY_DEFAULT 0x0 +#define GC_RBOX_STATUS_FUSE_READY_OFFSET 0x20 +#define GC_RBOX_STATUS_FUSE_ERROR_LSB 0x1 +#define GC_RBOX_STATUS_FUSE_ERROR_MASK 0x2 +#define GC_RBOX_STATUS_FUSE_ERROR_SIZE 0x1 +#define GC_RBOX_STATUS_FUSE_ERROR_DEFAULT 0x0 +#define GC_RBOX_STATUS_FUSE_ERROR_OFFSET 0x20 +#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_LSB 0x2 +#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_MASK 0x4 +#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_SIZE 0x1 +#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_DEFAULT 0x0 +#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_OFFSET 0x20 +#define GC_RBOX_FUSE_CTRL_ASSERT_FUSE_ERROR_LSB 0x0 +#define GC_RBOX_FUSE_CTRL_ASSERT_FUSE_ERROR_MASK 0x1 +#define GC_RBOX_FUSE_CTRL_ASSERT_FUSE_ERROR_SIZE 0x1 +#define GC_RBOX_FUSE_CTRL_ASSERT_FUSE_ERROR_DEFAULT 0x0 +#define GC_RBOX_FUSE_CTRL_ASSERT_FUSE_ERROR_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_LSB 0x1 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_MASK 0x2 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_SIZE 0x1 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_DEFAULT 0x0 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_LSB 0x2 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_MASK 0x4 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_SIZE 0x1 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_DEFAULT 0x0 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_USE_SILEGO_LSB 0x3 +#define GC_RBOX_FUSE_CTRL_USE_SILEGO_MASK 0x8 +#define GC_RBOX_FUSE_CTRL_USE_SILEGO_SIZE 0x1 +#define GC_RBOX_FUSE_CTRL_USE_SILEGO_DEFAULT 0x0 +#define GC_RBOX_FUSE_CTRL_USE_SILEGO_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_LSB 0x4 +#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_MASK 0x10 +#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_SIZE 0x1 +#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_DEFAULT 0x0 +#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_OFFSET 0x24 +#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_LSB 0x0 +#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_MASK 0xff +#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_SIZE 0x8 +#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_DEFAULT 0xc0 +#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_OFFSET 0x2c +#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_LSB 0x8 +#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_MASK 0xff00 +#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_SIZE 0x8 +#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_DEFAULT 0x63 +#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_OFFSET 0x2c +#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_LSB 0x0 +#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_MASK 0xff +#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_SIZE 0x8 +#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_DEFAULT 0x0 +#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_OFFSET 0x30 +#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_LSB 0x8 +#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_MASK 0xff00 +#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_SIZE 0x8 +#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_DEFAULT 0x63 +#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_OFFSET 0x30 +#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_LSB 0x0 +#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_MASK 0xff +#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_SIZE 0x8 +#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_DEFAULT 0x0 +#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_OFFSET 0x34 +#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_LSB 0x8 +#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_MASK 0xff00 +#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_SIZE 0x8 +#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_DEFAULT 0x63 +#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_OFFSET 0x34 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_LSB 0x0 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_MASK 0x1 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_SIZE 0x1 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_DEFAULT 0x0 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_OFFSET 0x38 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_LSB 0x1 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_MASK 0x2 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_SIZE 0x1 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_DEFAULT 0x0 +#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_OFFSET 0x38 +#define GC_RBOX_DEBUG_POL_PWRB_IN_LSB 0x0 +#define GC_RBOX_DEBUG_POL_PWRB_IN_MASK 0x1 +#define GC_RBOX_DEBUG_POL_PWRB_IN_SIZE 0x1 +#define GC_RBOX_DEBUG_POL_PWRB_IN_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_PWRB_IN_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_PWRB_OUT_LSB 0x1 +#define GC_RBOX_DEBUG_POL_PWRB_OUT_MASK 0x2 +#define GC_RBOX_DEBUG_POL_PWRB_OUT_SIZE 0x1 +#define GC_RBOX_DEBUG_POL_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_PWRB_OUT_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_KEY0_IN_LSB 0x2 +#define GC_RBOX_DEBUG_POL_KEY0_IN_MASK 0x4 +#define GC_RBOX_DEBUG_POL_KEY0_IN_SIZE 0x1 +#define GC_RBOX_DEBUG_POL_KEY0_IN_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_KEY0_IN_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_KEY0_OUT_LSB 0x3 +#define GC_RBOX_DEBUG_POL_KEY0_OUT_MASK 0x8 +#define GC_RBOX_DEBUG_POL_KEY0_OUT_SIZE 0x1 +#define GC_RBOX_DEBUG_POL_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_KEY0_OUT_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_KEY1_IN_LSB 0x4 +#define GC_RBOX_DEBUG_POL_KEY1_IN_MASK 0x10 +#define GC_RBOX_DEBUG_POL_KEY1_IN_SIZE 0x1 +#define GC_RBOX_DEBUG_POL_KEY1_IN_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_KEY1_IN_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_KEY1_OUT_LSB 0x5 +#define GC_RBOX_DEBUG_POL_KEY1_OUT_MASK 0x20 +#define GC_RBOX_DEBUG_POL_KEY1_OUT_SIZE 0x1 +#define GC_RBOX_DEBUG_POL_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_KEY1_OUT_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_AC_PRESENT_LSB 0x6 +#define GC_RBOX_DEBUG_POL_AC_PRESENT_MASK 0x40 +#define GC_RBOX_DEBUG_POL_AC_PRESENT_SIZE 0x1 +#define GC_RBOX_DEBUG_POL_AC_PRESENT_DEFAULT 0x1 +#define GC_RBOX_DEBUG_POL_AC_PRESENT_OFFSET 0x3c +#define GC_RBOX_DEBUG_TERM_PWRB_IN_LSB 0x0 +#define GC_RBOX_DEBUG_TERM_PWRB_IN_MASK 0x3 +#define GC_RBOX_DEBUG_TERM_PWRB_IN_SIZE 0x2 +#define GC_RBOX_DEBUG_TERM_PWRB_IN_DEFAULT 0x0 +#define GC_RBOX_DEBUG_TERM_PWRB_IN_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_PWRB_OUT_LSB 0x2 +#define GC_RBOX_DEBUG_TERM_PWRB_OUT_MASK 0xc +#define GC_RBOX_DEBUG_TERM_PWRB_OUT_SIZE 0x2 +#define GC_RBOX_DEBUG_TERM_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_TERM_PWRB_OUT_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_KEY0_IN_LSB 0x4 +#define GC_RBOX_DEBUG_TERM_KEY0_IN_MASK 0x30 +#define GC_RBOX_DEBUG_TERM_KEY0_IN_SIZE 0x2 +#define GC_RBOX_DEBUG_TERM_KEY0_IN_DEFAULT 0x0 +#define GC_RBOX_DEBUG_TERM_KEY0_IN_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_KEY0_OUT_LSB 0x6 +#define GC_RBOX_DEBUG_TERM_KEY0_OUT_MASK 0xc0 +#define GC_RBOX_DEBUG_TERM_KEY0_OUT_SIZE 0x2 +#define GC_RBOX_DEBUG_TERM_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_TERM_KEY0_OUT_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_KEY1_IN_LSB 0x8 +#define GC_RBOX_DEBUG_TERM_KEY1_IN_MASK 0x300 +#define GC_RBOX_DEBUG_TERM_KEY1_IN_SIZE 0x2 +#define GC_RBOX_DEBUG_TERM_KEY1_IN_DEFAULT 0x0 +#define GC_RBOX_DEBUG_TERM_KEY1_IN_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_KEY1_OUT_LSB 0xa +#define GC_RBOX_DEBUG_TERM_KEY1_OUT_MASK 0xc00 +#define GC_RBOX_DEBUG_TERM_KEY1_OUT_SIZE 0x2 +#define GC_RBOX_DEBUG_TERM_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_TERM_KEY1_OUT_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_AC_PRESENT_LSB 0xc +#define GC_RBOX_DEBUG_TERM_AC_PRESENT_MASK 0x3000 +#define GC_RBOX_DEBUG_TERM_AC_PRESENT_SIZE 0x2 +#define GC_RBOX_DEBUG_TERM_AC_PRESENT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_TERM_AC_PRESENT_OFFSET 0x40 +#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_LSB 0x0 +#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_MASK 0x3 +#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_SIZE 0x2 +#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_OFFSET 0x44 +#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_LSB 0x2 +#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_MASK 0xc +#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_SIZE 0x2 +#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_OFFSET 0x44 +#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_LSB 0x4 +#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_MASK 0x30 +#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_SIZE 0x2 +#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_OFFSET 0x44 +#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_LSB 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_MASK 0xff +#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_SIZE 0x8 +#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_DEFAULT 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_OFFSET 0x68 +#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_LSB 0x8 +#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_MASK 0xff00 +#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_SIZE 0x8 +#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_DEFAULT 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_OFFSET 0x68 +#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_LSB 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_MASK 0xff +#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_SIZE 0x8 +#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_DEFAULT 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_OFFSET 0x6c +#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_LSB 0x8 +#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_MASK 0xff00 +#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_SIZE 0x8 +#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_DEFAULT 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_OFFSET 0x6c +#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_LSB 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_MASK 0xff +#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_SIZE 0x8 +#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_DEFAULT 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_OFFSET 0x70 +#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_LSB 0x8 +#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_MASK 0xff00 +#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_SIZE 0x8 +#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_DEFAULT 0x0 +#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_OFFSET 0x70 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_LSB 0x0 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_MASK 0x1 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_SIZE 0x1 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_DEFAULT 0x0 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_OFFSET 0x74 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_LSB 0x1 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_MASK 0x2 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_SIZE 0x1 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_DEFAULT 0x0 +#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_OFFSET 0x74 +#define GC_RBOX_CONFIG_POL_PWRB_IN_LSB 0x0 +#define GC_RBOX_CONFIG_POL_PWRB_IN_MASK 0x1 +#define GC_RBOX_CONFIG_POL_PWRB_IN_SIZE 0x1 +#define GC_RBOX_CONFIG_POL_PWRB_IN_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_PWRB_IN_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_PWRB_OUT_LSB 0x1 +#define GC_RBOX_CONFIG_POL_PWRB_OUT_MASK 0x2 +#define GC_RBOX_CONFIG_POL_PWRB_OUT_SIZE 0x1 +#define GC_RBOX_CONFIG_POL_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_PWRB_OUT_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_KEY0_IN_LSB 0x2 +#define GC_RBOX_CONFIG_POL_KEY0_IN_MASK 0x4 +#define GC_RBOX_CONFIG_POL_KEY0_IN_SIZE 0x1 +#define GC_RBOX_CONFIG_POL_KEY0_IN_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_KEY0_IN_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_KEY0_OUT_LSB 0x3 +#define GC_RBOX_CONFIG_POL_KEY0_OUT_MASK 0x8 +#define GC_RBOX_CONFIG_POL_KEY0_OUT_SIZE 0x1 +#define GC_RBOX_CONFIG_POL_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_KEY0_OUT_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_KEY1_IN_LSB 0x4 +#define GC_RBOX_CONFIG_POL_KEY1_IN_MASK 0x10 +#define GC_RBOX_CONFIG_POL_KEY1_IN_SIZE 0x1 +#define GC_RBOX_CONFIG_POL_KEY1_IN_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_KEY1_IN_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_KEY1_OUT_LSB 0x5 +#define GC_RBOX_CONFIG_POL_KEY1_OUT_MASK 0x20 +#define GC_RBOX_CONFIG_POL_KEY1_OUT_SIZE 0x1 +#define GC_RBOX_CONFIG_POL_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_KEY1_OUT_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_AC_PRESENT_LSB 0x6 +#define GC_RBOX_CONFIG_POL_AC_PRESENT_MASK 0x40 +#define GC_RBOX_CONFIG_POL_AC_PRESENT_SIZE 0x1 +#define GC_RBOX_CONFIG_POL_AC_PRESENT_DEFAULT 0x1 +#define GC_RBOX_CONFIG_POL_AC_PRESENT_OFFSET 0x78 +#define GC_RBOX_CONFIG_TERM_PWRB_IN_LSB 0x0 +#define GC_RBOX_CONFIG_TERM_PWRB_IN_MASK 0x3 +#define GC_RBOX_CONFIG_TERM_PWRB_IN_SIZE 0x2 +#define GC_RBOX_CONFIG_TERM_PWRB_IN_DEFAULT 0x0 +#define GC_RBOX_CONFIG_TERM_PWRB_IN_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_PWRB_OUT_LSB 0x2 +#define GC_RBOX_CONFIG_TERM_PWRB_OUT_MASK 0xc +#define GC_RBOX_CONFIG_TERM_PWRB_OUT_SIZE 0x2 +#define GC_RBOX_CONFIG_TERM_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_TERM_PWRB_OUT_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_KEY0_IN_LSB 0x4 +#define GC_RBOX_CONFIG_TERM_KEY0_IN_MASK 0x30 +#define GC_RBOX_CONFIG_TERM_KEY0_IN_SIZE 0x2 +#define GC_RBOX_CONFIG_TERM_KEY0_IN_DEFAULT 0x0 +#define GC_RBOX_CONFIG_TERM_KEY0_IN_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_KEY0_OUT_LSB 0x6 +#define GC_RBOX_CONFIG_TERM_KEY0_OUT_MASK 0xc0 +#define GC_RBOX_CONFIG_TERM_KEY0_OUT_SIZE 0x2 +#define GC_RBOX_CONFIG_TERM_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_TERM_KEY0_OUT_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_KEY1_IN_LSB 0x8 +#define GC_RBOX_CONFIG_TERM_KEY1_IN_MASK 0x300 +#define GC_RBOX_CONFIG_TERM_KEY1_IN_SIZE 0x2 +#define GC_RBOX_CONFIG_TERM_KEY1_IN_DEFAULT 0x0 +#define GC_RBOX_CONFIG_TERM_KEY1_IN_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_KEY1_OUT_LSB 0xa +#define GC_RBOX_CONFIG_TERM_KEY1_OUT_MASK 0xc00 +#define GC_RBOX_CONFIG_TERM_KEY1_OUT_SIZE 0x2 +#define GC_RBOX_CONFIG_TERM_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_TERM_KEY1_OUT_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_AC_PRESENT_LSB 0xc +#define GC_RBOX_CONFIG_TERM_AC_PRESENT_MASK 0x3000 +#define GC_RBOX_CONFIG_TERM_AC_PRESENT_SIZE 0x2 +#define GC_RBOX_CONFIG_TERM_AC_PRESENT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_TERM_AC_PRESENT_OFFSET 0x7c +#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_LSB 0x0 +#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_MASK 0x3 +#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_SIZE 0x2 +#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_OFFSET 0x80 +#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_LSB 0x2 +#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_MASK 0xc +#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_SIZE 0x2 +#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_OFFSET 0x80 +#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_LSB 0x4 +#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_MASK 0x30 +#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_SIZE 0x2 +#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_OFFSET 0x80 #define GC_RBOX_VERSION_CHANGE_LSB 0x0 #define GC_RBOX_VERSION_CHANGE_MASK 0xffffff #define GC_RBOX_VERSION_CHANGE_SIZE 0x18 -#define GC_RBOX_VERSION_CHANGE_DEFAULT 0xc16f -#define GC_RBOX_VERSION_CHANGE_OFFSET 0x18 +#define GC_RBOX_VERSION_CHANGE_DEFAULT 0x10772 +#define GC_RBOX_VERSION_CHANGE_OFFSET 0x90 #define GC_RBOX_VERSION_REVISION_LSB 0x18 #define GC_RBOX_VERSION_REVISION_MASK 0xff000000 #define GC_RBOX_VERSION_REVISION_SIZE 0x8 -#define GC_RBOX_VERSION_REVISION_DEFAULT 0x6 -#define GC_RBOX_VERSION_REVISION_OFFSET 0x18 -#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_LSB 0x0 -#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_MASK 0xf -#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_SIZE 0x4 -#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_DEFAULT 0x1 -#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_OFFSET 0x0 -#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_LSB 0x4 -#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_MASK 0xff0 -#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_SIZE 0x8 -#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_DEFAULT 0xf0 -#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_OFFSET 0x0 -#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_LSB 0xc -#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_MASK 0x1000 -#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_SIZE 0x1 -#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_DEFAULT 0x0 -#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_OFFSET 0x0 -#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_LSB 0xd -#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_MASK 0x6000 -#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_SIZE 0x2 -#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_DEFAULT 0x1 -#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_OFFSET 0x0 -#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_LSB 0xf -#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_MASK 0x78000 -#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_SIZE 0x4 -#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_DEFAULT 0x4 -#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_OFFSET 0x0 -#define GC_RTC_SETHOLD_EN_LSB 0x0 -#define GC_RTC_SETHOLD_EN_MASK 0x1 -#define GC_RTC_SETHOLD_EN_SIZE 0x1 -#define GC_RTC_SETHOLD_EN_DEFAULT 0x0 -#define GC_RTC_SETHOLD_EN_OFFSET 0x8 -#define GC_RTC_CLRHOLD_EN_LSB 0x0 -#define GC_RTC_CLRHOLD_EN_MASK 0x1 -#define GC_RTC_CLRHOLD_EN_SIZE 0x1 -#define GC_RTC_CLRHOLD_EN_DEFAULT 0x0 -#define GC_RTC_CLRHOLD_EN_OFFSET 0xc +#define GC_RBOX_VERSION_REVISION_DEFAULT 0x23 +#define GC_RBOX_VERSION_REVISION_OFFSET 0x90 +#define GC_RDD_VERSION_CHANGE_LSB 0x0 +#define GC_RDD_VERSION_CHANGE_MASK 0xffffff +#define GC_RDD_VERSION_CHANGE_SIZE 0x18 +#define GC_RDD_VERSION_CHANGE_DEFAULT 0xf210 +#define GC_RDD_VERSION_CHANGE_OFFSET 0x0 +#define GC_RDD_VERSION_REVISION_LSB 0x18 +#define GC_RDD_VERSION_REVISION_MASK 0xff000000 +#define GC_RDD_VERSION_REVISION_SIZE 0x8 +#define GC_RDD_VERSION_REVISION_DEFAULT 0x5 +#define GC_RDD_VERSION_REVISION_OFFSET 0x0 +#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_LSB 0x0 +#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_MASK 0x1 +#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_SIZE 0x1 +#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_DEFAULT 0x0 +#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_OFFSET 0x4 +#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_LSB 0x0 +#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_MASK 0x1 +#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_SIZE 0x1 +#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_DEFAULT 0x0 +#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_OFFSET 0x8 +#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_LSB 0x0 +#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_MASK 0x1 +#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_SIZE 0x1 +#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_DEFAULT 0x0 +#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_OFFSET 0xc +#define GC_RDD_CUR_STABLE_STATE_OPEN_LSB 0x0 +#define GC_RDD_CUR_STABLE_STATE_OPEN_MASK 0x1 +#define GC_RDD_CUR_STABLE_STATE_OPEN_SIZE 0x1 +#define GC_RDD_CUR_STABLE_STATE_OPEN_DEFAULT 0x0 +#define GC_RDD_CUR_STABLE_STATE_OPEN_OFFSET 0x1c +#define GC_RDD_CUR_STABLE_STATE_DEBUG_LSB 0x1 +#define GC_RDD_CUR_STABLE_STATE_DEBUG_MASK 0x2 +#define GC_RDD_CUR_STABLE_STATE_DEBUG_SIZE 0x1 +#define GC_RDD_CUR_STABLE_STATE_DEBUG_DEFAULT 0x0 +#define GC_RDD_CUR_STABLE_STATE_DEBUG_OFFSET 0x1c +#define GC_RDD_CUR_STABLE_STATE_INVALID_LSB 0x2 +#define GC_RDD_CUR_STABLE_STATE_INVALID_MASK 0x4 +#define GC_RDD_CUR_STABLE_STATE_INVALID_SIZE 0x1 +#define GC_RDD_CUR_STABLE_STATE_INVALID_DEFAULT 0x1 +#define GC_RDD_CUR_STABLE_STATE_INVALID_OFFSET 0x1c +#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_LSB 0x3 +#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_MASK 0x8 +#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_SIZE 0x1 +#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_DEFAULT 0x0 +#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_OFFSET 0x1c +#define GC_RTC_CTRL_X_RTC_RC_CTRL_LSB 0x0 +#define GC_RTC_CTRL_X_RTC_RC_CTRL_MASK 0xff +#define GC_RTC_CTRL_X_RTC_RC_CTRL_SIZE 0x8 +#define GC_RTC_CTRL_X_RTC_RC_CTRL_DEFAULT 0x0 +#define GC_RTC_CTRL_X_RTC_RC_CTRL_OFFSET 0x0 +#define GC_RTC_PULSE_STRETCH_CNT_LSB 0x0 +#define GC_RTC_PULSE_STRETCH_CNT_MASK 0xffff +#define GC_RTC_PULSE_STRETCH_CNT_SIZE 0x10 +#define GC_RTC_PULSE_STRETCH_CNT_DEFAULT 0x0 +#define GC_RTC_PULSE_STRETCH_CNT_OFFSET 0x8 +#define GC_RTC_PULSE_STRETCH_EN_LSB 0x10 +#define GC_RTC_PULSE_STRETCH_EN_MASK 0x10000 +#define GC_RTC_PULSE_STRETCH_EN_SIZE 0x1 +#define GC_RTC_PULSE_STRETCH_EN_DEFAULT 0x0 +#define GC_RTC_PULSE_STRETCH_EN_OFFSET 0x8 +#define GC_RTC_SW_TRIM_COUNTER_VALUE_LSB 0x0 +#define GC_RTC_SW_TRIM_COUNTER_VALUE_MASK 0xffffff +#define GC_RTC_SW_TRIM_COUNTER_VALUE_SIZE 0x18 +#define GC_RTC_SW_TRIM_COUNTER_VALUE_DEFAULT 0x0 +#define GC_RTC_SW_TRIM_COUNTER_VALUE_OFFSET 0x10 +#define GC_RTC_SW_TRIM_COUNTER_DONE_LSB 0x18 +#define GC_RTC_SW_TRIM_COUNTER_DONE_MASK 0x1000000 +#define GC_RTC_SW_TRIM_COUNTER_DONE_SIZE 0x1 +#define GC_RTC_SW_TRIM_COUNTER_DONE_DEFAULT 0x0 +#define GC_RTC_SW_TRIM_COUNTER_DONE_OFFSET 0x10 #define GC_SHA_CFG_EN_EN_BIG_ENDIAN_LSB 0x0 #define GC_SHA_CFG_EN_EN_BIG_ENDIAN_MASK 0x1 #define GC_SHA_CFG_EN_EN_BIG_ENDIAN_SIZE 0x1 @@ -9442,21 +14509,36 @@ #define GC_SHA_CFG_EN_EN_SHA1_SIZE 0x1 #define GC_SHA_CFG_EN_EN_SHA1_DEFAULT 0x0 #define GC_SHA_CFG_EN_EN_SHA1_OFFSET 0x8 -#define GC_SHA_CFG_EN_EN_STEP_LSB 0x2 -#define GC_SHA_CFG_EN_EN_STEP_MASK 0x4 -#define GC_SHA_CFG_EN_EN_STEP_SIZE 0x1 -#define GC_SHA_CFG_EN_EN_STEP_DEFAULT 0x0 -#define GC_SHA_CFG_EN_EN_STEP_OFFSET 0x8 +#define GC_SHA_CFG_EN_RESERVED0_LSB 0x2 +#define GC_SHA_CFG_EN_RESERVED0_MASK 0x4 +#define GC_SHA_CFG_EN_RESERVED0_SIZE 0x1 +#define GC_SHA_CFG_EN_RESERVED0_DEFAULT 0x0 +#define GC_SHA_CFG_EN_RESERVED0_OFFSET 0x8 #define GC_SHA_CFG_EN_EN_BUS_ERROR_LSB 0x3 #define GC_SHA_CFG_EN_EN_BUS_ERROR_MASK 0x8 #define GC_SHA_CFG_EN_EN_BUS_ERROR_SIZE 0x1 #define GC_SHA_CFG_EN_EN_BUS_ERROR_DEFAULT 0x0 #define GC_SHA_CFG_EN_EN_BUS_ERROR_OFFSET 0x8 -#define GC_SHA_CFG_EN_RESERVED0_LSB 0x4 -#define GC_SHA_CFG_EN_RESERVED0_MASK 0xfff0 -#define GC_SHA_CFG_EN_RESERVED0_SIZE 0xc -#define GC_SHA_CFG_EN_RESERVED0_DEFAULT 0x0 -#define GC_SHA_CFG_EN_RESERVED0_OFFSET 0x8 +#define GC_SHA_CFG_EN_EN_LIVESTREAM_LSB 0x4 +#define GC_SHA_CFG_EN_EN_LIVESTREAM_MASK 0x10 +#define GC_SHA_CFG_EN_EN_LIVESTREAM_SIZE 0x1 +#define GC_SHA_CFG_EN_EN_LIVESTREAM_DEFAULT 0x0 +#define GC_SHA_CFG_EN_EN_LIVESTREAM_OFFSET 0x8 +#define GC_SHA_CFG_EN_EN_HMAC_LSB 0x5 +#define GC_SHA_CFG_EN_EN_HMAC_MASK 0x20 +#define GC_SHA_CFG_EN_EN_HMAC_SIZE 0x1 +#define GC_SHA_CFG_EN_EN_HMAC_DEFAULT 0x0 +#define GC_SHA_CFG_EN_EN_HMAC_OFFSET 0x8 +#define GC_SHA_CFG_EN_EN_HKEY_LSB 0x6 +#define GC_SHA_CFG_EN_EN_HKEY_MASK 0x40 +#define GC_SHA_CFG_EN_EN_HKEY_SIZE 0x1 +#define GC_SHA_CFG_EN_EN_HKEY_DEFAULT 0x0 +#define GC_SHA_CFG_EN_EN_HKEY_OFFSET 0x8 +#define GC_SHA_CFG_EN_RESERVED1_LSB 0x7 +#define GC_SHA_CFG_EN_RESERVED1_MASK 0xff80 +#define GC_SHA_CFG_EN_RESERVED1_SIZE 0x9 +#define GC_SHA_CFG_EN_RESERVED1_DEFAULT 0x0 +#define GC_SHA_CFG_EN_RESERVED1_OFFSET 0x8 #define GC_SHA_CFG_EN_INT_EN_SHA_DONE_LSB 0x10 #define GC_SHA_CFG_EN_INT_EN_SHA_DONE_MASK 0x10000 #define GC_SHA_CFG_EN_INT_EN_SHA_DONE_SIZE 0x1 @@ -9467,11 +14549,6 @@ #define GC_SHA_CFG_EN_INT_MASK_SHA_DONE_SIZE 0x1 #define GC_SHA_CFG_EN_INT_MASK_SHA_DONE_DEFAULT 0x0 #define GC_SHA_CFG_EN_INT_MASK_SHA_DONE_OFFSET 0x8 -#define GC_SHA_CFG_EN_RESERVED1_LSB 0x12 -#define GC_SHA_CFG_EN_RESERVED1_MASK 0xfffc0000 -#define GC_SHA_CFG_EN_RESERVED1_SIZE 0xe -#define GC_SHA_CFG_EN_RESERVED1_DEFAULT 0x0 -#define GC_SHA_CFG_EN_RESERVED1_OFFSET 0x8 #define GC_SHA_TRIG_TRIG_GO_LSB 0x0 #define GC_SHA_TRIG_TRIG_GO_MASK 0x1 #define GC_SHA_TRIG_TRIG_GO_SIZE 0x1 @@ -9487,6 +14564,26 @@ #define GC_SHA_TRIG_TRIG_STEP_SIZE 0x1 #define GC_SHA_TRIG_TRIG_STEP_DEFAULT 0x0 #define GC_SHA_TRIG_TRIG_STEP_OFFSET 0xc +#define GC_SHA_TRIG_TRIG_STOP_LSB 0x3 +#define GC_SHA_TRIG_TRIG_STOP_MASK 0x8 +#define GC_SHA_TRIG_TRIG_STOP_SIZE 0x1 +#define GC_SHA_TRIG_TRIG_STOP_DEFAULT 0x0 +#define GC_SHA_TRIG_TRIG_STOP_OFFSET 0xc +#define GC_SHA_STS_FIFO_EMPTY_LSB 0x0 +#define GC_SHA_STS_FIFO_EMPTY_MASK 0x1 +#define GC_SHA_STS_FIFO_EMPTY_SIZE 0x1 +#define GC_SHA_STS_FIFO_EMPTY_DEFAULT 0x1 +#define GC_SHA_STS_FIFO_EMPTY_OFFSET 0x130 +#define GC_SHA_STS_FIFO_FULL_LSB 0x1 +#define GC_SHA_STS_FIFO_FULL_MASK 0x2 +#define GC_SHA_STS_FIFO_FULL_SIZE 0x1 +#define GC_SHA_STS_FIFO_FULL_DEFAULT 0x0 +#define GC_SHA_STS_FIFO_FULL_OFFSET 0x130 +#define GC_SHA_STS_ERROR_LSB 0x2 +#define GC_SHA_STS_ERROR_MASK 0x4 +#define GC_SHA_STS_ERROR_SIZE 0x1 +#define GC_SHA_STS_ERROR_DEFAULT 0x0 +#define GC_SHA_STS_ERROR_OFFSET 0x130 #define GC_SPI_CTRL_CPOL_LSB 0x0 #define GC_SPI_CTRL_CPOL_MASK 0x1 #define GC_SPI_CTRL_CPOL_SIZE 0x1 @@ -9537,6 +14634,11 @@ #define GC_SPI_CTRL_RXBYTOR_SIZE 0x1 #define GC_SPI_CTRL_RXBYTOR_DEFAULT 0x0 #define GC_SPI_CTRL_RXBYTOR_OFFSET 0x0 +#define GC_SPI_CTRL_ENPASSTHRU_LSB 0x1b +#define GC_SPI_CTRL_ENPASSTHRU_MASK 0x8000000 +#define GC_SPI_CTRL_ENPASSTHRU_SIZE 0x1 +#define GC_SPI_CTRL_ENPASSTHRU_DEFAULT 0x0 +#define GC_SPI_CTRL_ENPASSTHRU_OFFSET 0x0 #define GC_SPI_XACT_START_LSB 0x0 #define GC_SPI_XACT_START_MASK 0x1 #define GC_SPI_XACT_START_SIZE 0x1 @@ -9662,11 +14764,6 @@ #define GC_SPS_CTRL_RXBITOR_SIZE 0x1 #define GC_SPS_CTRL_RXBITOR_DEFAULT 0x0 #define GC_SPS_CTRL_RXBITOR_OFFSET 0x0 -#define GC_SPS_CTRL_ROM_ADDR_SIZE_LSB 0x7 -#define GC_SPS_CTRL_ROM_ADDR_SIZE_MASK 0x180 -#define GC_SPS_CTRL_ROM_ADDR_SIZE_SIZE 0x2 -#define GC_SPS_CTRL_ROM_ADDR_SIZE_DEFAULT 0x3 -#define GC_SPS_CTRL_ROM_ADDR_SIZE_OFFSET 0x0 #define GC_SPS_STATUS01_STATUS0L_LSB 0x0 #define GC_SPS_STATUS01_STATUS0L_MASK 0xff #define GC_SPS_STATUS01_STATUS0L_SIZE 0x8 @@ -9782,528 +14879,593 @@ #define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_SIZE 0x1 #define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_DEFAULT 0x0 #define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_OFFSET 0x28 -#define GC_SPS_ROM_REGION0_CTRL_READ_EN_LSB 0x0 -#define GC_SPS_ROM_REGION0_CTRL_READ_EN_MASK 0x1 -#define GC_SPS_ROM_REGION0_CTRL_READ_EN_SIZE 0x1 -#define GC_SPS_ROM_REGION0_CTRL_READ_EN_DEFAULT 0x0 -#define GC_SPS_ROM_REGION0_CTRL_READ_EN_OFFSET 0x4c -#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_LSB 0x1 -#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_MASK 0x2 -#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_SIZE 0x1 -#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_DEFAULT 0x0 -#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_OFFSET 0x4c -#define GC_SPS_ROM_REGION0_CTRL_WRAP_LSB 0x2 -#define GC_SPS_ROM_REGION0_CTRL_WRAP_MASK 0x4 -#define GC_SPS_ROM_REGION0_CTRL_WRAP_SIZE 0x1 -#define GC_SPS_ROM_REGION0_CTRL_WRAP_DEFAULT 0x0 -#define GC_SPS_ROM_REGION0_CTRL_WRAP_OFFSET 0x4c -#define GC_SPS_ROM_REGION1_CTRL_READ_EN_LSB 0x0 -#define GC_SPS_ROM_REGION1_CTRL_READ_EN_MASK 0x1 -#define GC_SPS_ROM_REGION1_CTRL_READ_EN_SIZE 0x1 -#define GC_SPS_ROM_REGION1_CTRL_READ_EN_DEFAULT 0x0 -#define GC_SPS_ROM_REGION1_CTRL_READ_EN_OFFSET 0x60 -#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_LSB 0x1 -#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_MASK 0x2 -#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_SIZE 0x1 -#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_DEFAULT 0x0 -#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_OFFSET 0x60 -#define GC_SPS_ROM_REGION1_CTRL_WRAP_LSB 0x2 -#define GC_SPS_ROM_REGION1_CTRL_WRAP_MASK 0x4 -#define GC_SPS_ROM_REGION1_CTRL_WRAP_SIZE 0x1 -#define GC_SPS_ROM_REGION1_CTRL_WRAP_DEFAULT 0x0 -#define GC_SPS_ROM_REGION1_CTRL_WRAP_OFFSET 0x60 -#define GC_SPS_ROM_REGION2_CTRL_READ_EN_LSB 0x0 -#define GC_SPS_ROM_REGION2_CTRL_READ_EN_MASK 0x1 -#define GC_SPS_ROM_REGION2_CTRL_READ_EN_SIZE 0x1 -#define GC_SPS_ROM_REGION2_CTRL_READ_EN_DEFAULT 0x0 -#define GC_SPS_ROM_REGION2_CTRL_READ_EN_OFFSET 0x74 -#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_LSB 0x1 -#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_MASK 0x2 -#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_SIZE 0x1 -#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_DEFAULT 0x0 -#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_OFFSET 0x74 -#define GC_SPS_ROM_REGION2_CTRL_WRAP_LSB 0x2 -#define GC_SPS_ROM_REGION2_CTRL_WRAP_MASK 0x4 -#define GC_SPS_ROM_REGION2_CTRL_WRAP_SIZE 0x1 -#define GC_SPS_ROM_REGION2_CTRL_WRAP_DEFAULT 0x0 -#define GC_SPS_ROM_REGION2_CTRL_WRAP_OFFSET 0x74 -#define GC_SPS_ROM_REGION3_CTRL_READ_EN_LSB 0x0 -#define GC_SPS_ROM_REGION3_CTRL_READ_EN_MASK 0x1 -#define GC_SPS_ROM_REGION3_CTRL_READ_EN_SIZE 0x1 -#define GC_SPS_ROM_REGION3_CTRL_READ_EN_DEFAULT 0x0 -#define GC_SPS_ROM_REGION3_CTRL_READ_EN_OFFSET 0x88 -#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_LSB 0x1 -#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_MASK 0x2 -#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_SIZE 0x1 -#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_DEFAULT 0x0 -#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_OFFSET 0x88 -#define GC_SPS_ROM_REGION3_CTRL_WRAP_LSB 0x2 -#define GC_SPS_ROM_REGION3_CTRL_WRAP_MASK 0x4 -#define GC_SPS_ROM_REGION3_CTRL_WRAP_SIZE 0x1 -#define GC_SPS_ROM_REGION3_CTRL_WRAP_DEFAULT 0x0 -#define GC_SPS_ROM_REGION3_CTRL_WRAP_OFFSET 0x88 #define GC_SPS_OVRD_MISOEN_LSB 0x0 #define GC_SPS_OVRD_MISOEN_MASK 0x1 #define GC_SPS_OVRD_MISOEN_SIZE 0x1 #define GC_SPS_OVRD_MISOEN_DEFAULT 0x0 -#define GC_SPS_OVRD_MISOEN_OFFSET 0xb4 +#define GC_SPS_OVRD_MISOEN_OFFSET 0x4c #define GC_SPS_OVRD_MISOVAL_LSB 0x1 #define GC_SPS_OVRD_MISOVAL_MASK 0x2 #define GC_SPS_OVRD_MISOVAL_SIZE 0x1 #define GC_SPS_OVRD_MISOVAL_DEFAULT 0x0 -#define GC_SPS_OVRD_MISOVAL_OFFSET 0xb4 +#define GC_SPS_OVRD_MISOVAL_OFFSET 0x4c #define GC_SPS_VAL_MISO_LSB 0x0 #define GC_SPS_VAL_MISO_MASK 0x1 #define GC_SPS_VAL_MISO_SIZE 0x1 #define GC_SPS_VAL_MISO_DEFAULT 0x0 -#define GC_SPS_VAL_MISO_OFFSET 0xb8 +#define GC_SPS_VAL_MISO_OFFSET 0x50 #define GC_SPS_VAL_MOSI_LSB 0x1 #define GC_SPS_VAL_MOSI_MASK 0x2 #define GC_SPS_VAL_MOSI_SIZE 0x1 #define GC_SPS_VAL_MOSI_DEFAULT 0x0 -#define GC_SPS_VAL_MOSI_OFFSET 0xb8 +#define GC_SPS_VAL_MOSI_OFFSET 0x50 #define GC_SPS_VAL_CSB_LSB 0x2 #define GC_SPS_VAL_CSB_MASK 0x4 #define GC_SPS_VAL_CSB_SIZE 0x1 #define GC_SPS_VAL_CSB_DEFAULT 0x0 -#define GC_SPS_VAL_CSB_OFFSET 0xb8 +#define GC_SPS_VAL_CSB_OFFSET 0x50 #define GC_SPS_VAL_SCK_LSB 0x3 #define GC_SPS_VAL_SCK_MASK 0x8 #define GC_SPS_VAL_SCK_SIZE 0x1 #define GC_SPS_VAL_SCK_DEFAULT 0x0 -#define GC_SPS_VAL_SCK_OFFSET 0xb8 -#define GC_SPS_ICTRL_CTLWR0_LSB 0x0 -#define GC_SPS_ICTRL_CTLWR0_MASK 0x1 -#define GC_SPS_ICTRL_CTLWR0_SIZE 0x1 -#define GC_SPS_ICTRL_CTLWR0_DEFAULT 0x0 -#define GC_SPS_ICTRL_CTLWR0_OFFSET 0xbc -#define GC_SPS_ICTRL_CTLWR1_LSB 0x1 -#define GC_SPS_ICTRL_CTLWR1_MASK 0x2 -#define GC_SPS_ICTRL_CTLWR1_SIZE 0x1 -#define GC_SPS_ICTRL_CTLWR1_DEFAULT 0x0 -#define GC_SPS_ICTRL_CTLWR1_OFFSET 0xbc -#define GC_SPS_ICTRL_CTLWR2_LSB 0x2 -#define GC_SPS_ICTRL_CTLWR2_MASK 0x4 -#define GC_SPS_ICTRL_CTLWR2_SIZE 0x1 -#define GC_SPS_ICTRL_CTLWR2_DEFAULT 0x0 -#define GC_SPS_ICTRL_CTLWR2_OFFSET 0xbc -#define GC_SPS_ICTRL_CTLWR3_LSB 0x3 -#define GC_SPS_ICTRL_CTLWR3_MASK 0x8 -#define GC_SPS_ICTRL_CTLWR3_SIZE 0x1 -#define GC_SPS_ICTRL_CTLWR3_DEFAULT 0x0 -#define GC_SPS_ICTRL_CTLWR3_OFFSET 0xbc -#define GC_SPS_ICTRL_CTLWR4_LSB 0x4 -#define GC_SPS_ICTRL_CTLWR4_MASK 0x10 -#define GC_SPS_ICTRL_CTLWR4_SIZE 0x1 -#define GC_SPS_ICTRL_CTLWR4_DEFAULT 0x0 -#define GC_SPS_ICTRL_CTLWR4_OFFSET 0xbc -#define GC_SPS_ICTRL_CTLWR5_LSB 0x5 -#define GC_SPS_ICTRL_CTLWR5_MASK 0x20 -#define GC_SPS_ICTRL_CTLWR5_SIZE 0x1 -#define GC_SPS_ICTRL_CTLWR5_DEFAULT 0x0 -#define GC_SPS_ICTRL_CTLWR5_OFFSET 0xbc -#define GC_SPS_ICTRL_CTLWR6_LSB 0x6 -#define GC_SPS_ICTRL_CTLWR6_MASK 0x40 -#define GC_SPS_ICTRL_CTLWR6_SIZE 0x1 -#define GC_SPS_ICTRL_CTLWR6_DEFAULT 0x0 -#define GC_SPS_ICTRL_CTLWR6_OFFSET 0xbc -#define GC_SPS_ICTRL_CTLWR7_LSB 0x7 -#define GC_SPS_ICTRL_CTLWR7_MASK 0x80 -#define GC_SPS_ICTRL_CTLWR7_SIZE 0x1 -#define GC_SPS_ICTRL_CTLWR7_DEFAULT 0x0 -#define GC_SPS_ICTRL_CTLWR7_OFFSET 0xbc -#define GC_SPS_ICTRL_CS_ASSERT_LSB 0x8 -#define GC_SPS_ICTRL_CS_ASSERT_MASK 0x100 -#define GC_SPS_ICTRL_CS_ASSERT_SIZE 0x1 -#define GC_SPS_ICTRL_CS_ASSERT_DEFAULT 0x0 -#define GC_SPS_ICTRL_CS_ASSERT_OFFSET 0xbc -#define GC_SPS_ICTRL_CS_DEASSERT_LSB 0x9 -#define GC_SPS_ICTRL_CS_DEASSERT_MASK 0x200 -#define GC_SPS_ICTRL_CS_DEASSERT_SIZE 0x1 -#define GC_SPS_ICTRL_CS_DEASSERT_DEFAULT 0x0 -#define GC_SPS_ICTRL_CS_DEASSERT_OFFSET 0xbc -#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_LSB 0xa -#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_MASK 0x400 -#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_SIZE 0x1 -#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_DEFAULT 0x0 -#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_OFFSET 0xbc -#define GC_SPS_ICTRL_TXFIFO_EMPTY_LSB 0xb -#define GC_SPS_ICTRL_TXFIFO_EMPTY_MASK 0x800 -#define GC_SPS_ICTRL_TXFIFO_EMPTY_SIZE 0x1 -#define GC_SPS_ICTRL_TXFIFO_EMPTY_DEFAULT 0x0 -#define GC_SPS_ICTRL_TXFIFO_EMPTY_OFFSET 0xbc -#define GC_SPS_ICTRL_TXFIFO_FULL_LSB 0xc -#define GC_SPS_ICTRL_TXFIFO_FULL_MASK 0x1000 -#define GC_SPS_ICTRL_TXFIFO_FULL_SIZE 0x1 -#define GC_SPS_ICTRL_TXFIFO_FULL_DEFAULT 0x0 -#define GC_SPS_ICTRL_TXFIFO_FULL_OFFSET 0xbc -#define GC_SPS_ICTRL_TXFIFO_LVL_LSB 0xd -#define GC_SPS_ICTRL_TXFIFO_LVL_MASK 0x2000 -#define GC_SPS_ICTRL_TXFIFO_LVL_SIZE 0x1 -#define GC_SPS_ICTRL_TXFIFO_LVL_DEFAULT 0x0 -#define GC_SPS_ICTRL_TXFIFO_LVL_OFFSET 0xbc -#define GC_SPS_ICTRL_RXFIFO_LVL_LSB 0xe -#define GC_SPS_ICTRL_RXFIFO_LVL_MASK 0x4000 -#define GC_SPS_ICTRL_RXFIFO_LVL_SIZE 0x1 -#define GC_SPS_ICTRL_RXFIFO_LVL_DEFAULT 0x0 -#define GC_SPS_ICTRL_RXFIFO_LVL_OFFSET 0xbc -#define GC_SPS_ICTRL_ROM_CMD_START_LSB 0xf -#define GC_SPS_ICTRL_ROM_CMD_START_MASK 0x8000 -#define GC_SPS_ICTRL_ROM_CMD_START_SIZE 0x1 -#define GC_SPS_ICTRL_ROM_CMD_START_DEFAULT 0x0 -#define GC_SPS_ICTRL_ROM_CMD_START_OFFSET 0xbc -#define GC_SPS_ICTRL_ROM_CMD_END_LSB 0x10 -#define GC_SPS_ICTRL_ROM_CMD_END_MASK 0x10000 -#define GC_SPS_ICTRL_ROM_CMD_END_SIZE 0x1 -#define GC_SPS_ICTRL_ROM_CMD_END_DEFAULT 0x0 -#define GC_SPS_ICTRL_ROM_CMD_END_OFFSET 0xbc -#define GC_SPS_ICTRL_REGION0_BUF_LVL_LSB 0x11 -#define GC_SPS_ICTRL_REGION0_BUF_LVL_MASK 0x20000 -#define GC_SPS_ICTRL_REGION0_BUF_LVL_SIZE 0x1 -#define GC_SPS_ICTRL_REGION0_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ICTRL_REGION0_BUF_LVL_OFFSET 0xbc -#define GC_SPS_ICTRL_REGION1_BUF_LVL_LSB 0x12 -#define GC_SPS_ICTRL_REGION1_BUF_LVL_MASK 0x40000 -#define GC_SPS_ICTRL_REGION1_BUF_LVL_SIZE 0x1 -#define GC_SPS_ICTRL_REGION1_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ICTRL_REGION1_BUF_LVL_OFFSET 0xbc -#define GC_SPS_ICTRL_REGION2_BUF_LVL_LSB 0x13 -#define GC_SPS_ICTRL_REGION2_BUF_LVL_MASK 0x80000 -#define GC_SPS_ICTRL_REGION2_BUF_LVL_SIZE 0x1 -#define GC_SPS_ICTRL_REGION2_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ICTRL_REGION2_BUF_LVL_OFFSET 0xbc -#define GC_SPS_ICTRL_REGION3_BUF_LVL_LSB 0x14 -#define GC_SPS_ICTRL_REGION3_BUF_LVL_MASK 0x100000 -#define GC_SPS_ICTRL_REGION3_BUF_LVL_SIZE 0x1 -#define GC_SPS_ICTRL_REGION3_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ICTRL_REGION3_BUF_LVL_OFFSET 0xbc +#define GC_SPS_VAL_SCK_OFFSET 0x50 #define GC_SPS_ISTATE_CTLWR0_LSB 0x0 #define GC_SPS_ISTATE_CTLWR0_MASK 0x1 #define GC_SPS_ISTATE_CTLWR0_SIZE 0x1 #define GC_SPS_ISTATE_CTLWR0_DEFAULT 0x0 -#define GC_SPS_ISTATE_CTLWR0_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR0_OFFSET 0x54 #define GC_SPS_ISTATE_CTLWR1_LSB 0x1 #define GC_SPS_ISTATE_CTLWR1_MASK 0x2 #define GC_SPS_ISTATE_CTLWR1_SIZE 0x1 #define GC_SPS_ISTATE_CTLWR1_DEFAULT 0x0 -#define GC_SPS_ISTATE_CTLWR1_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR1_OFFSET 0x54 #define GC_SPS_ISTATE_CTLWR2_LSB 0x2 #define GC_SPS_ISTATE_CTLWR2_MASK 0x4 #define GC_SPS_ISTATE_CTLWR2_SIZE 0x1 #define GC_SPS_ISTATE_CTLWR2_DEFAULT 0x0 -#define GC_SPS_ISTATE_CTLWR2_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR2_OFFSET 0x54 #define GC_SPS_ISTATE_CTLWR3_LSB 0x3 #define GC_SPS_ISTATE_CTLWR3_MASK 0x8 #define GC_SPS_ISTATE_CTLWR3_SIZE 0x1 #define GC_SPS_ISTATE_CTLWR3_DEFAULT 0x0 -#define GC_SPS_ISTATE_CTLWR3_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR3_OFFSET 0x54 #define GC_SPS_ISTATE_CTLWR4_LSB 0x4 #define GC_SPS_ISTATE_CTLWR4_MASK 0x10 #define GC_SPS_ISTATE_CTLWR4_SIZE 0x1 #define GC_SPS_ISTATE_CTLWR4_DEFAULT 0x0 -#define GC_SPS_ISTATE_CTLWR4_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR4_OFFSET 0x54 #define GC_SPS_ISTATE_CTLWR5_LSB 0x5 #define GC_SPS_ISTATE_CTLWR5_MASK 0x20 #define GC_SPS_ISTATE_CTLWR5_SIZE 0x1 #define GC_SPS_ISTATE_CTLWR5_DEFAULT 0x0 -#define GC_SPS_ISTATE_CTLWR5_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR5_OFFSET 0x54 #define GC_SPS_ISTATE_CTLWR6_LSB 0x6 #define GC_SPS_ISTATE_CTLWR6_MASK 0x40 #define GC_SPS_ISTATE_CTLWR6_SIZE 0x1 #define GC_SPS_ISTATE_CTLWR6_DEFAULT 0x0 -#define GC_SPS_ISTATE_CTLWR6_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR6_OFFSET 0x54 #define GC_SPS_ISTATE_CTLWR7_LSB 0x7 #define GC_SPS_ISTATE_CTLWR7_MASK 0x80 #define GC_SPS_ISTATE_CTLWR7_SIZE 0x1 #define GC_SPS_ISTATE_CTLWR7_DEFAULT 0x0 -#define GC_SPS_ISTATE_CTLWR7_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR7_OFFSET 0x54 #define GC_SPS_ISTATE_CS_ASSERT_LSB 0x8 #define GC_SPS_ISTATE_CS_ASSERT_MASK 0x100 #define GC_SPS_ISTATE_CS_ASSERT_SIZE 0x1 #define GC_SPS_ISTATE_CS_ASSERT_DEFAULT 0x0 -#define GC_SPS_ISTATE_CS_ASSERT_OFFSET 0xc0 +#define GC_SPS_ISTATE_CS_ASSERT_OFFSET 0x54 #define GC_SPS_ISTATE_CS_DEASSERT_LSB 0x9 #define GC_SPS_ISTATE_CS_DEASSERT_MASK 0x200 #define GC_SPS_ISTATE_CS_DEASSERT_SIZE 0x1 #define GC_SPS_ISTATE_CS_DEASSERT_DEFAULT 0x0 -#define GC_SPS_ISTATE_CS_DEASSERT_OFFSET 0xc0 +#define GC_SPS_ISTATE_CS_DEASSERT_OFFSET 0x54 #define GC_SPS_ISTATE_RXFIFO_OVERFLOW_LSB 0xa #define GC_SPS_ISTATE_RXFIFO_OVERFLOW_MASK 0x400 #define GC_SPS_ISTATE_RXFIFO_OVERFLOW_SIZE 0x1 #define GC_SPS_ISTATE_RXFIFO_OVERFLOW_DEFAULT 0x0 -#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_OFFSET 0xc0 +#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_OFFSET 0x54 #define GC_SPS_ISTATE_TXFIFO_EMPTY_LSB 0xb #define GC_SPS_ISTATE_TXFIFO_EMPTY_MASK 0x800 #define GC_SPS_ISTATE_TXFIFO_EMPTY_SIZE 0x1 #define GC_SPS_ISTATE_TXFIFO_EMPTY_DEFAULT 0x0 -#define GC_SPS_ISTATE_TXFIFO_EMPTY_OFFSET 0xc0 +#define GC_SPS_ISTATE_TXFIFO_EMPTY_OFFSET 0x54 #define GC_SPS_ISTATE_TXFIFO_FULL_LSB 0xc #define GC_SPS_ISTATE_TXFIFO_FULL_MASK 0x1000 #define GC_SPS_ISTATE_TXFIFO_FULL_SIZE 0x1 #define GC_SPS_ISTATE_TXFIFO_FULL_DEFAULT 0x0 -#define GC_SPS_ISTATE_TXFIFO_FULL_OFFSET 0xc0 +#define GC_SPS_ISTATE_TXFIFO_FULL_OFFSET 0x54 #define GC_SPS_ISTATE_TXFIFO_LVL_LSB 0xd #define GC_SPS_ISTATE_TXFIFO_LVL_MASK 0x2000 #define GC_SPS_ISTATE_TXFIFO_LVL_SIZE 0x1 #define GC_SPS_ISTATE_TXFIFO_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_TXFIFO_LVL_OFFSET 0xc0 +#define GC_SPS_ISTATE_TXFIFO_LVL_OFFSET 0x54 #define GC_SPS_ISTATE_RXFIFO_LVL_LSB 0xe #define GC_SPS_ISTATE_RXFIFO_LVL_MASK 0x4000 #define GC_SPS_ISTATE_RXFIFO_LVL_SIZE 0x1 #define GC_SPS_ISTATE_RXFIFO_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_RXFIFO_LVL_OFFSET 0xc0 -#define GC_SPS_ISTATE_ROM_CMD_START_LSB 0xf -#define GC_SPS_ISTATE_ROM_CMD_START_MASK 0x8000 -#define GC_SPS_ISTATE_ROM_CMD_START_SIZE 0x1 -#define GC_SPS_ISTATE_ROM_CMD_START_DEFAULT 0x0 -#define GC_SPS_ISTATE_ROM_CMD_START_OFFSET 0xc0 -#define GC_SPS_ISTATE_ROM_CMD_END_LSB 0x10 -#define GC_SPS_ISTATE_ROM_CMD_END_MASK 0x10000 -#define GC_SPS_ISTATE_ROM_CMD_END_SIZE 0x1 -#define GC_SPS_ISTATE_ROM_CMD_END_DEFAULT 0x0 -#define GC_SPS_ISTATE_ROM_CMD_END_OFFSET 0xc0 -#define GC_SPS_ISTATE_REGION0_BUF_LVL_LSB 0x11 -#define GC_SPS_ISTATE_REGION0_BUF_LVL_MASK 0x20000 -#define GC_SPS_ISTATE_REGION0_BUF_LVL_SIZE 0x1 -#define GC_SPS_ISTATE_REGION0_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_REGION0_BUF_LVL_OFFSET 0xc0 -#define GC_SPS_ISTATE_REGION1_BUF_LVL_LSB 0x12 -#define GC_SPS_ISTATE_REGION1_BUF_LVL_MASK 0x40000 -#define GC_SPS_ISTATE_REGION1_BUF_LVL_SIZE 0x1 -#define GC_SPS_ISTATE_REGION1_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_REGION1_BUF_LVL_OFFSET 0xc0 -#define GC_SPS_ISTATE_REGION2_BUF_LVL_LSB 0x13 -#define GC_SPS_ISTATE_REGION2_BUF_LVL_MASK 0x80000 -#define GC_SPS_ISTATE_REGION2_BUF_LVL_SIZE 0x1 -#define GC_SPS_ISTATE_REGION2_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_REGION2_BUF_LVL_OFFSET 0xc0 -#define GC_SPS_ISTATE_REGION3_BUF_LVL_LSB 0x14 -#define GC_SPS_ISTATE_REGION3_BUF_LVL_MASK 0x100000 -#define GC_SPS_ISTATE_REGION3_BUF_LVL_SIZE 0x1 -#define GC_SPS_ISTATE_REGION3_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_REGION3_BUF_LVL_OFFSET 0xc0 +#define GC_SPS_ISTATE_RXFIFO_LVL_OFFSET 0x54 #define GC_SPS_ISTATE_CLR_CTLWR0_LSB 0x0 #define GC_SPS_ISTATE_CLR_CTLWR0_MASK 0x1 #define GC_SPS_ISTATE_CLR_CTLWR0_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CTLWR0_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CTLWR0_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR0_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_CTLWR1_LSB 0x1 #define GC_SPS_ISTATE_CLR_CTLWR1_MASK 0x2 #define GC_SPS_ISTATE_CLR_CTLWR1_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CTLWR1_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CTLWR1_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR1_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_CTLWR2_LSB 0x2 #define GC_SPS_ISTATE_CLR_CTLWR2_MASK 0x4 #define GC_SPS_ISTATE_CLR_CTLWR2_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CTLWR2_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CTLWR2_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR2_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_CTLWR3_LSB 0x3 #define GC_SPS_ISTATE_CLR_CTLWR3_MASK 0x8 #define GC_SPS_ISTATE_CLR_CTLWR3_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CTLWR3_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CTLWR3_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR3_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_CTLWR4_LSB 0x4 #define GC_SPS_ISTATE_CLR_CTLWR4_MASK 0x10 #define GC_SPS_ISTATE_CLR_CTLWR4_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CTLWR4_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CTLWR4_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR4_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_CTLWR5_LSB 0x5 #define GC_SPS_ISTATE_CLR_CTLWR5_MASK 0x20 #define GC_SPS_ISTATE_CLR_CTLWR5_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CTLWR5_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CTLWR5_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR5_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_CTLWR6_LSB 0x6 #define GC_SPS_ISTATE_CLR_CTLWR6_MASK 0x40 #define GC_SPS_ISTATE_CLR_CTLWR6_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CTLWR6_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CTLWR6_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR6_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_CTLWR7_LSB 0x7 #define GC_SPS_ISTATE_CLR_CTLWR7_MASK 0x80 #define GC_SPS_ISTATE_CLR_CTLWR7_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CTLWR7_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CTLWR7_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR7_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_CS_ASSERT_LSB 0x8 #define GC_SPS_ISTATE_CLR_CS_ASSERT_MASK 0x100 #define GC_SPS_ISTATE_CLR_CS_ASSERT_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CS_ASSERT_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CS_ASSERT_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CS_ASSERT_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_CS_DEASSERT_LSB 0x9 #define GC_SPS_ISTATE_CLR_CS_DEASSERT_MASK 0x200 #define GC_SPS_ISTATE_CLR_CS_DEASSERT_SIZE 0x1 #define GC_SPS_ISTATE_CLR_CS_DEASSERT_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_CS_DEASSERT_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CS_DEASSERT_OFFSET 0x58 #define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_LSB 0xa #define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_MASK 0x400 #define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_SIZE 0x1 #define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_OFFSET 0xc4 -#define GC_SPS_ISTATE_CLR_ROM_CMD_START_LSB 0xb -#define GC_SPS_ISTATE_CLR_ROM_CMD_START_MASK 0x800 -#define GC_SPS_ISTATE_CLR_ROM_CMD_START_SIZE 0x1 -#define GC_SPS_ISTATE_CLR_ROM_CMD_START_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_ROM_CMD_START_OFFSET 0xc4 -#define GC_SPS_ISTATE_CLR_ROM_CMD_END_LSB 0xc -#define GC_SPS_ISTATE_CLR_ROM_CMD_END_MASK 0x1000 -#define GC_SPS_ISTATE_CLR_ROM_CMD_END_SIZE 0x1 -#define GC_SPS_ISTATE_CLR_ROM_CMD_END_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_ROM_CMD_END_OFFSET 0xc4 -#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_LSB 0xd -#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_MASK 0x2000 -#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_SIZE 0x1 -#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_OFFSET 0xc4 -#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_LSB 0xe -#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_MASK 0x4000 -#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_SIZE 0x1 -#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_OFFSET 0xc4 -#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_LSB 0xf -#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_MASK 0x8000 -#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_SIZE 0x1 -#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_OFFSET 0xc4 -#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_LSB 0x10 -#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_MASK 0x10000 -#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_SIZE 0x1 -#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_OFFSET 0x58 #define GC_SPS_ITOP_CTRLINT0_LSB 0x0 #define GC_SPS_ITOP_CTRLINT0_MASK 0x1 #define GC_SPS_ITOP_CTRLINT0_SIZE 0x1 #define GC_SPS_ITOP_CTRLINT0_DEFAULT 0x0 -#define GC_SPS_ITOP_CTRLINT0_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT0_OFFSET 0x60 #define GC_SPS_ITOP_CTRLINT1_LSB 0x1 #define GC_SPS_ITOP_CTRLINT1_MASK 0x2 #define GC_SPS_ITOP_CTRLINT1_SIZE 0x1 #define GC_SPS_ITOP_CTRLINT1_DEFAULT 0x0 -#define GC_SPS_ITOP_CTRLINT1_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT1_OFFSET 0x60 #define GC_SPS_ITOP_CTRLINT2_LSB 0x2 #define GC_SPS_ITOP_CTRLINT2_MASK 0x4 #define GC_SPS_ITOP_CTRLINT2_SIZE 0x1 #define GC_SPS_ITOP_CTRLINT2_DEFAULT 0x0 -#define GC_SPS_ITOP_CTRLINT2_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT2_OFFSET 0x60 #define GC_SPS_ITOP_CTRLINT3_LSB 0x3 #define GC_SPS_ITOP_CTRLINT3_MASK 0x8 #define GC_SPS_ITOP_CTRLINT3_SIZE 0x1 #define GC_SPS_ITOP_CTRLINT3_DEFAULT 0x0 -#define GC_SPS_ITOP_CTRLINT3_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT3_OFFSET 0x60 #define GC_SPS_ITOP_CTRLINT4_LSB 0x4 #define GC_SPS_ITOP_CTRLINT4_MASK 0x10 #define GC_SPS_ITOP_CTRLINT4_SIZE 0x1 #define GC_SPS_ITOP_CTRLINT4_DEFAULT 0x0 -#define GC_SPS_ITOP_CTRLINT4_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT4_OFFSET 0x60 #define GC_SPS_ITOP_CTRLINT5_LSB 0x5 #define GC_SPS_ITOP_CTRLINT5_MASK 0x20 #define GC_SPS_ITOP_CTRLINT5_SIZE 0x1 #define GC_SPS_ITOP_CTRLINT5_DEFAULT 0x0 -#define GC_SPS_ITOP_CTRLINT5_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT5_OFFSET 0x60 #define GC_SPS_ITOP_CTRLINT6_LSB 0x6 #define GC_SPS_ITOP_CTRLINT6_MASK 0x40 #define GC_SPS_ITOP_CTRLINT6_SIZE 0x1 #define GC_SPS_ITOP_CTRLINT6_DEFAULT 0x0 -#define GC_SPS_ITOP_CTRLINT6_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT6_OFFSET 0x60 #define GC_SPS_ITOP_CTRLINT7_LSB 0x7 #define GC_SPS_ITOP_CTRLINT7_MASK 0x80 #define GC_SPS_ITOP_CTRLINT7_SIZE 0x1 #define GC_SPS_ITOP_CTRLINT7_DEFAULT 0x0 -#define GC_SPS_ITOP_CTRLINT7_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT7_OFFSET 0x60 #define GC_SPS_ITOP_CS_ASSERT_LSB 0x8 #define GC_SPS_ITOP_CS_ASSERT_MASK 0x100 #define GC_SPS_ITOP_CS_ASSERT_SIZE 0x1 #define GC_SPS_ITOP_CS_ASSERT_DEFAULT 0x0 -#define GC_SPS_ITOP_CS_ASSERT_OFFSET 0xf04 +#define GC_SPS_ITOP_CS_ASSERT_OFFSET 0x60 #define GC_SPS_ITOP_CS_DEASSERT_LSB 0x9 #define GC_SPS_ITOP_CS_DEASSERT_MASK 0x200 #define GC_SPS_ITOP_CS_DEASSERT_SIZE 0x1 #define GC_SPS_ITOP_CS_DEASSERT_DEFAULT 0x0 -#define GC_SPS_ITOP_CS_DEASSERT_OFFSET 0xf04 +#define GC_SPS_ITOP_CS_DEASSERT_OFFSET 0x60 #define GC_SPS_ITOP_RXFIFO_OVERFLOW_LSB 0xa #define GC_SPS_ITOP_RXFIFO_OVERFLOW_MASK 0x400 #define GC_SPS_ITOP_RXFIFO_OVERFLOW_SIZE 0x1 #define GC_SPS_ITOP_RXFIFO_OVERFLOW_DEFAULT 0x0 -#define GC_SPS_ITOP_RXFIFO_OVERFLOW_OFFSET 0xf04 +#define GC_SPS_ITOP_RXFIFO_OVERFLOW_OFFSET 0x60 #define GC_SPS_ITOP_TXFIFO_EMPTY_LSB 0xb #define GC_SPS_ITOP_TXFIFO_EMPTY_MASK 0x800 #define GC_SPS_ITOP_TXFIFO_EMPTY_SIZE 0x1 #define GC_SPS_ITOP_TXFIFO_EMPTY_DEFAULT 0x0 -#define GC_SPS_ITOP_TXFIFO_EMPTY_OFFSET 0xf04 +#define GC_SPS_ITOP_TXFIFO_EMPTY_OFFSET 0x60 #define GC_SPS_ITOP_TXFIFO_FULL_LSB 0xc #define GC_SPS_ITOP_TXFIFO_FULL_MASK 0x1000 #define GC_SPS_ITOP_TXFIFO_FULL_SIZE 0x1 #define GC_SPS_ITOP_TXFIFO_FULL_DEFAULT 0x0 -#define GC_SPS_ITOP_TXFIFO_FULL_OFFSET 0xf04 +#define GC_SPS_ITOP_TXFIFO_FULL_OFFSET 0x60 #define GC_SPS_ITOP_TXFIFO_LVL_LSB 0xd #define GC_SPS_ITOP_TXFIFO_LVL_MASK 0x2000 #define GC_SPS_ITOP_TXFIFO_LVL_SIZE 0x1 #define GC_SPS_ITOP_TXFIFO_LVL_DEFAULT 0x0 -#define GC_SPS_ITOP_TXFIFO_LVL_OFFSET 0xf04 +#define GC_SPS_ITOP_TXFIFO_LVL_OFFSET 0x60 #define GC_SPS_ITOP_RXFIFO_LVL_LSB 0xe #define GC_SPS_ITOP_RXFIFO_LVL_MASK 0x4000 #define GC_SPS_ITOP_RXFIFO_LVL_SIZE 0x1 #define GC_SPS_ITOP_RXFIFO_LVL_DEFAULT 0x0 -#define GC_SPS_ITOP_RXFIFO_LVL_OFFSET 0xf04 -#define GC_SPS_ITOP_ROM_CMD_START_LSB 0xf -#define GC_SPS_ITOP_ROM_CMD_START_MASK 0x8000 -#define GC_SPS_ITOP_ROM_CMD_START_SIZE 0x1 -#define GC_SPS_ITOP_ROM_CMD_START_DEFAULT 0x0 -#define GC_SPS_ITOP_ROM_CMD_START_OFFSET 0xf04 -#define GC_SPS_ITOP_ROM_CMD_END_LSB 0x10 -#define GC_SPS_ITOP_ROM_CMD_END_MASK 0x10000 -#define GC_SPS_ITOP_ROM_CMD_END_SIZE 0x1 -#define GC_SPS_ITOP_ROM_CMD_END_DEFAULT 0x0 -#define GC_SPS_ITOP_ROM_CMD_END_OFFSET 0xf04 -#define GC_SPS_ITOP_REGION0_BUF_LVL_LSB 0x11 -#define GC_SPS_ITOP_REGION0_BUF_LVL_MASK 0x20000 -#define GC_SPS_ITOP_REGION0_BUF_LVL_SIZE 0x1 -#define GC_SPS_ITOP_REGION0_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ITOP_REGION0_BUF_LVL_OFFSET 0xf04 -#define GC_SPS_ITOP_REGION1_BUF_LVL_LSB 0x12 -#define GC_SPS_ITOP_REGION1_BUF_LVL_MASK 0x40000 -#define GC_SPS_ITOP_REGION1_BUF_LVL_SIZE 0x1 -#define GC_SPS_ITOP_REGION1_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ITOP_REGION1_BUF_LVL_OFFSET 0xf04 -#define GC_SPS_ITOP_REGION2_BUF_LVL_LSB 0x13 -#define GC_SPS_ITOP_REGION2_BUF_LVL_MASK 0x80000 -#define GC_SPS_ITOP_REGION2_BUF_LVL_SIZE 0x1 -#define GC_SPS_ITOP_REGION2_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ITOP_REGION2_BUF_LVL_OFFSET 0xf04 -#define GC_SPS_ITOP_REGION3_BUF_LVL_LSB 0x14 -#define GC_SPS_ITOP_REGION3_BUF_LVL_MASK 0x100000 -#define GC_SPS_ITOP_REGION3_BUF_LVL_SIZE 0x1 -#define GC_SPS_ITOP_REGION3_BUF_LVL_DEFAULT 0x0 -#define GC_SPS_ITOP_REGION3_BUF_LVL_OFFSET 0xf04 +#define GC_SPS_ITOP_RXFIFO_LVL_OFFSET 0x60 +#define GC_SPS_ICTRL_CTLWR0_LSB 0x0 +#define GC_SPS_ICTRL_CTLWR0_MASK 0x1 +#define GC_SPS_ICTRL_CTLWR0_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR0_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR0_OFFSET 0x64 +#define GC_SPS_ICTRL_CTLWR1_LSB 0x1 +#define GC_SPS_ICTRL_CTLWR1_MASK 0x2 +#define GC_SPS_ICTRL_CTLWR1_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR1_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR1_OFFSET 0x64 +#define GC_SPS_ICTRL_CTLWR2_LSB 0x2 +#define GC_SPS_ICTRL_CTLWR2_MASK 0x4 +#define GC_SPS_ICTRL_CTLWR2_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR2_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR2_OFFSET 0x64 +#define GC_SPS_ICTRL_CTLWR3_LSB 0x3 +#define GC_SPS_ICTRL_CTLWR3_MASK 0x8 +#define GC_SPS_ICTRL_CTLWR3_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR3_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR3_OFFSET 0x64 +#define GC_SPS_ICTRL_CTLWR4_LSB 0x4 +#define GC_SPS_ICTRL_CTLWR4_MASK 0x10 +#define GC_SPS_ICTRL_CTLWR4_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR4_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR4_OFFSET 0x64 +#define GC_SPS_ICTRL_CTLWR5_LSB 0x5 +#define GC_SPS_ICTRL_CTLWR5_MASK 0x20 +#define GC_SPS_ICTRL_CTLWR5_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR5_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR5_OFFSET 0x64 +#define GC_SPS_ICTRL_CTLWR6_LSB 0x6 +#define GC_SPS_ICTRL_CTLWR6_MASK 0x40 +#define GC_SPS_ICTRL_CTLWR6_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR6_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR6_OFFSET 0x64 +#define GC_SPS_ICTRL_CTLWR7_LSB 0x7 +#define GC_SPS_ICTRL_CTLWR7_MASK 0x80 +#define GC_SPS_ICTRL_CTLWR7_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR7_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR7_OFFSET 0x64 +#define GC_SPS_ICTRL_CS_ASSERT_LSB 0x8 +#define GC_SPS_ICTRL_CS_ASSERT_MASK 0x100 +#define GC_SPS_ICTRL_CS_ASSERT_SIZE 0x1 +#define GC_SPS_ICTRL_CS_ASSERT_DEFAULT 0x0 +#define GC_SPS_ICTRL_CS_ASSERT_OFFSET 0x64 +#define GC_SPS_ICTRL_CS_DEASSERT_LSB 0x9 +#define GC_SPS_ICTRL_CS_DEASSERT_MASK 0x200 +#define GC_SPS_ICTRL_CS_DEASSERT_SIZE 0x1 +#define GC_SPS_ICTRL_CS_DEASSERT_DEFAULT 0x0 +#define GC_SPS_ICTRL_CS_DEASSERT_OFFSET 0x64 +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_LSB 0xa +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_MASK 0x400 +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_SIZE 0x1 +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_OFFSET 0x64 +#define GC_SPS_ICTRL_TXFIFO_EMPTY_LSB 0xb +#define GC_SPS_ICTRL_TXFIFO_EMPTY_MASK 0x800 +#define GC_SPS_ICTRL_TXFIFO_EMPTY_SIZE 0x1 +#define GC_SPS_ICTRL_TXFIFO_EMPTY_DEFAULT 0x0 +#define GC_SPS_ICTRL_TXFIFO_EMPTY_OFFSET 0x64 +#define GC_SPS_ICTRL_TXFIFO_FULL_LSB 0xc +#define GC_SPS_ICTRL_TXFIFO_FULL_MASK 0x1000 +#define GC_SPS_ICTRL_TXFIFO_FULL_SIZE 0x1 +#define GC_SPS_ICTRL_TXFIFO_FULL_DEFAULT 0x0 +#define GC_SPS_ICTRL_TXFIFO_FULL_OFFSET 0x64 +#define GC_SPS_ICTRL_TXFIFO_LVL_LSB 0xd +#define GC_SPS_ICTRL_TXFIFO_LVL_MASK 0x2000 +#define GC_SPS_ICTRL_TXFIFO_LVL_SIZE 0x1 +#define GC_SPS_ICTRL_TXFIFO_LVL_DEFAULT 0x0 +#define GC_SPS_ICTRL_TXFIFO_LVL_OFFSET 0x64 +#define GC_SPS_ICTRL_RXFIFO_LVL_LSB 0xe +#define GC_SPS_ICTRL_RXFIFO_LVL_MASK 0x4000 +#define GC_SPS_ICTRL_RXFIFO_LVL_SIZE 0x1 +#define GC_SPS_ICTRL_RXFIFO_LVL_DEFAULT 0x0 +#define GC_SPS_ICTRL_RXFIFO_LVL_OFFSET 0x64 +#define GC_SPS_EEPROM_CTRL_ADDR_MODE_LSB 0x0 +#define GC_SPS_EEPROM_CTRL_ADDR_MODE_MASK 0x1 +#define GC_SPS_EEPROM_CTRL_ADDR_MODE_SIZE 0x1 +#define GC_SPS_EEPROM_CTRL_ADDR_MODE_DEFAULT 0x0 +#define GC_SPS_EEPROM_CTRL_ADDR_MODE_OFFSET 0x400 +#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_LSB 0x1 +#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_MASK 0x2 +#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_SIZE 0x1 +#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_DEFAULT 0x0 +#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_OFFSET 0x400 +#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_LSB 0x2 +#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_MASK 0x4 +#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_SIZE 0x1 +#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_DEFAULT 0x0 +#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_OFFSET 0x400 +#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_LSB 0x3 +#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_MASK 0x8 +#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_SIZE 0x1 +#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_DEFAULT 0x0 +#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_OFFSET 0x400 +#define GC_SPS_EEPROM_CTRL_RAM_DIS_LSB 0x4 +#define GC_SPS_EEPROM_CTRL_RAM_DIS_MASK 0x10 +#define GC_SPS_EEPROM_CTRL_RAM_DIS_SIZE 0x1 +#define GC_SPS_EEPROM_CTRL_RAM_DIS_DEFAULT 0x0 +#define GC_SPS_EEPROM_CTRL_RAM_DIS_OFFSET 0x400 +#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_LSB 0x5 +#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_MASK 0x20 +#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_SIZE 0x1 +#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_DEFAULT 0x0 +#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_OFFSET 0x400 +#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_LSB 0x6 +#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_MASK 0x3c0 +#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_SIZE 0x4 +#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_DEFAULT 0x2 +#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_OFFSET 0x400 +#define GC_SPS_BUSY_OPCODE0_EN_LSB 0x0 +#define GC_SPS_BUSY_OPCODE0_EN_MASK 0x1 +#define GC_SPS_BUSY_OPCODE0_EN_SIZE 0x1 +#define GC_SPS_BUSY_OPCODE0_EN_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE0_EN_OFFSET 0x40c +#define GC_SPS_BUSY_OPCODE0_VALUE_LSB 0x1 +#define GC_SPS_BUSY_OPCODE0_VALUE_MASK 0x1fe +#define GC_SPS_BUSY_OPCODE0_VALUE_SIZE 0x8 +#define GC_SPS_BUSY_OPCODE0_VALUE_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE0_VALUE_OFFSET 0x40c +#define GC_SPS_BUSY_OPCODE1_EN_LSB 0x0 +#define GC_SPS_BUSY_OPCODE1_EN_MASK 0x1 +#define GC_SPS_BUSY_OPCODE1_EN_SIZE 0x1 +#define GC_SPS_BUSY_OPCODE1_EN_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE1_EN_OFFSET 0x410 +#define GC_SPS_BUSY_OPCODE1_VALUE_LSB 0x1 +#define GC_SPS_BUSY_OPCODE1_VALUE_MASK 0x1fe +#define GC_SPS_BUSY_OPCODE1_VALUE_SIZE 0x8 +#define GC_SPS_BUSY_OPCODE1_VALUE_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE1_VALUE_OFFSET 0x410 +#define GC_SPS_BUSY_OPCODE2_EN_LSB 0x0 +#define GC_SPS_BUSY_OPCODE2_EN_MASK 0x1 +#define GC_SPS_BUSY_OPCODE2_EN_SIZE 0x1 +#define GC_SPS_BUSY_OPCODE2_EN_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE2_EN_OFFSET 0x414 +#define GC_SPS_BUSY_OPCODE2_VALUE_LSB 0x1 +#define GC_SPS_BUSY_OPCODE2_VALUE_MASK 0x1fe +#define GC_SPS_BUSY_OPCODE2_VALUE_SIZE 0x8 +#define GC_SPS_BUSY_OPCODE2_VALUE_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE2_VALUE_OFFSET 0x414 +#define GC_SPS_BUSY_OPCODE3_EN_LSB 0x0 +#define GC_SPS_BUSY_OPCODE3_EN_MASK 0x1 +#define GC_SPS_BUSY_OPCODE3_EN_SIZE 0x1 +#define GC_SPS_BUSY_OPCODE3_EN_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE3_EN_OFFSET 0x418 +#define GC_SPS_BUSY_OPCODE3_VALUE_LSB 0x1 +#define GC_SPS_BUSY_OPCODE3_VALUE_MASK 0x1fe +#define GC_SPS_BUSY_OPCODE3_VALUE_SIZE 0x8 +#define GC_SPS_BUSY_OPCODE3_VALUE_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE3_VALUE_OFFSET 0x418 +#define GC_SPS_BUSY_OPCODE4_EN_LSB 0x0 +#define GC_SPS_BUSY_OPCODE4_EN_MASK 0x1 +#define GC_SPS_BUSY_OPCODE4_EN_SIZE 0x1 +#define GC_SPS_BUSY_OPCODE4_EN_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE4_EN_OFFSET 0x41c +#define GC_SPS_BUSY_OPCODE4_VALUE_LSB 0x1 +#define GC_SPS_BUSY_OPCODE4_VALUE_MASK 0x1fe +#define GC_SPS_BUSY_OPCODE4_VALUE_SIZE 0x8 +#define GC_SPS_BUSY_OPCODE4_VALUE_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE4_VALUE_OFFSET 0x41c +#define GC_SPS_BUSY_OPCODE5_EN_LSB 0x0 +#define GC_SPS_BUSY_OPCODE5_EN_MASK 0x1 +#define GC_SPS_BUSY_OPCODE5_EN_SIZE 0x1 +#define GC_SPS_BUSY_OPCODE5_EN_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE5_EN_OFFSET 0x420 +#define GC_SPS_BUSY_OPCODE5_VALUE_LSB 0x1 +#define GC_SPS_BUSY_OPCODE5_VALUE_MASK 0x1fe +#define GC_SPS_BUSY_OPCODE5_VALUE_SIZE 0x8 +#define GC_SPS_BUSY_OPCODE5_VALUE_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE5_VALUE_OFFSET 0x420 +#define GC_SPS_BUSY_OPCODE6_EN_LSB 0x0 +#define GC_SPS_BUSY_OPCODE6_EN_MASK 0x1 +#define GC_SPS_BUSY_OPCODE6_EN_SIZE 0x1 +#define GC_SPS_BUSY_OPCODE6_EN_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE6_EN_OFFSET 0x424 +#define GC_SPS_BUSY_OPCODE6_VALUE_LSB 0x1 +#define GC_SPS_BUSY_OPCODE6_VALUE_MASK 0x1fe +#define GC_SPS_BUSY_OPCODE6_VALUE_SIZE 0x8 +#define GC_SPS_BUSY_OPCODE6_VALUE_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE6_VALUE_OFFSET 0x424 +#define GC_SPS_BUSY_OPCODE7_EN_LSB 0x0 +#define GC_SPS_BUSY_OPCODE7_EN_MASK 0x1 +#define GC_SPS_BUSY_OPCODE7_EN_SIZE 0x1 +#define GC_SPS_BUSY_OPCODE7_EN_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE7_EN_OFFSET 0x428 +#define GC_SPS_BUSY_OPCODE7_VALUE_LSB 0x1 +#define GC_SPS_BUSY_OPCODE7_VALUE_MASK 0x1fe +#define GC_SPS_BUSY_OPCODE7_VALUE_SIZE 0x8 +#define GC_SPS_BUSY_OPCODE7_VALUE_DEFAULT 0x0 +#define GC_SPS_BUSY_OPCODE7_VALUE_OFFSET 0x428 +#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_LSB 0x0 +#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_MASK 0x1 +#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_SIZE 0x1 +#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_OFFSET 0x4dc +#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_LSB 0x1 +#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_MASK 0x3fe +#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_SIZE 0x9 +#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_OFFSET 0x4dc +#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_LSB 0x0 +#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_MASK 0x1 +#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_SIZE 0x1 +#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_OFFSET 0x4e0 +#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_LSB 0x1 +#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_MASK 0x3fe +#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_SIZE 0x9 +#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_OFFSET 0x4e0 +#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_LSB 0x0 +#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_MASK 0x1 +#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_SIZE 0x1 +#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_OFFSET 0x4e4 +#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_LSB 0x1 +#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_MASK 0x3fe +#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_SIZE 0x9 +#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_OFFSET 0x4e4 +#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_LSB 0x0 +#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_MASK 0x1 +#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_SIZE 0x1 +#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_OFFSET 0x4e8 +#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_LSB 0x1 +#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_MASK 0x3fe +#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_SIZE 0x9 +#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_DEFAULT 0x0 +#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_OFFSET 0x4e8 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_LSB 0x0 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_MASK 0x1 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_SIZE 0x1 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x560 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_LSB 0x1 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_MASK 0x2 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x560 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_LSB 0x2 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_MASK 0x4 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_OFFSET 0x560 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_LSB 0x3 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_MASK 0x8 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_OFFSET 0x560 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_LSB 0x4 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_MASK 0x10 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_OFFSET 0x560 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_LSB 0x5 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_MASK 0x20 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_OFFSET 0x560 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_LSB 0x6 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_MASK 0x40 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_OFFSET 0x560 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_LSB 0x0 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_MASK 0x1 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_SIZE 0x1 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x564 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_LSB 0x1 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_MASK 0x2 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x564 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_LSB 0x2 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_MASK 0x4 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_OFFSET 0x564 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_LSB 0x3 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_MASK 0x8 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_OFFSET 0x564 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_LSB 0x4 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_MASK 0x10 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_OFFSET 0x564 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_LSB 0x5 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_MASK 0x20 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_OFFSET 0x564 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_LSB 0x6 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_MASK 0x40 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_OFFSET 0x564 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_LSB 0x0 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_MASK 0x1 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_SIZE 0x1 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x568 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_LSB 0x1 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_MASK 0x2 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x568 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_LSB 0x2 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_MASK 0x4 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_OFFSET 0x568 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_LSB 0x3 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_MASK 0x8 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_OFFSET 0x568 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_LSB 0x4 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_MASK 0x10 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_OFFSET 0x568 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_LSB 0x5 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_MASK 0x20 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_OFFSET 0x568 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_LSB 0x6 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_MASK 0x40 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_SIZE 0x1 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_DEFAULT 0x0 +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_OFFSET 0x568 #define GC_TEMP_VERSION_CHANGE_LSB 0x0 #define GC_TEMP_VERSION_CHANGE_MASK 0xffffff #define GC_TEMP_VERSION_CHANGE_SIZE 0x18 -#define GC_TEMP_VERSION_CHANGE_DEFAULT 0xc178 +#define GC_TEMP_VERSION_CHANGE_DEFAULT 0xed82 #define GC_TEMP_VERSION_CHANGE_OFFSET 0x0 #define GC_TEMP_VERSION_REVISION_LSB 0x18 #define GC_TEMP_VERSION_REVISION_MASK 0xff000000 #define GC_TEMP_VERSION_REVISION_SIZE 0x8 -#define GC_TEMP_VERSION_REVISION_DEFAULT 0xd +#define GC_TEMP_VERSION_REVISION_DEFAULT 0x4 #define GC_TEMP_VERSION_REVISION_OFFSET 0x0 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_LSB 0x0 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_MASK 0x1 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_SIZE 0x1 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_DEFAULT 0x0 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_OFFSET 0x4 -#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_LSB 0x1 -#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_MASK 0x2 -#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_SIZE 0x1 -#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_DEFAULT 0x0 -#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_OFFSET 0x4 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_LSB 0x2 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_MASK 0x4 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_SIZE 0x1 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DEFAULT 0x0 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_OFFSET 0x4 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_LSB 0x3 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_MASK 0x8 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_SIZE 0x1 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_DEFAULT 0x0 -#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_OFFSET 0x4 -#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_LSB 0x4 -#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_MASK 0x10 +#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_LSB 0x1 +#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_MASK 0x2 #define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_SIZE 0x1 #define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_DEFAULT 0x0 #define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_OFFSET 0x4 @@ -10312,23 +15474,8 @@ #define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_SIZE 0x1 #define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_DEFAULT 0x0 #define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_OFFSET 0x8 -#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_LSB 0x1 -#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_MASK 0x2 -#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_SIZE 0x1 -#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_DEFAULT 0x0 -#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_OFFSET 0x8 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_LSB 0x2 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_MASK 0x4 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_SIZE 0x1 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DEFAULT 0x0 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_OFFSET 0x8 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_LSB 0x3 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_MASK 0x8 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_SIZE 0x1 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_DEFAULT 0x0 -#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_OFFSET 0x8 -#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_LSB 0x4 -#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_MASK 0x10 +#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_LSB 0x1 +#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_MASK 0x2 #define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_SIZE 0x1 #define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_DEFAULT 0x0 #define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_OFFSET 0x8 @@ -10337,23 +15484,8 @@ #define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_SIZE 0x1 #define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_DEFAULT 0x0 #define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_OFFSET 0xc -#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_LSB 0x1 -#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_MASK 0x2 -#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_SIZE 0x1 -#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_DEFAULT 0x0 -#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_OFFSET 0xc -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_LSB 0x2 -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_MASK 0x4 -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_SIZE 0x1 -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DEFAULT 0x0 -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_OFFSET 0xc -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_LSB 0x3 -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_MASK 0x8 -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_SIZE 0x1 -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_DEFAULT 0x0 -#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_OFFSET 0xc -#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_LSB 0x4 -#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_MASK 0x10 +#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_LSB 0x1 +#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_MASK 0x2 #define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_SIZE 0x1 #define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_DEFAULT 0x0 #define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_OFFSET 0xc @@ -10622,16 +15754,6 @@ #define GC_TIMELS_TIMER0_STATUS_WRAPPED_SIZE 0x1 #define GC_TIMELS_TIMER0_STATUS_WRAPPED_DEFAULT 0x0 #define GC_TIMELS_TIMER0_STATUS_WRAPPED_OFFSET 0x4 -#define GC_TIMELS_TIMER0_SETHOLD_EN_LSB 0x0 -#define GC_TIMELS_TIMER0_SETHOLD_EN_MASK 0x1 -#define GC_TIMELS_TIMER0_SETHOLD_EN_SIZE 0x1 -#define GC_TIMELS_TIMER0_SETHOLD_EN_DEFAULT 0x0 -#define GC_TIMELS_TIMER0_SETHOLD_EN_OFFSET 0x28 -#define GC_TIMELS_TIMER0_CLRHOLD_EN_LSB 0x0 -#define GC_TIMELS_TIMER0_CLRHOLD_EN_MASK 0x1 -#define GC_TIMELS_TIMER0_CLRHOLD_EN_SIZE 0x1 -#define GC_TIMELS_TIMER0_CLRHOLD_EN_DEFAULT 0x0 -#define GC_TIMELS_TIMER0_CLRHOLD_EN_OFFSET 0x2c #define GC_TIMELS_TIMER1_CONTROL_ENABLE_LSB 0x0 #define GC_TIMELS_TIMER1_CONTROL_ENABLE_MASK 0x1 #define GC_TIMELS_TIMER1_CONTROL_ENABLE_SIZE 0x1 @@ -10687,16 +15809,6 @@ #define GC_TIMELS_TIMER1_STATUS_WRAPPED_SIZE 0x1 #define GC_TIMELS_TIMER1_STATUS_WRAPPED_DEFAULT 0x0 #define GC_TIMELS_TIMER1_STATUS_WRAPPED_OFFSET 0x44 -#define GC_TIMELS_TIMER1_SETHOLD_EN_LSB 0x0 -#define GC_TIMELS_TIMER1_SETHOLD_EN_MASK 0x1 -#define GC_TIMELS_TIMER1_SETHOLD_EN_SIZE 0x1 -#define GC_TIMELS_TIMER1_SETHOLD_EN_DEFAULT 0x0 -#define GC_TIMELS_TIMER1_SETHOLD_EN_OFFSET 0x68 -#define GC_TIMELS_TIMER1_CLRHOLD_EN_LSB 0x0 -#define GC_TIMELS_TIMER1_CLRHOLD_EN_MASK 0x1 -#define GC_TIMELS_TIMER1_CLRHOLD_EN_SIZE 0x1 -#define GC_TIMELS_TIMER1_CLRHOLD_EN_DEFAULT 0x0 -#define GC_TIMELS_TIMER1_CLRHOLD_EN_OFFSET 0x6c #define GC_TIMELS_ITOP_TIMINT0_LSB 0x0 #define GC_TIMELS_ITOP_TIMINT0_MASK 0x1 #define GC_TIMELS_ITOP_TIMINT0_SIZE 0x1 @@ -10707,156 +15819,256 @@ #define GC_TIMELS_ITOP_TIMINT1_SIZE 0x1 #define GC_TIMELS_ITOP_TIMINT1_DEFAULT 0x0 #define GC_TIMELS_ITOP_TIMINT1_OFFSET 0xf04 +#define GC_TIMEUS_VERSION_CHANGE_LSB 0x0 +#define GC_TIMEUS_VERSION_CHANGE_MASK 0xffffff +#define GC_TIMEUS_VERSION_CHANGE_SIZE 0x18 +#define GC_TIMEUS_VERSION_CHANGE_DEFAULT 0xea91 +#define GC_TIMEUS_VERSION_CHANGE_OFFSET 0x0 +#define GC_TIMEUS_VERSION_REVISION_LSB 0x18 +#define GC_TIMEUS_VERSION_REVISION_MASK 0xff000000 +#define GC_TIMEUS_VERSION_REVISION_SIZE 0x8 +#define GC_TIMEUS_VERSION_REVISION_DEFAULT 0x8 +#define GC_TIMEUS_VERSION_REVISION_OFFSET 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_LSB 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_MASK 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_SIZE 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_DEFAULT 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_OFFSET 0x4 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_LSB 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_MASK 0x2 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_SIZE 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_DEFAULT 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_OFFSET 0x4 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_LSB 0x2 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_MASK 0x4 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_SIZE 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_DEFAULT 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_OFFSET 0x4 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_LSB 0x3 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_MASK 0x8 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_SIZE 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_DEFAULT 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_OFFSET 0x4 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_LSB 0x4 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_MASK 0x10 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_SIZE 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_DEFAULT 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_OFFSET 0x4 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_LSB 0x5 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_MASK 0x20 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_SIZE 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_DEFAULT 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_OFFSET 0x4 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_LSB 0x6 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_MASK 0x40 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_SIZE 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_DEFAULT 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_OFFSET 0x4 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_LSB 0x7 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_MASK 0x80 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_SIZE 0x1 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_DEFAULT 0x0 +#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_OFFSET 0x4 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_LSB 0x0 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_MASK 0x1 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_SIZE 0x1 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_DEFAULT 0x0 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_OFFSET 0x8 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_LSB 0x1 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_MASK 0x2 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_SIZE 0x1 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_DEFAULT 0x0 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_OFFSET 0x8 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_LSB 0x2 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_MASK 0x4 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_SIZE 0x1 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_DEFAULT 0x0 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_OFFSET 0x8 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_LSB 0x3 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_MASK 0x8 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_SIZE 0x1 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_DEFAULT 0x0 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_OFFSET 0x8 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_LSB 0x4 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_MASK 0x10 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_SIZE 0x1 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_DEFAULT 0x0 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_OFFSET 0x8 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_LSB 0x5 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_MASK 0x20 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_SIZE 0x1 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_DEFAULT 0x0 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_OFFSET 0x8 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_LSB 0x6 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_MASK 0x40 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_SIZE 0x1 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_DEFAULT 0x0 +#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_OFFSET 0x8 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_LSB 0x7 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_MASK 0x80 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_SIZE 0x1 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_DEFAULT 0x0 +#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_OFFSET 0x8 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_LSB 0x0 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_MASK 0x1 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_SIZE 0x1 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_DEFAULT 0x0 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_OFFSET 0xc +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_LSB 0x1 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_MASK 0x2 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_SIZE 0x1 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_DEFAULT 0x0 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_OFFSET 0xc +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_LSB 0x2 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_MASK 0x4 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_SIZE 0x1 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_DEFAULT 0x0 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_OFFSET 0xc +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_LSB 0x3 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_MASK 0x8 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_SIZE 0x1 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_DEFAULT 0x0 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_OFFSET 0xc +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_LSB 0x4 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_MASK 0x10 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_SIZE 0x1 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_DEFAULT 0x0 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_OFFSET 0xc +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_LSB 0x5 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_MASK 0x20 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_SIZE 0x1 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_DEFAULT 0x0 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_OFFSET 0xc +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_LSB 0x6 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_MASK 0x40 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_SIZE 0x1 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_DEFAULT 0x0 +#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_OFFSET 0xc +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_LSB 0x7 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_MASK 0x80 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_SIZE 0x1 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_DEFAULT 0x0 +#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_OFFSET 0xc #define GC_TRNG_VERSION_CHANGE_LSB 0x0 #define GC_TRNG_VERSION_CHANGE_MASK 0xffffff #define GC_TRNG_VERSION_CHANGE_SIZE 0x18 -#define GC_TRNG_VERSION_CHANGE_DEFAULT 0xc241 +#define GC_TRNG_VERSION_CHANGE_DEFAULT 0x10564 #define GC_TRNG_VERSION_CHANGE_OFFSET 0x0 #define GC_TRNG_VERSION_REVISION_LSB 0x18 #define GC_TRNG_VERSION_REVISION_MASK 0xff000000 #define GC_TRNG_VERSION_REVISION_SIZE 0x8 -#define GC_TRNG_VERSION_REVISION_DEFAULT 0x7 +#define GC_TRNG_VERSION_REVISION_DEFAULT 0x14 #define GC_TRNG_VERSION_REVISION_OFFSET 0x0 -#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_LSB 0x0 -#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_MASK 0x1 -#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_SIZE 0x1 -#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_DEFAULT 0x0 -#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_OFFSET 0x4 -#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_LSB 0x1 -#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_MASK 0x2 -#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_SIZE 0x1 -#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_DEFAULT 0x0 -#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_OFFSET 0x4 -#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_LSB 0x2 -#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_MASK 0x4 +#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_LSB 0x0 +#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_MASK 0x1 #define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_SIZE 0x1 #define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_DEFAULT 0x0 #define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_OFFSET 0x4 -#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_LSB 0x3 -#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_MASK 0x8 +#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_LSB 0x1 +#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_MASK 0x2 #define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_SIZE 0x1 #define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_DEFAULT 0x0 #define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_OFFSET 0x4 -#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_LSB 0x4 -#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_MASK 0x10 -#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_SIZE 0x1 -#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_DEFAULT 0x0 -#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_OFFSET 0x4 -#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_LSB 0x5 -#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_MASK 0x20 -#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_SIZE 0x1 -#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_DEFAULT 0x0 -#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_OFFSET 0x4 -#define GC_TRNG_INT_STATE_INTR_TIMEOUT_LSB 0x0 -#define GC_TRNG_INT_STATE_INTR_TIMEOUT_MASK 0x1 -#define GC_TRNG_INT_STATE_INTR_TIMEOUT_SIZE 0x1 -#define GC_TRNG_INT_STATE_INTR_TIMEOUT_DEFAULT 0x0 -#define GC_TRNG_INT_STATE_INTR_TIMEOUT_OFFSET 0x8 -#define GC_TRNG_INT_STATE_INTR_CALC_DONE_LSB 0x1 -#define GC_TRNG_INT_STATE_INTR_CALC_DONE_MASK 0x2 -#define GC_TRNG_INT_STATE_INTR_CALC_DONE_SIZE 0x1 -#define GC_TRNG_INT_STATE_INTR_CALC_DONE_DEFAULT 0x0 -#define GC_TRNG_INT_STATE_INTR_CALC_DONE_OFFSET 0x8 -#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_LSB 0x2 -#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_MASK 0x4 +#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_LSB 0x2 +#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_MASK 0x4 +#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_SIZE 0x1 +#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_DEFAULT 0x0 +#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_OFFSET 0x4 +#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_LSB 0x0 +#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_MASK 0x1 #define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_SIZE 0x1 #define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_DEFAULT 0x0 #define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_OFFSET 0x8 -#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_LSB 0x3 -#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_MASK 0x8 +#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_LSB 0x1 +#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_MASK 0x2 #define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_SIZE 0x1 #define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_DEFAULT 0x0 #define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_OFFSET 0x8 -#define GC_TRNG_INT_STATE_INTR_STAT_40_60_LSB 0x4 -#define GC_TRNG_INT_STATE_INTR_STAT_40_60_MASK 0x10 -#define GC_TRNG_INT_STATE_INTR_STAT_40_60_SIZE 0x1 -#define GC_TRNG_INT_STATE_INTR_STAT_40_60_DEFAULT 0x0 -#define GC_TRNG_INT_STATE_INTR_STAT_40_60_OFFSET 0x8 -#define GC_TRNG_INT_STATE_INTR_STAT_30_70_LSB 0x5 -#define GC_TRNG_INT_STATE_INTR_STAT_30_70_MASK 0x20 -#define GC_TRNG_INT_STATE_INTR_STAT_30_70_SIZE 0x1 -#define GC_TRNG_INT_STATE_INTR_STAT_30_70_DEFAULT 0x0 -#define GC_TRNG_INT_STATE_INTR_STAT_30_70_OFFSET 0x8 -#define GC_TRNG_INT_TEST_INTR_TIMEOUT_LSB 0x0 -#define GC_TRNG_INT_TEST_INTR_TIMEOUT_MASK 0x1 -#define GC_TRNG_INT_TEST_INTR_TIMEOUT_SIZE 0x1 -#define GC_TRNG_INT_TEST_INTR_TIMEOUT_DEFAULT 0x0 -#define GC_TRNG_INT_TEST_INTR_TIMEOUT_OFFSET 0xc -#define GC_TRNG_INT_TEST_INTR_CALC_DONE_LSB 0x1 -#define GC_TRNG_INT_TEST_INTR_CALC_DONE_MASK 0x2 -#define GC_TRNG_INT_TEST_INTR_CALC_DONE_SIZE 0x1 -#define GC_TRNG_INT_TEST_INTR_CALC_DONE_DEFAULT 0x0 -#define GC_TRNG_INT_TEST_INTR_CALC_DONE_OFFSET 0xc -#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_LSB 0x2 -#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_MASK 0x4 +#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_LSB 0x2 +#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_MASK 0x4 +#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_SIZE 0x1 +#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_DEFAULT 0x0 +#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_OFFSET 0x8 +#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_LSB 0x0 +#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_MASK 0x1 #define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_SIZE 0x1 #define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_DEFAULT 0x0 #define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_OFFSET 0xc -#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_LSB 0x3 -#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_MASK 0x8 +#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_LSB 0x1 +#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_MASK 0x2 #define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_SIZE 0x1 #define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_DEFAULT 0x0 #define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_OFFSET 0xc -#define GC_TRNG_INT_TEST_INTR_STAT_40_60_LSB 0x4 -#define GC_TRNG_INT_TEST_INTR_STAT_40_60_MASK 0x10 -#define GC_TRNG_INT_TEST_INTR_STAT_40_60_SIZE 0x1 -#define GC_TRNG_INT_TEST_INTR_STAT_40_60_DEFAULT 0x0 -#define GC_TRNG_INT_TEST_INTR_STAT_40_60_OFFSET 0xc -#define GC_TRNG_INT_TEST_INTR_STAT_30_70_LSB 0x5 -#define GC_TRNG_INT_TEST_INTR_STAT_30_70_MASK 0x20 -#define GC_TRNG_INT_TEST_INTR_STAT_30_70_SIZE 0x1 -#define GC_TRNG_INT_TEST_INTR_STAT_30_70_DEFAULT 0x0 -#define GC_TRNG_INT_TEST_INTR_STAT_30_70_OFFSET 0xc -#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_LSB 0x0 -#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_MASK 0xf -#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_SIZE 0x4 -#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_DEFAULT 0x0 -#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_OFFSET 0x28 -#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_LSB 0x4 -#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_MASK 0xf0 -#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_SIZE 0x4 -#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_DEFAULT 0xf -#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_OFFSET 0x28 +#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_LSB 0x2 +#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_MASK 0x4 +#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_SIZE 0x1 +#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_DEFAULT 0x0 +#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_OFFSET 0xc +#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_LSB 0x0 +#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_MASK 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_SIZE 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_DEFAULT 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_OFFSET 0x10 +#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_LSB 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_MASK 0x2 +#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_SIZE 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_DEFAULT 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_OFFSET 0x10 +#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_LSB 0x2 +#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_MASK 0x4 +#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_SIZE 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_DEFAULT 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_OFFSET 0x10 +#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_LSB 0x3 +#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_MASK 0x8 +#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_SIZE 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_DEFAULT 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_OFFSET 0x10 +#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_LSB 0x4 +#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_MASK 0x10 +#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_SIZE 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_DEFAULT 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_OFFSET 0x10 +#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_LSB 0x5 +#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_MASK 0x20 +#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_SIZE 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_DEFAULT 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_OFFSET 0x10 #define GC_TRNG_FSM_STATE_FSM_IDLE_LSB 0x0 #define GC_TRNG_FSM_STATE_FSM_IDLE_MASK 0x1 #define GC_TRNG_FSM_STATE_FSM_IDLE_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_IDLE_DEFAULT 0x1 -#define GC_TRNG_FSM_STATE_FSM_IDLE_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_FSM_IDLE_OFFSET 0x2c #define GC_TRNG_FSM_STATE_FSM_WAIT_LSB 0x1 #define GC_TRNG_FSM_STATE_FSM_WAIT_MASK 0x2 #define GC_TRNG_FSM_STATE_FSM_WAIT_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_WAIT_DEFAULT 0x0 -#define GC_TRNG_FSM_STATE_FSM_WAIT_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_FSM_WAIT_OFFSET 0x2c #define GC_TRNG_FSM_STATE_FSM_TIMEOUT_LSB 0x2 #define GC_TRNG_FSM_STATE_FSM_TIMEOUT_MASK 0x4 #define GC_TRNG_FSM_STATE_FSM_TIMEOUT_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_TIMEOUT_DEFAULT 0x0 -#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_OFFSET 0x2c #define GC_TRNG_FSM_STATE_FSM_CAPTURE_LSB 0x3 #define GC_TRNG_FSM_STATE_FSM_CAPTURE_MASK 0x8 #define GC_TRNG_FSM_STATE_FSM_CAPTURE_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_CAPTURE_DEFAULT 0x0 -#define GC_TRNG_FSM_STATE_FSM_CAPTURE_OFFSET 0x38 -#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_LSB 0x4 -#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_MASK 0x10 -#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_SIZE 0x1 -#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_DEFAULT 0x0 -#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_OFFSET 0x38 -#define GC_TRNG_FSM_STATE_FSM_FULL_LSB 0x5 -#define GC_TRNG_FSM_STATE_FSM_FULL_MASK 0x20 +#define GC_TRNG_FSM_STATE_FSM_CAPTURE_OFFSET 0x2c +#define GC_TRNG_FSM_STATE_FSM_FULL_LSB 0x4 +#define GC_TRNG_FSM_STATE_FSM_FULL_MASK 0x10 #define GC_TRNG_FSM_STATE_FSM_FULL_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_FULL_DEFAULT 0x0 -#define GC_TRNG_FSM_STATE_FSM_FULL_OFFSET 0x38 -#define GC_TRNG_SLICE_RANGE_LOWER_LSB 0x0 -#define GC_TRNG_SLICE_RANGE_LOWER_MASK 0xf -#define GC_TRNG_SLICE_RANGE_LOWER_SIZE 0x4 -#define GC_TRNG_SLICE_RANGE_LOWER_DEFAULT 0x0 -#define GC_TRNG_SLICE_RANGE_LOWER_OFFSET 0x40 -#define GC_TRNG_SLICE_RANGE_UPPER_LSB 0x4 -#define GC_TRNG_SLICE_RANGE_UPPER_MASK 0xf0 -#define GC_TRNG_SLICE_RANGE_UPPER_SIZE 0x4 -#define GC_TRNG_SLICE_RANGE_UPPER_DEFAULT 0xf -#define GC_TRNG_SLICE_RANGE_UPPER_OFFSET 0x40 +#define GC_TRNG_FSM_STATE_FSM_FULL_OFFSET 0x2c +#define GC_TRNG_ALLOWED_VALUES_MIN_LSB 0x0 +#define GC_TRNG_ALLOWED_VALUES_MIN_MASK 0x7 +#define GC_TRNG_ALLOWED_VALUES_MIN_SIZE 0x3 +#define GC_TRNG_ALLOWED_VALUES_MIN_DEFAULT 0x0 +#define GC_TRNG_ALLOWED_VALUES_MIN_OFFSET 0x30 +#define GC_TRNG_ALLOWED_VALUES_MAX_LSB 0x3 +#define GC_TRNG_ALLOWED_VALUES_MAX_MASK 0x78 +#define GC_TRNG_ALLOWED_VALUES_MAX_SIZE 0x4 +#define GC_TRNG_ALLOWED_VALUES_MAX_DEFAULT 0x0 +#define GC_TRNG_ALLOWED_VALUES_MAX_OFFSET 0x30 #define GC_UART_CTRL_TX_LSB 0x0 #define GC_UART_CTRL_TX_MASK 0x1 #define GC_UART_CTRL_TX_SIZE 0x1 @@ -17857,6 +23069,46 @@ #define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20 #define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 #define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc +#define GC_VOLT_VERSION_CHANGE_LSB 0x0 +#define GC_VOLT_VERSION_CHANGE_MASK 0xffffff +#define GC_VOLT_VERSION_CHANGE_SIZE 0x18 +#define GC_VOLT_VERSION_CHANGE_DEFAULT 0x10218 +#define GC_VOLT_VERSION_CHANGE_OFFSET 0x0 +#define GC_VOLT_VERSION_REVISION_LSB 0x18 +#define GC_VOLT_VERSION_REVISION_MASK 0xff000000 +#define GC_VOLT_VERSION_REVISION_SIZE 0x8 +#define GC_VOLT_VERSION_REVISION_DEFAULT 0x1 +#define GC_VOLT_VERSION_REVISION_OFFSET 0x0 +#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_LSB 0x0 +#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_MASK 0x1 +#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_SIZE 0x1 +#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_DEFAULT 0x0 +#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_LSB 0x1 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_MASK 0x3e +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_SIZE 0x5 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_DEFAULT 0x0 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_LSB 0x6 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_MASK 0x1c0 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_SIZE 0x3 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_DEFAULT 0x0 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_LSB 0x9 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_MASK 0xe00 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_SIZE 0x3 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_DEFAULT 0x0 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_LSB 0xc +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_MASK 0x1f000 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_SIZE 0x5 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_DEFAULT 0x0 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_OFFSET 0x4 +#define GC_VOLT_CONFIG_SERIAL_TEST_EN_LSB 0x0 +#define GC_VOLT_CONFIG_SERIAL_TEST_EN_MASK 0x1 +#define GC_VOLT_CONFIG_SERIAL_TEST_EN_SIZE 0x1 +#define GC_VOLT_CONFIG_SERIAL_TEST_EN_DEFAULT 0x0 +#define GC_VOLT_CONFIG_SERIAL_TEST_EN_OFFSET 0x8 #define GC_WATCHDOG_WDOGCONTROL_INTEN_LSB 0x0 #define GC_WATCHDOG_WDOGCONTROL_INTEN_MASK 0x1 #define GC_WATCHDOG_WDOGCONTROL_INTEN_SIZE 0x1 @@ -17877,220 +23129,970 @@ #define GC_WATCHDOG_WDOGITOP_WDOGINT_SIZE 0x1 #define GC_WATCHDOG_WDOGITOP_WDOGINT_DEFAULT 0x0 #define GC_WATCHDOG_WDOGITOP_WDOGINT_OFFSET 0xf04 -#define GC_XO_OSC_CLKOUT_ADC_EN_LSB 0x0 -#define GC_XO_OSC_CLKOUT_ADC_EN_MASK 0x1 -#define GC_XO_OSC_CLKOUT_ADC_EN_SIZE 0x1 -#define GC_XO_OSC_CLKOUT_ADC_EN_DEFAULT 0x0 -#define GC_XO_OSC_CLKOUT_ADC_EN_OFFSET 0x0 -#define GC_XO_OSC_CLKOUT_PLL_EN_LSB 0x1 -#define GC_XO_OSC_CLKOUT_PLL_EN_MASK 0x2 -#define GC_XO_OSC_CLKOUT_PLL_EN_SIZE 0x1 -#define GC_XO_OSC_CLKOUT_PLL_EN_DEFAULT 0x0 -#define GC_XO_OSC_CLKOUT_PLL_EN_OFFSET 0x0 -#define GC_XO_OSC_CLKOUT_BADC_EN_LSB 0x2 -#define GC_XO_OSC_CLKOUT_BADC_EN_MASK 0x4 -#define GC_XO_OSC_CLKOUT_BADC_EN_SIZE 0x1 -#define GC_XO_OSC_CLKOUT_BADC_EN_DEFAULT 0x0 -#define GC_XO_OSC_CLKOUT_BADC_EN_OFFSET 0x0 -#define GC_XO_OSC_CLKOUT_USB_EN_LSB 0x3 -#define GC_XO_OSC_CLKOUT_USB_EN_MASK 0x8 -#define GC_XO_OSC_CLKOUT_USB_EN_SIZE 0x1 -#define GC_XO_OSC_CLKOUT_USB_EN_DEFAULT 0x0 -#define GC_XO_OSC_CLKOUT_USB_EN_OFFSET 0x0 -#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_LSB 0x0 -#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_MASK 0xf -#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_SIZE 0x4 -#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_DEFAULT 0x6 -#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_OFFSET 0x4 -#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_LSB 0x4 -#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_MASK 0x10 -#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_SIZE 0x1 -#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_DEFAULT 0x0 -#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_OFFSET 0x4 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_LSB 0x0 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_MASK 0xf -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_SIZE 0x4 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_DEFAULT 0x6 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_OFFSET 0x8 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_LSB 0x4 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_MASK 0x10 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_SIZE 0x1 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_DEFAULT 0x0 -#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_OFFSET 0x8 -#define GC_XO_OSC_24_48B_SEL_ADC_LSB 0x0 -#define GC_XO_OSC_24_48B_SEL_ADC_MASK 0x1 -#define GC_XO_OSC_24_48B_SEL_ADC_SIZE 0x1 -#define GC_XO_OSC_24_48B_SEL_ADC_DEFAULT 0x0 -#define GC_XO_OSC_24_48B_SEL_ADC_OFFSET 0xc -#define GC_XO_OSC_24_48B_SEL_PLL_LSB 0x1 -#define GC_XO_OSC_24_48B_SEL_PLL_MASK 0x2 -#define GC_XO_OSC_24_48B_SEL_PLL_SIZE 0x1 -#define GC_XO_OSC_24_48B_SEL_PLL_DEFAULT 0x0 -#define GC_XO_OSC_24_48B_SEL_PLL_OFFSET 0xc -#define GC_XO_OSC_TEST_CLK48_ADC_EN_LSB 0x0 -#define GC_XO_OSC_TEST_CLK48_ADC_EN_MASK 0x1 -#define GC_XO_OSC_TEST_CLK48_ADC_EN_SIZE 0x1 -#define GC_XO_OSC_TEST_CLK48_ADC_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK48_ADC_EN_OFFSET 0x10 -#define GC_XO_OSC_TEST_CLK48_PLL_EN_LSB 0x1 -#define GC_XO_OSC_TEST_CLK48_PLL_EN_MASK 0x2 -#define GC_XO_OSC_TEST_CLK48_PLL_EN_SIZE 0x1 -#define GC_XO_OSC_TEST_CLK48_PLL_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK48_PLL_EN_OFFSET 0x10 -#define GC_XO_OSC_TEST_DIG_EN_LSB 0x2 -#define GC_XO_OSC_TEST_DIG_EN_MASK 0x4 -#define GC_XO_OSC_TEST_DIG_EN_SIZE 0x1 -#define GC_XO_OSC_TEST_DIG_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_DIG_EN_OFFSET 0x10 -#define GC_XO_OSC_RC_TRIM_LSB 0x0 -#define GC_XO_OSC_RC_TRIM_MASK 0xfffffff -#define GC_XO_OSC_RC_TRIM_SIZE 0x1c -#define GC_XO_OSC_RC_TRIM_DEFAULT 0x4444444 -#define GC_XO_OSC_RC_TRIM_OFFSET 0x28 -#define GC_XO_OSC_RC_EN_LSB 0x1c -#define GC_XO_OSC_RC_EN_MASK 0x10000000 -#define GC_XO_OSC_RC_EN_SIZE 0x1 -#define GC_XO_OSC_RC_EN_DEFAULT 0x0 -#define GC_XO_OSC_RC_EN_OFFSET 0x28 -#define GC_XO_OSC_RC_STATUS_TRIM_LSB 0x0 -#define GC_XO_OSC_RC_STATUS_TRIM_MASK 0xfffffff -#define GC_XO_OSC_RC_STATUS_TRIM_SIZE 0x1c -#define GC_XO_OSC_RC_STATUS_TRIM_DEFAULT 0x4444444 -#define GC_XO_OSC_RC_STATUS_TRIM_OFFSET 0x2c -#define GC_XO_OSC_RC_STATUS_EN_LSB 0x1c -#define GC_XO_OSC_RC_STATUS_EN_MASK 0x10000000 -#define GC_XO_OSC_RC_STATUS_EN_SIZE 0x1 -#define GC_XO_OSC_RC_STATUS_EN_DEFAULT 0x0 -#define GC_XO_OSC_RC_STATUS_EN_OFFSET 0x2c +#define GC_XO_VERSION_CHANGE_LSB 0x0 +#define GC_XO_VERSION_CHANGE_MASK 0xffffff +#define GC_XO_VERSION_CHANGE_SIZE 0x18 +#define GC_XO_VERSION_CHANGE_DEFAULT 0x10370 +#define GC_XO_VERSION_CHANGE_OFFSET 0x0 +#define GC_XO_VERSION_REVISION_LSB 0x18 +#define GC_XO_VERSION_REVISION_MASK 0xff000000 +#define GC_XO_VERSION_REVISION_SIZE 0x8 +#define GC_XO_VERSION_REVISION_DEFAULT 0x14 +#define GC_XO_VERSION_REVISION_OFFSET 0x0 +#define GC_XO_CLK_JTR_CTRL_HS_SEL_LSB 0x0 +#define GC_XO_CLK_JTR_CTRL_HS_SEL_MASK 0x1 +#define GC_XO_CLK_JTR_CTRL_HS_SEL_SIZE 0x1 +#define GC_XO_CLK_JTR_CTRL_HS_SEL_DEFAULT 0x1 +#define GC_XO_CLK_JTR_CTRL_HS_SEL_OFFSET 0x4 +#define GC_XO_CLK_JTR_CTRL_SEL_LSB 0x1 +#define GC_XO_CLK_JTR_CTRL_SEL_MASK 0x2 +#define GC_XO_CLK_JTR_CTRL_SEL_SIZE 0x1 +#define GC_XO_CLK_JTR_CTRL_SEL_DEFAULT 0x1 +#define GC_XO_CLK_JTR_CTRL_SEL_OFFSET 0x4 +#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_LSB 0x0 +#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_MASK 0xff +#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_SIZE 0x8 +#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_OFFSET 0x10 +#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_LSB 0x8 +#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_MASK 0xff00 +#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_SIZE 0x8 +#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_OFFSET 0x10 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_LSB 0x0 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_MASK 0x1 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_SIZE 0x1 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_DEFAULT 0x0 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x18 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_LSB 0x1 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_MASK 0x1fe +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_SIZE 0x8 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_DEFAULT 0xf +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x18 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_LSB 0x9 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_MASK 0x200 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_SIZE 0x1 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_DEFAULT 0x0 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x18 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_LSB 0xa +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_MASK 0xc00 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_SIZE 0x2 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_DEFAULT 0x0 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x18 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_LSB 0x0 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_MASK 0x1 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_SIZE 0x1 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_LSB 0x1 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_MASK 0x2 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_SIZE 0x1 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_LSB 0x2 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_MASK 0x4 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_SIZE 0x1 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_LSB 0x3 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_MASK 0x8 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_SIZE 0x1 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_LSB 0x4 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_MASK 0x10 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_SIZE 0x1 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x6c +#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_OFFSET 0x7c +#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_OFFSET 0x80 +#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_OFFSET 0x84 +#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_OFFSET 0x88 +#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_OFFSET 0x8c +#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_OFFSET 0x90 +#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_OFFSET 0x94 +#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_OFFSET 0x98 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_MASK 0xf +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_OFFSET 0x9c +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_OFFSET 0x9c +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_MASK 0xf +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_OFFSET 0xa0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_OFFSET 0xa0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_MASK 0xf +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_OFFSET 0xa4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_OFFSET 0xa4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_MASK 0xf +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_OFFSET 0xa8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_OFFSET 0xa8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_MASK 0xf +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_OFFSET 0xac +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_OFFSET 0xac +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_MASK 0xf +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_OFFSET 0xb0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_OFFSET 0xb0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_MASK 0xf +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_OFFSET 0xb4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_OFFSET 0xb4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_MASK 0xf +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_OFFSET 0xb8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_OFFSET 0xb8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_LSB 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_MASK 0xf +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_OFFSET 0xbc +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_OFFSET 0xbc +#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_OFFSET 0xc0 +#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_OFFSET 0xc4 +#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_OFFSET 0xc8 +#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_OFFSET 0xcc +#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_OFFSET 0xd0 +#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_OFFSET 0xd4 +#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_OFFSET 0xd8 +#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_OFFSET 0xdc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_MASK 0xf +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_OFFSET 0xe0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0xe0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_MASK 0xf +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_OFFSET 0xe4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0xe4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_MASK 0xf +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_OFFSET 0xe8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0xe8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_MASK 0xf +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_OFFSET 0xec +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0xec +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_MASK 0xf +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_OFFSET 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_MASK 0xf +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_OFFSET 0xf4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0xf4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_MASK 0xf +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_OFFSET 0xf8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0xf8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_MASK 0xf +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_OFFSET 0xfc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0xfc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_LSB 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_MASK 0xf +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_OFFSET 0x100 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_LSB 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_MASK 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_SIZE 0x4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x100 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_LSB 0x0 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_MASK 0xffffff +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_SIZE 0x18 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_OFFSET 0x108 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_LSB 0x18 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_MASK 0x1000000 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_SIZE 0x1 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_DEFAULT 0x0 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_OFFSET 0x108 +#define GC_XO_CLK_TIMER_CTRL_HS_SEL_LSB 0x0 +#define GC_XO_CLK_TIMER_CTRL_HS_SEL_MASK 0x1 +#define GC_XO_CLK_TIMER_CTRL_HS_SEL_SIZE 0x1 +#define GC_XO_CLK_TIMER_CTRL_HS_SEL_DEFAULT 0x1 +#define GC_XO_CLK_TIMER_CTRL_HS_SEL_OFFSET 0x10c +#define GC_XO_CLK_TIMER_CTRL_SEL_LSB 0x1 +#define GC_XO_CLK_TIMER_CTRL_SEL_MASK 0x2 +#define GC_XO_CLK_TIMER_CTRL_SEL_SIZE 0x1 +#define GC_XO_CLK_TIMER_CTRL_SEL_DEFAULT 0x1 +#define GC_XO_CLK_TIMER_CTRL_SEL_OFFSET 0x10c +#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_LSB 0x0 +#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_MASK 0xff +#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_SIZE 0x8 +#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_OFFSET 0x118 +#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_LSB 0x8 +#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_MASK 0xff00 +#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_SIZE 0x8 +#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_OFFSET 0x118 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_LSB 0x0 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_MASK 0x1 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_SIZE 0x1 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x120 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_LSB 0x1 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_MASK 0x1fe +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_SIZE 0x8 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_DEFAULT 0xf +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x120 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_LSB 0x9 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_MASK 0x200 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_SIZE 0x1 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x120 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_LSB 0xa +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_MASK 0xc00 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_SIZE 0x2 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x120 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_LSB 0x0 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_MASK 0x1 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_SIZE 0x1 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_LSB 0x1 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_MASK 0x2 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_SIZE 0x1 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_LSB 0x2 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_MASK 0x4 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_SIZE 0x1 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_LSB 0x3 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_MASK 0x8 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_SIZE 0x1 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_LSB 0x4 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_MASK 0x10 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_SIZE 0x1 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x124 +#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_OFFSET 0x134 +#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_OFFSET 0x138 +#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_OFFSET 0x13c +#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_OFFSET 0x140 +#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_OFFSET 0x144 +#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_OFFSET 0x148 +#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_OFFSET 0x14c +#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_OFFSET 0x150 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_MASK 0xf +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_OFFSET 0x154 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_OFFSET 0x154 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_MASK 0xf +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_OFFSET 0x158 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_OFFSET 0x158 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_MASK 0xf +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_OFFSET 0x15c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_OFFSET 0x15c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_MASK 0xf +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_OFFSET 0x160 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_OFFSET 0x160 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_MASK 0xf +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_OFFSET 0x164 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_OFFSET 0x164 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_MASK 0xf +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_OFFSET 0x168 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_OFFSET 0x168 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_MASK 0xf +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_OFFSET 0x16c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_OFFSET 0x16c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_MASK 0xf +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_OFFSET 0x170 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_OFFSET 0x170 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_MASK 0xf +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_OFFSET 0x174 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_OFFSET 0x174 +#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_OFFSET 0x178 +#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_OFFSET 0x17c +#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_OFFSET 0x180 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_OFFSET 0x184 +#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_OFFSET 0x188 +#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_OFFSET 0x18c +#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_OFFSET 0x190 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_MASK 0xffff +#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_SIZE 0x10 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_OFFSET 0x194 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_MASK 0xf +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_OFFSET 0x198 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0x198 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_MASK 0xf +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_OFFSET 0x19c +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0x19c +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_MASK 0xf +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_OFFSET 0x1a0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0x1a0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_MASK 0xf +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_OFFSET 0x1a4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0x1a4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_MASK 0xf +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_OFFSET 0x1a8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0x1a8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_MASK 0xf +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_OFFSET 0x1ac +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0x1ac +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_MASK 0xf +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_OFFSET 0x1b0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0x1b0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_MASK 0xf +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_OFFSET 0x1b4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x1b4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_LSB 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_MASK 0xf +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_OFFSET 0x1b8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_LSB 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_MASK 0xf0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_SIZE 0x4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x1b8 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_LSB 0x0 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_MASK 0xffffff +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_SIZE 0x18 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_OFFSET 0x1c0 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_LSB 0x18 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_MASK 0x1000000 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_SIZE 0x1 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_DEFAULT 0x0 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_OFFSET 0x1c0 +#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_LSB 0x0 +#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_MASK 0xf +#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_SIZE 0x4 +#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_DEFAULT 0x6 +#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_OFFSET 0x1c4 +#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_LSB 0x4 +#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_MASK 0x10 +#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_SIZE 0x1 +#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_OFFSET 0x1c4 +#define GC_XO_OSC_XTL_FREQ2X_SELB_LSB 0x5 +#define GC_XO_OSC_XTL_FREQ2X_SELB_MASK 0x20 +#define GC_XO_OSC_XTL_FREQ2X_SELB_SIZE 0x1 +#define GC_XO_OSC_XTL_FREQ2X_SELB_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FREQ2X_SELB_OFFSET 0x1c4 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_LSB 0x0 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_MASK 0xf +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_SIZE 0x4 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_DEFAULT 0x6 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_LSB 0x4 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_MASK 0x10 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_SIZE 0x1 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_LSB 0x5 +#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_MASK 0x20 +#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_SIZE 0x1 +#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_OFFSET 0x1c8 #define GC_XO_OSC_XTL_RC_FLTR_TRIM_LSB 0x0 #define GC_XO_OSC_XTL_RC_FLTR_TRIM_MASK 0xf #define GC_XO_OSC_XTL_RC_FLTR_TRIM_SIZE 0x4 #define GC_XO_OSC_XTL_RC_FLTR_TRIM_DEFAULT 0x5 -#define GC_XO_OSC_XTL_RC_FLTR_TRIM_OFFSET 0x3c +#define GC_XO_OSC_XTL_RC_FLTR_TRIM_OFFSET 0x1d8 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_LSB 0x4 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_MASK 0x10 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_SIZE 0x1 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_DEFAULT 0x1 -#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_OFFSET 0x3c +#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_OFFSET 0x1d8 #define GC_XO_OSC_XTL_OVRD_TRIM_LSB 0x0 #define GC_XO_OSC_XTL_OVRD_TRIM_MASK 0xf #define GC_XO_OSC_XTL_OVRD_TRIM_SIZE 0x4 #define GC_XO_OSC_XTL_OVRD_TRIM_DEFAULT 0x7 -#define GC_XO_OSC_XTL_OVRD_TRIM_OFFSET 0x40 +#define GC_XO_OSC_XTL_OVRD_TRIM_OFFSET 0x1dc #define GC_XO_OSC_XTL_OVRD_ENB_LSB 0x4 #define GC_XO_OSC_XTL_OVRD_ENB_MASK 0x10 #define GC_XO_OSC_XTL_OVRD_ENB_SIZE 0x1 #define GC_XO_OSC_XTL_OVRD_ENB_DEFAULT 0x1 -#define GC_XO_OSC_XTL_OVRD_ENB_OFFSET 0x40 +#define GC_XO_OSC_XTL_OVRD_ENB_OFFSET 0x1dc #define GC_XO_OSC_XTL_TRIM_CODE_LSB 0x0 #define GC_XO_OSC_XTL_TRIM_CODE_MASK 0xf #define GC_XO_OSC_XTL_TRIM_CODE_SIZE 0x4 #define GC_XO_OSC_XTL_TRIM_CODE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_CODE_OFFSET 0x48 +#define GC_XO_OSC_XTL_TRIM_CODE_OFFSET 0x1e4 #define GC_XO_OSC_XTL_TRIM_EN_LSB 0x4 #define GC_XO_OSC_XTL_TRIM_EN_MASK 0x10 #define GC_XO_OSC_XTL_TRIM_EN_SIZE 0x1 #define GC_XO_OSC_XTL_TRIM_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_EN_OFFSET 0x48 +#define GC_XO_OSC_XTL_TRIM_EN_OFFSET 0x1e4 #define GC_XO_OSC_XTL_TRIM_STAT_CODE_LSB 0x0 #define GC_XO_OSC_XTL_TRIM_STAT_CODE_MASK 0xf #define GC_XO_OSC_XTL_TRIM_STAT_CODE_SIZE 0x4 #define GC_XO_OSC_XTL_TRIM_STAT_CODE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_STAT_CODE_OFFSET 0x4c +#define GC_XO_OSC_XTL_TRIM_STAT_CODE_OFFSET 0x1e8 #define GC_XO_OSC_XTL_TRIM_STAT_EN_LSB 0x4 #define GC_XO_OSC_XTL_TRIM_STAT_EN_MASK 0x10 #define GC_XO_OSC_XTL_TRIM_STAT_EN_SIZE 0x1 #define GC_XO_OSC_XTL_TRIM_STAT_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_STAT_EN_OFFSET 0x4c +#define GC_XO_OSC_XTL_TRIM_STAT_EN_OFFSET 0x1e8 #define GC_XO_OSC_XTL_FSM_DONE_LSB 0x0 #define GC_XO_OSC_XTL_FSM_DONE_MASK 0x1 #define GC_XO_OSC_XTL_FSM_DONE_SIZE 0x1 #define GC_XO_OSC_XTL_FSM_DONE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_DONE_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_DONE_OFFSET 0x1f4 #define GC_XO_OSC_XTL_FSM_TRIM_LSB 0x1 #define GC_XO_OSC_XTL_FSM_TRIM_MASK 0x1e #define GC_XO_OSC_XTL_FSM_TRIM_SIZE 0x4 #define GC_XO_OSC_XTL_FSM_TRIM_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_TRIM_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_TRIM_OFFSET 0x1f4 #define GC_XO_OSC_XTL_FSM_STATUS_LSB 0x5 #define GC_XO_OSC_XTL_FSM_STATUS_MASK 0x20 #define GC_XO_OSC_XTL_FSM_STATUS_SIZE 0x1 #define GC_XO_OSC_XTL_FSM_STATUS_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_STATUS_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_STATUS_OFFSET 0x1f4 #define GC_XO_OSC_XTL_FSM_STATE_LSB 0x6 #define GC_XO_OSC_XTL_FSM_STATE_MASK 0x3c0 #define GC_XO_OSC_XTL_FSM_STATE_SIZE 0x4 #define GC_XO_OSC_XTL_FSM_STATE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_STATE_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_STATE_OFFSET 0x1f4 #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_LSB 0xa #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_MASK 0x400 #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_SIZE 0x1 #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_OFFSET 0x1f4 #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_LSB 0x0 #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_MASK 0xf #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_SIZE 0x4 #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_DEFAULT 0x8 -#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_LSB 0x4 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_MASK 0x30 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_SIZE 0x2 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_LSB 0x6 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_MASK 0xc0 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_SIZE 0x2 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_DEFAULT 0x2 -#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_LSB 0x8 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_MASK 0x700 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_SIZE 0x3 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_DEFAULT 0x4 -#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_LSB 0xb #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_MASK 0xf800 #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_SIZE 0x5 #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_DEFAULT 0xe -#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_LSB 0x10 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_MASK 0x1f0000 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_SIZE 0x5 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_DEFAULT 0xd -#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_OFFSET 0x58 -#define GC_XO_OSC_SETHOLD_RC_TRIM_LSB 0x0 -#define GC_XO_OSC_SETHOLD_RC_TRIM_MASK 0x1 -#define GC_XO_OSC_SETHOLD_RC_TRIM_SIZE 0x1 -#define GC_XO_OSC_SETHOLD_RC_TRIM_DEFAULT 0x0 -#define GC_XO_OSC_SETHOLD_RC_TRIM_OFFSET 0x5c -#define GC_XO_OSC_SETHOLD_XTL_LSB 0x1 -#define GC_XO_OSC_SETHOLD_XTL_MASK 0x2 +#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_OFFSET 0x1f8 +#define GC_XO_OSC_SETHOLD_XTL_LSB 0x0 +#define GC_XO_OSC_SETHOLD_XTL_MASK 0x1 #define GC_XO_OSC_SETHOLD_XTL_SIZE 0x1 #define GC_XO_OSC_SETHOLD_XTL_DEFAULT 0x0 -#define GC_XO_OSC_SETHOLD_XTL_OFFSET 0x5c -#define GC_XO_OSC_SETHOLD_ANA_LSB 0x2 -#define GC_XO_OSC_SETHOLD_ANA_MASK 0x4 +#define GC_XO_OSC_SETHOLD_XTL_OFFSET 0x1fc +#define GC_XO_OSC_SETHOLD_ANA_LSB 0x1 +#define GC_XO_OSC_SETHOLD_ANA_MASK 0x2 #define GC_XO_OSC_SETHOLD_ANA_SIZE 0x1 #define GC_XO_OSC_SETHOLD_ANA_DEFAULT 0x0 -#define GC_XO_OSC_SETHOLD_ANA_OFFSET 0x5c -#define GC_XO_OSC_CLRHOLD_RC_TRIM_LSB 0x0 -#define GC_XO_OSC_CLRHOLD_RC_TRIM_MASK 0x1 -#define GC_XO_OSC_CLRHOLD_RC_TRIM_SIZE 0x1 -#define GC_XO_OSC_CLRHOLD_RC_TRIM_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_RC_TRIM_OFFSET 0x60 -#define GC_XO_OSC_CLRHOLD_XTL_LSB 0x1 -#define GC_XO_OSC_CLRHOLD_XTL_MASK 0x2 +#define GC_XO_OSC_SETHOLD_ANA_OFFSET 0x1fc +#define GC_XO_OSC_CLRHOLD_XTL_LSB 0x0 +#define GC_XO_OSC_CLRHOLD_XTL_MASK 0x1 #define GC_XO_OSC_CLRHOLD_XTL_SIZE 0x1 #define GC_XO_OSC_CLRHOLD_XTL_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_XTL_OFFSET 0x60 -#define GC_XO_OSC_CLRHOLD_ANA_LSB 0x2 -#define GC_XO_OSC_CLRHOLD_ANA_MASK 0x4 +#define GC_XO_OSC_CLRHOLD_XTL_OFFSET 0x200 +#define GC_XO_OSC_CLRHOLD_ANA_LSB 0x1 +#define GC_XO_OSC_CLRHOLD_ANA_MASK 0x2 #define GC_XO_OSC_CLRHOLD_ANA_SIZE 0x1 #define GC_XO_OSC_CLRHOLD_ANA_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_ANA_OFFSET 0x60 +#define GC_XO_OSC_CLRHOLD_ANA_OFFSET 0x200 +#define GC_XO_OSC_TEST_CLK2X_EN_LSB 0x0 +#define GC_XO_OSC_TEST_CLK2X_EN_MASK 0x1 +#define GC_XO_OSC_TEST_CLK2X_EN_SIZE 0x1 +#define GC_XO_OSC_TEST_CLK2X_EN_DEFAULT 0x0 +#define GC_XO_OSC_TEST_CLK2X_EN_OFFSET 0x204 +#define GC_XO_OSC_TEST_CLK_JTR_EN_LSB 0x1 +#define GC_XO_OSC_TEST_CLK_JTR_EN_MASK 0x2 +#define GC_XO_OSC_TEST_CLK_JTR_EN_SIZE 0x1 +#define GC_XO_OSC_TEST_CLK_JTR_EN_DEFAULT 0x0 +#define GC_XO_OSC_TEST_CLK_JTR_EN_OFFSET 0x204 +#define GC_XO_OSC_TEST_CLK_TIMER_EN_LSB 0x2 +#define GC_XO_OSC_TEST_CLK_TIMER_EN_MASK 0x4 +#define GC_XO_OSC_TEST_CLK_TIMER_EN_SIZE 0x1 +#define GC_XO_OSC_TEST_CLK_TIMER_EN_DEFAULT 0x0 +#define GC_XO_OSC_TEST_CLK_TIMER_EN_OFFSET 0x204 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_LSB 0x0 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_MASK 0x1 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_SIZE 0x1 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_LSB 0x1 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_MASK 0x2 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_SIZE 0x1 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_LSB 0x2 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_MASK 0x4 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_SIZE 0x1 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_LSB 0x3 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_MASK 0x8 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_SIZE 0x1 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_LSB 0x4 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_MASK 0x10 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_SIZE 0x1 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_LSB 0x5 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_MASK 0x20 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_SIZE 0x1 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_LSB 0x6 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_MASK 0x40 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x208 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_LSB 0x0 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_MASK 0x1 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_SIZE 0x1 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_DEFAULT 0x0 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_LSB 0x1 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_MASK 0x2 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_SIZE 0x1 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_DEFAULT 0x0 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_LSB 0x2 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_MASK 0x4 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_SIZE 0x1 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_LSB 0x3 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_MASK 0x8 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_SIZE 0x1 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_LSB 0x4 +#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_MASK 0x10 +#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_SIZE 0x1 +#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_DEFAULT 0x0 +#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_LSB 0x5 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_MASK 0x20 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_SIZE 0x1 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_LSB 0x6 +#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_MASK 0x40 +#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 +#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 +#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x20c +#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_LSB 0x0 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_MASK 0x1 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_SIZE 0x1 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_DEFAULT 0x0 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_LSB 0x1 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_MASK 0x2 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_SIZE 0x1 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_DEFAULT 0x0 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_LSB 0x2 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_MASK 0x4 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_SIZE 0x1 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_LSB 0x3 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_MASK 0x8 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_SIZE 0x1 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_LSB 0x4 +#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_MASK 0x10 +#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_SIZE 0x1 +#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_DEFAULT 0x0 +#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_LSB 0x5 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_MASK 0x20 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_SIZE 0x1 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_LSB 0x6 +#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_MASK 0x40 +#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 +#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 +#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x210 #define GC_M3_ICTR_INTLINESNUM_LSB 0x0 #define GC_M3_ICTR_INTLINESNUM_MASK 0xf #define GC_M3_ICTR_INTLINESNUM_SIZE 0x4 -#define GC_M3_ICTR_INTLINESNUM_DEFAULT 0x4 +#define GC_M3_ICTR_INTLINESNUM_DEFAULT 0x7 #define GC_M3_ICTR_INTLINESNUM_OFFSET 0xe004 #define GC_M3_SYST_CSR_ENABLE_LSB 0x0 #define GC_M3_SYST_CSR_ENABLE_MASK 0x1 @@ -18147,24 +24149,11 @@ #define GC_M3_SYST_CALIB_NOREF_SIZE 0x1 #define GC_M3_SYST_CALIB_NOREF_DEFAULT 0x0 #define GC_M3_SYST_CALIB_NOREF_OFFSET 0xe01c +#define GC_CRYPTO_DMEM_DUMMY_SIZE 0x1000 +#define GC_CRYPTO_IMEM_DUMMY_SIZE 0x1000 #define GC_SPI_DATA_SIZE 0x100 #define GC_SPS_DATA_SIZE 0x800 -#define GC_USB_DFIFO_PP0_SIZE 0x1000 -#define GC_USB_DFIFO_PP1_SIZE 0x1000 -#define GC_USB_DFIFO_PP2_SIZE 0x1000 -#define GC_USB_DFIFO_PP3_SIZE 0x1000 -#define GC_USB_DFIFO_PP4_SIZE 0x1000 -#define GC_USB_DFIFO_PP5_SIZE 0x1000 -#define GC_USB_DFIFO_PP6_SIZE 0x1000 -#define GC_USB_DFIFO_PP7_SIZE 0x1000 -#define GC_USB_DFIFO_PP8_SIZE 0x1000 -#define GC_USB_DFIFO_PP9_SIZE 0x1000 -#define GC_USB_DFIFO_PP10_SIZE 0x1000 -#define GC_USB_DFIFO_PP11_SIZE 0x1000 -#define GC_USB_DFIFO_PP12_SIZE 0x1000 -#define GC_USB_DFIFO_PP13_SIZE 0x1000 -#define GC_USB_DFIFO_PP14_SIZE 0x1000 -#define GC_USB_DFIFO_PP15_SIZE 0x1000 +#define GC_SPS_ROM_CMD_SIZE 0x200 #define GC_USB_DFIFO_SIZE 0x1000 #ifdef GC__ENABLE_FLASH_DFT_DEFINITIONS__ #define GC_FLASH_DFT_REGS_ADDR_WIDTH 4 @@ -18211,10 +24200,11 @@ -1 #endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */ -#endif /* __CROS_EC_CR50_FPGA_REGDEFS_H */ -#define GC_CONST_FSH_PE_CONTROL_READ 0x16021765 +#define GC_CONST_FSH_PE_CONTROL_BULKERASE 0x1d1e2bad +#define GC_CONST_FSH_PE_EN 0xb11924e1 #define GC_CONST_FSH_PE_CONTROL_PROGRAM 0x27182818 #define GC_CONST_FSH_PE_CONTROL_ERASE 0x31415927 -#define GC_CONST_FSH_PE_CONTROL_BULKERASE 0x1d1e2bad +#define GC_CONST_FSH_PE_CONTROL_READ 0x16021765 #define GC_CONST_FSH_OVRD_UNLOCK 0x13806488 -#define GC_CONST_FSH_PE_EN 0xb11924e1 + +#endif /* __EC_CHIP_G_CR50_FPGA_REGDEFS_H */ diff --git a/chip/g/gpio.c b/chip/g/gpio.c index e2a6ffe169..95b2a79385 100644 --- a/chip/g/gpio.c +++ b/chip/g/gpio.c @@ -144,11 +144,11 @@ void gpio_pre_init(void) /* Enable clocks */ REG_WRITE_MLV(GR_PMU_PERICLKSET0, - GC_PMU_PERICLKSET0_DGPIO0_MASK, - GC_PMU_PERICLKSET0_DGPIO0_LSB, 1); + GC_PMU_PERICLKSET0_DGPIO0_CLK_MASK, + GC_PMU_PERICLKSET0_DGPIO0_CLK_LSB, 1); REG_WRITE_MLV(GR_PMU_PERICLKSET0, - GC_PMU_PERICLKSET0_DGPIO1_MASK, - GC_PMU_PERICLKSET0_DGPIO1_LSB, 1); + GC_PMU_PERICLKSET0_DGPIO1_CLK_MASK, + GC_PMU_PERICLKSET0_DGPIO1_CLK_LSB, 1); /* Set up the pinmux */ for (i = 0; i < gpio_alt_funcs_count; i++, af++) diff --git a/chip/g/pmu.c b/chip/g/pmu.c index b2841fe289..f6ec4d164d 100644 --- a/chip/g/pmu.c +++ b/chip/g/pmu.c @@ -7,6 +7,11 @@ #include "task.h" /* + * TODO_FPGA this file should be thoroughly reworked when actual support is + * introduced. + */ + +/* * RC Trim constants */ #define RCTRIM_RESOLUTION (12) @@ -52,364 +57,20 @@ void pmu_peripheral_rst(uint32_t periph) GR_PMU_RST1 = 1 << (periph - 32); } -/* - * Internal helper to convert value to trim code - */ -static uint32_t _pmu_value_to_trim(uint32_t val) -{ - uint32_t base = val / 7; - uint32_t mod = val % 7; - uint32_t code = 0x0; - uint32_t digit; - - /* Increasing count from right to left */ - for (digit = 0; digit < 7; digit++) { - if (digit < mod) - code |= (((base + 1) & 0xF) << (4 * digit)); - else - code |= ((base & 0xF) << (4 * digit)); - } - - return code; -} - -/* - * Run the RC calibration counters - * This must be used otherwise the counters may get stuck - */ -static uint32_t _pmu_run_rc_counters(uint32_t load_val, uint32_t trim_val) -{ - uint32_t trim_code; - - /* Convert value to trim code */ - trim_code = _pmu_value_to_trim(trim_val); - - /* Set the trim value */ - GWRITE_FIELD(XO, OSC_RC, TRIM, trim_code); - - /* Reset counters */ - GR_XO_OSC_RC_CAL_RSTB = 0x0; - GR_XO_OSC_RC_CAL_RSTB = 0x1; - - /* Load */ - GR_XO_OSC_RC_CAL_LOAD = load_val; - - /* Do calibration */ - GR_XO_OSC_RC_CAL_START = 0x1; - - /* - * There is a small race condition because of the delay in dregfile. - * The start doesn't actually appear for 2 clock cycles after the write. - * So, poll until done goes low. - */ - while (GR_XO_OSC_RC_CAL_DONE) - ; - - /* Wait until it's done */ - while (!GR_XO_OSC_RC_CAL_DONE) - ; - - /* Calculate the difference */ - return GR_XO_OSC_RC_CAL_LOAD - GR_XO_OSC_RC_CAL_COUNT; -} - -/* - * Calibrate RC trim - */ -uint32_t pmu_calibrate_rc_trim(void) -{ - uint32_t size, iter; - uint32_t mid; - uint32_t diff; - - /* - * Switch to crystal for calibration - * This should work since we are on an uncalibrated RC trim clock - */ - pmu_clock_switch_xo(); - - /* Clear the HOLD signal on dxo */ - GR_XO_OSC_CLRHOLD = GC_XO_OSC_CLRHOLD_RC_TRIM_MASK; - - /* Clear EN bit while iterating through codes */ - GWRITE_FIELD(XO, OSC_RC, EN, 0); - - /* Begin binary search */ - mid = RCTRIM_RANGE_MAX - (RCTRIM_RANGE / 2); - size = RCTRIM_RANGE / 2; - for (iter = 0; iter < 8; iter++) { - /* Run the counters */ - diff = _pmu_run_rc_counters(RCTRIM_LOAD_VAL, mid); - - /* - * Test to see whether we are still outside of - * our desired resolution - */ - if ((diff < -RCTRIM_RESOLUTION) - || (diff > RCTRIM_RESOLUTION)) { - if (diff > 0) - mid -= size / 2; - else - mid += size / 2; - } - - /* Move to next range, round up */ - size = (size + 1) >> 1; - } - - /* Set the final trim value, set EN bit to lock in the code */ - GR_XO_OSC_RC = (_pmu_value_to_trim(mid) << GC_XO_OSC_RC_TRIM_LSB) - | (0x1 << GC_XO_OSC_RC_EN_LSB); - - /* Set EN bit to lock in this trim_code */ - /* GWRITE_FIELD(XO, OSC_RC, EN, 1); */ - - /* Set the HOLD signal on dxo */ - GR_XO_OSC_SETHOLD = GC_XO_OSC_SETHOLD_RC_TRIM_MASK; - - /* Switch back to the RC trim now that we are calibrated */ - /* pmu_clock_switch_rc_trim(); */ - - return _pmu_value_to_trim(mid); -} - -/* - * Switch system clock to RC no trim - */ -uint32_t pmu_clock_switch_rc_notrim(void) -{ - uint32_t osc_sel; - - /* check which clock we are running on */ - osc_sel = GR_PMU_OSC_SELECT_STAT; - - if (osc_sel == GC_PMU_OSC_SELECT_RC) { - /* Already on untrimmed RC */ - return 0; - } else if (osc_sel == GC_PMU_OSC_SELECT_XTL) { - /* Need to switch to RC trimmed first */ - pmu_clock_switch_rc_trim(1); - } - - /* Turn on XO clock */ - pmu_clock_en(PERIPH_XO); - - /* Power up RC notrim clock if it's currently off */ - GWRITE_FIELD(PMU, CLRDIS, RC_NOTRIM, 1); - - /* Switch to the clock */ - GR_PMU_OSC_HOLD_CLR = 0x1; /* make sure the hold signal is clear */ - GR_PMU_OSC_SELECT = GC_PMU_OSC_SELECT_RC; - /* make sure the hold signal is set for future power downs */ - GR_PMU_OSC_HOLD_SET = 0x1; - - return 0; -} /* * enable clock doubler for USB purposes */ void pmu_enable_clock_doubler(void) { - /* enable stuff */ - GREG32(XO, OSC_ADC_CAL_FREQ2X) = - (GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_DEFAULT - << GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_LSB) | - (1 << GC_XO_OSC_ADC_CAL_FREQ2X_EN_LSB); - /* enable more stuff */ - GREG32(XO, OSC_CLKOUT) = - (1 << GC_XO_OSC_CLKOUT_ADC_EN_LSB) | - (1 << GC_XO_OSC_CLKOUT_PLL_EN_LSB) | - (1 << GC_XO_OSC_CLKOUT_BADC_EN_LSB) | - (1 << GC_XO_OSC_CLKOUT_USB_EN_LSB); - - /* make sure doubled clock is selected */ - GREG32(XO, OSC_24_48B_SEL) = GC_XO_OSC_24_48B_SEL_DEFAULT; -} - -/* - * Switch system clock to RC trim - */ -uint32_t pmu_clock_switch_rc_trim(uint32_t skip_calibration) -{ - uint32_t trimmed; - uint32_t trim_code; - uint32_t osc_sel; - - /* check which clock we are running on */ - osc_sel = GREG32(PMU, OSC_SELECT_STAT); - - if (osc_sel == GC_PMU_OSC_SELECT_RC_TRIM) { - /* - * already using the rc_trim so nothing to do here - * make sure the hold signal is set for future power downs - */ - GREG32(PMU, OSC_HOLD_SET) = 0x1; - return 0; - } - - /* Turn on DXO clock so we can write in the trim code in */ - pmu_clock_en(PERIPH_XO); - - /* Disable the RC Trim flops in the glitchless switch */ - GWRITE_FIELD(PMU, OSC_CTRL, RC_TRIM_READYB, 0x1); - - /* Power up the clock if not already powered up */ - GREG32(PMU, CLRDIS) = 1 << GC_PMU_SETDIS_RC_TRIM_LSB; - - /* Check for the trim code in the always-on domain - * before looking at the fuse - */ - if (GREAD_FIELD(XO, OSC_RC_STATUS, EN)) { - trim_code = GREAD_FIELD(XO, OSC_RC_STATUS, TRIM); - trimmed = 1; - } else if (GREAD_FIELD(PMU, FUSE_RD_RC_OSC_26MHZ, EN)) { - trim_code = GREAD_FIELD(PMU, FUSE_RD_RC_OSC_26MHZ, TRIM); - trimmed = 1; - } else { - if (skip_calibration) { - trim_code = GREAD_FIELD(XO, OSC_RC, TRIM); - trimmed = 0; - } else { - trim_code = pmu_calibrate_rc_trim(); - trimmed = 1; - } - } - - /* Write the trim code to dxo */ - if (trimmed) { - /* clear the hold signal */ - GREG32(XO, OSC_CLRHOLD) = GC_XO_OSC_CLRHOLD_RC_TRIM_MASK; - - /* Write the trim code and enable the trim code */ - GREG32(XO, OSC_RC) = (trim_code << GC_XO_OSC_RC_TRIM_LSB) | - (1 << GC_XO_OSC_RC_EN_LSB); - - /* set the hold signal */ - GREG32(XO, OSC_SETHOLD) = 1 << GC_XO_OSC_SETHOLD_RC_TRIM_LSB; - } - - /* Enable the flops for RC TRIM in the glitchless switch */ - GWRITE_FIELD(PMU, OSC_CTRL, RC_TRIM_READYB, 0x0); - - /* - * Switch the select signal - * make sure the hold signal is clear - */ - GREG32(PMU, OSC_HOLD_CLR) = 0x1; - GREG32(PMU, OSC_SELECT) = GC_PMU_OSC_SELECT_RC_TRIM; - - /* make sure the hold signal is set for future power downs */ - GREG32(PMU, OSC_HOLD_SET) = 0x1; - - return !trimmed; } - /* * Switch system clock to XO * @returns The value of XO_OSC_XTL_FSM_STATUS. 0 = okay, 1 = error. */ uint32_t pmu_clock_switch_xo(void) { - uint32_t osc_sel; - uint32_t trim_code, final_trim, fsm_done, fsm_status; - - /* check which clock we are running on */ - osc_sel = GREG32(PMU, OSC_SELECT_STAT); - - if (osc_sel == GC_PMU_OSC_SELECT_XTL) { - /* - * already using the crystal so nothing to do here - * make sure the hold signal is set for future power downs - */ - GREG32(PMU, OSC_HOLD_SET) = 0x1; - return 0; - } else if (osc_sel == GC_PMU_OSC_SELECT_RC) { - /* - * RC untrimmed clock. We must go through - * the trimmed clock first to avoid glitching - */ - pmu_clock_switch_rc_trim(1); - } - - /* Turn on DXO clock so we can write in the trim code in */ - pmu_clock_en(PERIPH_XO); - - /* Disable the XTL Clock */ - GWRITE_FIELD(PMU, OSC_CTRL, XTL_READYB, 0x1); - - /* Power up the clock if not already powered up */ - GREG32(PMU, CLRDIS) = 1 << GC_PMU_CLRDIS_XTL_LSB; - - /* Try to find the trim code */ - trim_code = 0; - - /* - * Check for the trim code in the always-on domain - * before looking at the fuse - */ - if (GREAD_FIELD(XO, OSC_XTL_TRIM_STAT, EN)) { - /* nothing to do */ - trim_code = GREAD_FIELD(XO, OSC_XTL_TRIM_STAT, CODE); - - } else if (GREAD_FIELD(PMU, FUSE_RD_XTL_OSC_26MHZ, EN)) { - - /* push the fuse trim code as the saved trim code */ - trim_code = GREAD_FIELD(PMU, FUSE_RD_XTL_OSC_26MHZ, TRIM); - - /* make sure the hold signal is clear */ - GREG32(XO, OSC_CLRHOLD) = 1 << GC_XO_OSC_CLRHOLD_XTL_LSB; - GREG32(XO, OSC_XTL_TRIM) = - (trim_code << GC_XO_OSC_XTL_TRIM_CODE_LSB) - | (0x1 << GC_XO_OSC_XTL_TRIM_EN_LSB); - } else { - /* Run the crystal FSM to calibrate the crystal trim */ - fsm_done = GREG32(XO, OSC_XTL_FSM); - if (fsm_done & GC_XO_OSC_XTL_FSM_DONE_MASK) { - /* - * If FSM done is high, it means we already ran it - * so let's not run it again - * DO NOTHING - */ - } else { - /* reset FSM */ - GREG32(XO, OSC_XTL_FSM_EN) = 0x0; - GREG32(XO, OSC_XTL_FSM_EN) = GC_XO_OSC_XTL_FSM_EN_KEY; - while (!(fsm_done & GC_XO_OSC_XTL_FSM_DONE_MASK)) - fsm_done = GREG32(XO, OSC_XTL_FSM); - } - } - - /* Check the status and final trim value */ - /* max_trim = GREAD_FIELD(XO, OSC_XTL_FSM_CFG, TRIM_MAX); */ - final_trim = GREAD_FIELD(XO, OSC_XTL_FSM, TRIM); - fsm_status = GREAD_FIELD(XO, OSC_XTL_FSM, STATUS); - - /* - * Save the trim for future powerups - * make sure the hold signal is clear (may have already been cleared) - */ - GREG32(XO, OSC_CLRHOLD) = 1 << GC_XO_OSC_CLRHOLD_XTL_LSB; - GREG32(XO, OSC_XTL_TRIM) = (final_trim << GC_XO_OSC_XTL_TRIM_CODE_LSB) | - (1 << GC_XO_OSC_XTL_TRIM_EN_LSB); - - /* make sure the hold signal is set for future power downs */ - GREG32(XO, OSC_SETHOLD) = 1 << GC_XO_OSC_SETHOLD_XTL_LSB; - - /* Enable the flops for XTL in the glitchless switch */ - GWRITE_FIELD(PMU, OSC_CTRL, XTL_READYB, 0x0); - - /* - * Switch the select signal - * make sure the hold signal is clear - */ - GREG32(PMU, OSC_HOLD_CLR) = 0x1; - GREG32(PMU, OSC_SELECT) = GC_PMU_OSC_SELECT_XTL; - - /* make sure the hold signal is set for future power downs */ - GREG32(PMU, OSC_HOLD_SET) = 0x1; - - return !fsm_status; + return 0; } /* @@ -418,103 +79,6 @@ uint32_t pmu_clock_switch_xo(void) */ void pmu_sleep(void) { - uint32_t val; - - /* Enable PMU sleep interrupts */ - GREG32(PMU, ICTRL) = 1 << GC_PMU_ICTRL_SLEEP_LSB; - - /* nvic_irq_en(GC_IRQNUM_PMU_PMUINT); */ - - /* Enable CPU SLEEPDEEP */ - val = GREG32(M3, SCR); - GREG32(M3, SCR) = val | 0x4; - - /* Enable WIC mode */ - GREG32(PMU, SETWIC) = 1 << GC_PMU_SETWIC_PROC0_LSB; - - /* Disable power domains for entering sleep mode */ - GREG32(PMU, SETDIS) = (1 << GC_PMU_SETDIS_START_LSB) | - (1 << GC_PMU_SETDIS_VDDL_LSB) | - (1 << GC_PMU_SETDIS_VDDA_LSB) | - (1 << GC_PMU_SETDIS_VDDSRM_LSB) | - (1 << GC_PMU_SETDIS_BGAP_LSB) | - (1 << GC_PMU_SETDIS_VDDXO_LSB) | - (1 << GC_PMU_SETDIS_VDDXOLP_LSB) | - (1 << GC_PMU_SETDIS_XTL_LSB) | - (1 << GC_PMU_SETDIS_RC_TRIM_LSB) | - (1 << GC_PMU_SETDIS_RC_NOTRIM_LSB) | - (1 << GC_PMU_SETDIS_BATMON_LSB) | - (1 << GC_PMU_SETDIS_FST_BRNOUT_PWR_LSB) | - (1 << GC_PMU_SETDIS_FST_BRNOUT_LSB); - - /* Wait for exit interrupt - * @todo Add code to disable all non-PMU interrupts. - */ - __asm__("wfi"); - - /* Disable WIC mode */ - GREG32(PMU, CLRWIC) = 1 << GC_PMU_CLRWIC_PROC0_LSB; - - /* Disable CPU SLEEPDEEP */ - val = GREG32(M3, SCR); - GREG32(M3, SCR) = val & (~0x4); - - /* Re-enable power domains */ - GREG32(PMU, CLRDIS) = (1 << GC_PMU_CLRDIS_START_LSB) | - (1 << GC_PMU_CLRDIS_VDDL_LSB) | - (1 << GC_PMU_CLRDIS_VDDA_LSB) | - (1 << GC_PMU_CLRDIS_VDDSRM_LSB) | - (1 << GC_PMU_CLRDIS_VDDIOF_LSB) | - (1 << GC_PMU_CLRDIS_BGAP_LSB) | - (1 << GC_PMU_CLRDIS_VDDXO_LSB); - -#ifdef __FIX_ME__ - GREG32(PMU, CLRDIS) = (1 << GC_PMU_CLRDIS_START_LSB) | - (1 << GC_PMU_CLRDIS_VDDL_LSB) | - (1 << GC_PMU_CLRDIS_VDDA_LSB) | - (1 << GC_PMU_CLRDIS_VDDSRM_LSB) | - (1 << GC_PMU_CLRDIS_BGAP_LSB) | - (1 << GC_PMU_CLRDIS_VDDXO_LSB) | - (1 << GC_PMU_CLRDIS_VDDXOLP_LSB) | - (1 << GC_PMU_CLRDIS_XTL_LSB) | - (1 << GC_PMU_CLRDIS_RC_TRIM_LSB) | - (1 << GC_PMU_CLRDIS_RC_NOTRIM_LSB) | - (1 << GC_PMU_CLRDIS_BATMON_LSB) | - (1 << GC_PMU_CLRDIS_FST_BRNOUT_PWR_LSB) | - (1 << GC_PMU_CLRDIS_FST_BRNOUT_LSB); -#endif -} - -/* - * Enter hibernate mode - * This function does not return. The powerdown exit event will - * cause the CPU to begin executing the system / app bootloader. - * @warning The CPU must be in RC no trim mode - */ -void pmu_hibernate(void) -{ - /* Turn off power to everything except retention domains */ - GREG32(PMU, SETDIS) = (1 << GC_PMU_SETDIS_START_LSB) | - (1 << GC_PMU_SETDIS_VDDL_LSB) | - (1 << GC_PMU_SETDIS_VDDA_LSB) | - (1 << GC_PMU_SETDIS_VDDSRM_LSB) | - (1 << GC_PMU_SETDIS_VDDIOF_LSB) | - (1 << GC_PMU_SETDIS_VDDLK_LSB) | - (1 << GC_PMU_SETDIS_VDDSK_LSB) | - (1 << GC_PMU_SETDIS_BIAS_LSB) | - (1 << GC_PMU_SETDIS_BGAP_LSB) | - (1 << GC_PMU_SETDIS_VDDXO_LSB) | - (1 << GC_PMU_SETDIS_VDDXOLP_LSB) | - (1 << GC_PMU_SETDIS_XTL_LSB) | - (1 << GC_PMU_SETDIS_RC_TRIM_LSB) | - (1 << GC_PMU_SETDIS_RC_NOTRIM_LSB) | - (1 << GC_PMU_SETDIS_BATMON_LSB) | - (1 << GC_PMU_SETDIS_FST_BRNOUT_PWR_LSB) | - (1 << GC_PMU_SETDIS_FST_BRNOUT_LSB); - - /* Wait for powerdown */ - for (;;) - __asm__("wfi"); } /* @@ -525,24 +89,6 @@ void pmu_hibernate(void) */ void pmu_hibernate_exit(void) { - /* Turn on power to everything */ - GREG32(PMU, CLRDIS) = (1 << GC_PMU_CLRDIS_START_LSB) | - (1 << GC_PMU_CLRDIS_VDDL_LSB) | - (1 << GC_PMU_CLRDIS_VDDA_LSB) | - (1 << GC_PMU_CLRDIS_VDDSRM_LSB) | - (1 << GC_PMU_CLRDIS_VDDIOF_LSB) | - (1 << GC_PMU_CLRDIS_VDDLK_LSB) | - (1 << GC_PMU_CLRDIS_VDDSK_LSB) | - (1 << GC_PMU_CLRDIS_BIAS_LSB) | - (1 << GC_PMU_CLRDIS_BGAP_LSB) | - (1 << GC_PMU_CLRDIS_VDDXO_LSB) | - (1 << GC_PMU_CLRDIS_VDDXOLP_LSB) | - (1 << GC_PMU_CLRDIS_XTL_LSB) | - (1 << GC_PMU_CLRDIS_RC_TRIM_LSB) | - (1 << GC_PMU_CLRDIS_RC_NOTRIM_LSB) | - (1 << GC_PMU_CLRDIS_BATMON_LSB) | - (1 << GC_PMU_CLRDIS_FST_BRNOUT_PWR_LSB) | - (1 << GC_PMU_CLRDIS_FST_BRNOUT_LSB); } /* @@ -553,30 +99,6 @@ void pmu_hibernate_exit(void) */ void pmu_powerdown(void) { - /* Turn off power to everything */ - GREG32(PMU, SETDIS) = (1 << GC_PMU_SETDIS_START_LSB) | - (1 << GC_PMU_SETDIS_VDDL_LSB) | - (1 << GC_PMU_SETDIS_VDDA_LSB) | - (1 << GC_PMU_SETDIS_VDDSRM_LSB) | - (1 << GC_PMU_SETDIS_VDDIOF_LSB) | - (1 << GC_PMU_SETDIS_VDDLK_LSB) | - (1 << GC_PMU_SETDIS_VDDSK_LSB) | - (1 << GC_PMU_SETDIS_VDDSRK_LSB) | - (1 << GC_PMU_SETDIS_RETCOMPREF_LSB) | - (1 << GC_PMU_SETDIS_BIAS_LSB) | - (1 << GC_PMU_SETDIS_BGAP_LSB) | - (1 << GC_PMU_SETDIS_VDDXO_LSB) | - (1 << GC_PMU_SETDIS_VDDXOLP_LSB) | - (1 << GC_PMU_SETDIS_XTL_LSB) | - (1 << GC_PMU_SETDIS_RC_TRIM_LSB) | - (1 << GC_PMU_SETDIS_RC_NOTRIM_LSB) | - (1 << GC_PMU_SETDIS_BATMON_LSB) | - (1 << GC_PMU_SETDIS_FST_BRNOUT_PWR_LSB) | - (1 << GC_PMU_SETDIS_FST_BRNOUT_LSB); - - /* Wait for powerdown */ - for (;;) - __asm__("wfi"); } /* @@ -587,26 +109,6 @@ void pmu_powerdown(void) */ void pmu_powerdown_exit(void) { - /* Turn on power to everything */ - GREG32(PMU, CLRDIS) = (1 << GC_PMU_CLRDIS_START_LSB) | - (1 << GC_PMU_CLRDIS_VDDL_LSB) | - (1 << GC_PMU_CLRDIS_VDDA_LSB) | - (1 << GC_PMU_CLRDIS_VDDSRM_LSB) | - (1 << GC_PMU_CLRDIS_VDDIOF_LSB) | - (1 << GC_PMU_CLRDIS_VDDLK_LSB) | - (1 << GC_PMU_CLRDIS_VDDSK_LSB) | - (1 << GC_PMU_CLRDIS_VDDSRK_LSB) | - (1 << GC_PMU_CLRDIS_RETCOMPREF_LSB) | - (1 << GC_PMU_CLRDIS_BIAS_LSB) | - (1 << GC_PMU_CLRDIS_BGAP_LSB) | - (1 << GC_PMU_CLRDIS_VDDXO_LSB) | - (1 << GC_PMU_CLRDIS_VDDXOLP_LSB) | - (1 << GC_PMU_CLRDIS_XTL_LSB) | - (1 << GC_PMU_CLRDIS_RC_TRIM_LSB) | - (1 << GC_PMU_CLRDIS_RC_NOTRIM_LSB) | - (1 << GC_PMU_CLRDIS_BATMON_LSB) | - (1 << GC_PMU_CLRDIS_FST_BRNOUT_PWR_LSB) | - (1 << GC_PMU_CLRDIS_FST_BRNOUT_LSB); } /** @@ -616,4 +118,4 @@ void pmu_interrupt(void) { /* TBD */ } -DECLARE_IRQ(GC_IRQNUM_PMU_PMUINT, pmu_interrupt, 1); +/* DECLARE_IRQ(GC_IRQNUM_PMU_PMUINT, pmu_interrupt, 1); */ diff --git a/chip/g/sps.c b/chip/g/sps.c index 82690b01ba..92b4acf1e4 100644 --- a/chip/g/sps.c +++ b/chip/g/sps.c @@ -234,6 +234,12 @@ int sps_unregister_rx_handler(void) static void sps_init(void) { pmu_clock_en(PERIPH_SPS); + + GWRITE_FIELD(PINMUX, DIOA2_CTL, IE, 1); + GWRITE_FIELD(PINMUX, DIOA6_CTL, IE, 1); + GWRITE_FIELD(PINMUX, DIOA12_CTL, IE, 1); + GWRITE_FIELD(PINMUX, DIOA10_CTL, IE, 0); + } DECLARE_HOOK(HOOK_INIT, sps_init, HOOK_PRIO_DEFAULT); diff --git a/chip/g/system.c b/chip/g/system.c index f02f5807ee..761849ad1c 100644 --- a/chip/g/system.c +++ b/chip/g/system.c @@ -18,8 +18,6 @@ static void check_reset_cause(void) if (reset_source & (1 << GC_PMU_RSTSRC_POR_LSB)) flags |= RESET_FLAG_POWER_ON; - else if (reset_source & (1 << GC_PMU_RSTSRC_RESETB_LSB)) - flags |= RESET_FLAG_RESET_PIN; else if (reset_source & (1 << GC_PMU_RSTSRC_EXIT_LSB)) flags |= RESET_FLAG_WAKE_PIN; @@ -82,20 +80,6 @@ const char *system_get_chip_revision(void) return GC_REVISION_STR; } -int system_set_scratchpad(uint32_t value) -{ - GR_PMU_PWRDN_SCRATCH_HOLD_CLR = 1; - GR_PMU_PWRDN_SCRATCH0 = value; - GR_PMU_PWRDN_SCRATCH_HOLD_SET = 1; - - return EC_SUCCESS; -} - -uint32_t system_get_scratchpad(void) -{ - return GR_PMU_PWRDN_SCRATCH0; -} - /* TODO(crosbug.com/p/33822): Where can we store stuff persistently? */ int system_get_vbnvcontext(uint8_t *block) { diff --git a/chip/g/watchdog.c b/chip/g/watchdog.c index e5c3f11d12..2a827b09a8 100644 --- a/chip/g/watchdog.c +++ b/chip/g/watchdog.c @@ -77,9 +77,7 @@ DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); int watchdog_init(void) { /* Enable clocks */ - REG_WRITE_MLV(GR_PMU_PERICLKSET0, - GC_PMU_PERICLKSET0_DWATCHDOG0_MASK, - GC_PMU_PERICLKSET0_DWATCHDOG0_LSB, 1); + /* TODO_FPGA add relevant clock init here, when supported. */ /* Unlock watchdog registers */ GR_WATCHDOG_LOCK = WATCHDOG_MAGIC_WORD; |