diff options
| author | Alec Berg <alecaberg@chromium.org> | 2014-09-25 10:03:36 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-09-25 22:49:41 +0000 |
| commit | e04f4cce1143250e9005e9f7843e91638e8132fd (patch) | |
| tree | 559ede77f33939f2b756353625a964f3c711830f | |
| parent | 2c00459e19d816dde993a47d3adc647fb7dd2dd1 (diff) | |
| download | chrome-ec-e04f4cce1143250e9005e9f7843e91638e8132fd.tar.gz | |
stm32f0: enable flash prefetch buffer
Enable flash prefetch buffer for stm32f0 chips to make for
faster CPU execution.
BUG=none
BRANCH=none
TEST=load onto samus_pd and zinger. let run for a while.
connect/disconnect AC a few times. boot samus.
Change-Id: I88c0ae67a3205987344552f5b44952f9890c8177
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219921
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
| -rw-r--r-- | board/zinger/hardware.c | 7 | ||||
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 7 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 1 |
3 files changed, 11 insertions, 4 deletions
diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c index 7e2cb013ea..1358220ee3 100644 --- a/board/zinger/hardware.c +++ b/board/zinger/hardware.c @@ -17,8 +17,11 @@ static void clock_init(void) { - /* put 1 Wait-State for flash access to ensure proper reads at 48Mhz */ - STM32_FLASH_ACR = 0x1001; /* 1 WS / Prefetch enabled */ + /* + * put 1 Wait-State for flash access to ensure proper reads at 48Mhz + * and enable prefetch buffer. + */ + STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN; /* Ensure that HSI8 is ON */ if (!(STM32_RCC_CR & (1 << 1))) { diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index bcb72fa070..b43a442f02 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -389,8 +389,11 @@ void clock_init(void) * PLL unlocked, RTC enabled on LSE */ - /* put 1 Wait-State for flash access to ensure proper reads at 48Mhz */ - STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY; /* 1 WS / Prefetch enabled */ + /* + * put 1 Wait-State for flash access to ensure proper reads at 48Mhz + * and enable prefetch buffer. + */ + STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN; config_hispeed_clock(); diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 79c2e54934..3f519e9345 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -814,6 +814,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY (1 << 0) +#define STM32_FLASH_ACR_PRFTEN (1 << 4) #define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) #define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) #define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) |